void tick_start(unsigned int interval_in_ms)
{
ccm_module_clock_gating(CG_EPIT1, CGM_ON_RUN_WAIT); /* EPIT1 module
clock ON - before writing
regs! */
EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable the counter */
CCM_WIMR0 &= ~CCM_WIMR0_IPI_INT_EPIT1; /* Clear wakeup mask */
/* mcu_main_clk = 528MHz = 27MHz * 2 * ((9 + 7/9) / 1)
* CLKSRC = ipg_clk = 528MHz / 4 / 2 = 66MHz,
* EPIT Output Disconnected,
* Enabled in wait mode
* Prescale 1/2640 for 25KHz
* Reload from modulus register,
* Compare interrupt enabled,
* Count from load value */
EPITCR1 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW |
((2640-1) << EPITCR_PRESCALER_POS) | EPITCR_RLD |
EPITCR_OCIEN | EPITCR_ENMOD;
EPITLR1 = interval_in_ms*25; /* Count down from interval */
EPITCMPR1 = 0; /* Event when counter reaches 0 */
EPITSR1 = EPITSR_OCIF; /* Clear any pending interrupt */
avic_enable_int(INT_EPIT1, INT_TYPE_IRQ, INT_PRIO_DEFAULT,
EPIT1_HANDLER);
EPITCR1 |= EPITCR_EN; /* Enable the counter */
}
void usb_drv_int_enable(bool enable)
{
if (enable)
{
avic_enable_int(INT_USB_OTG, INT_TYPE_IRQ, INT_PRIO_DEFAULT,
USB_OTG_HANDLER);
}
else
{
avic_disable_int(INT_USB_OTG);
}
}
bool timer_start(void)
{
int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
/* Halt timer if running - leave module clock enabled */
stop_timer(false);
/* Enable interrupt */
EPITCR2 |= EPITCR_OCIEN;
avic_enable_int(INT_EPIT2, INT_TYPE_IRQ, INT_PRIO_DEFAULT,
EPIT2_HANDLER);
/* Start timer */
EPITCR2 |= EPITCR_EN;
restore_interrupt(oldstatus);
return true;
}
/** Public routines **/
void INIT_ATTR sdma_init(void)
{
int i;
unsigned long acr;
ccm_module_clock_gating(CG_SDMA, CGM_ON_RUN_WAIT);
/* Reset the controller */
SDMA_RESET |= SDMA_RESET_RESET;
while (SDMA_RESET & SDMA_RESET_RESET);
/* No channel enabled, all priorities 0 */
for (i = 0; i < CH_NUM; i++)
{
SDMA_CHNENBL(i) = 0;
SDMA_CHNPRI(i) = 0;
}
/* Ensure no ints pending */
SDMA_INTR = 0xffffffff;
/* Nobody owns any channel (yet) */
SDMA_HOSTOVR = 0xffffffff;
SDMA_DSPOVR = 0xffffffff;
SDMA_EVTOVR = 0xffffffff;
SDMA_MC0PTR = 0x00000000;
/* 32-word channel contexts, use default bootscript address */
SDMA_CHN0ADDR = SDMA_CHN0ADDR_SMSZ | 0x0050;
avic_enable_int(INT_SDMA, INT_TYPE_IRQ, INT_PRIO_SDMA, SDMA_HANDLER);
/* SDMA core must run at the proper frequency based upon the AHB/IPG
* ratio */
acr = (ccm_get_ahb_clk() / ccm_get_ipg_clk()) < 2 ? SDMA_CONFIG_ACR : 0;
/* No dsp, no debug
* Static context switching - TLSbo86520L SW Workaround for SDMA Chnl0
* access issue */
SDMA_CONFIG = acr;
/* Tell SDMA where the host channel table is */
SDMA_MC0PTR = (unsigned long)ccb_array;
ccb_array[0].status.opened_init = 1;
ccb_array[0].curr_bd_ptr = &c0_buffer_desc.bd;
ccb_array[0].base_bd_ptr = &c0_buffer_desc.bd;
ccb_array[0].channel_desc = NULL; /* No channel descriptor */
/* Command channel owned by AP */
set_channel_ownership(0, CH_OWNSHP_MCU);
sdma_channel_set_priority(0, 1);
/* Load SDMA script code */
set_buffer_descriptor(&c0_buffer_desc.bd,
C0_SETPM,
BD_DONE | BD_WRAP | BD_EXTD,
RAM_CODE_SIZE,
(void *)addr_virt_to_phys(MCU_START_ADDR),
(void *)RAM_CODE_START_ADDR);
SDMA_HSTART = 1ul;
sdma_channel_wait_nonblocking(0);
/* No dsp, no debug, dynamic context switching */
SDMA_CONFIG = acr | SDMA_CONFIG_CSM_DYNAMIC;
}
