/**
* axienet_mdio_write - MDIO interface write function
* @bus: Pointer to mii bus structure
* @phy_id: Address of the PHY device
* @reg: PHY register to write to
* @val: Value to be written into the register
*
* returns: 0 on success, -ETIMEDOUT on a timeout
*
* Writes the value to the requested register by first writing the value
* into MWD register. The the MCR register is then appropriately setup
* to finish the write operation.
*/
static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg,
u16 val)
{
int ret;
struct axienet_local *lp = bus->priv;
dev_dbg(lp->dev, "axienet_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
phy_id, reg, val);
ret = axienet_mdio_wait_until_ready(lp);
if (ret < 0)
return ret;
axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32) val);
axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
(((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
XAE_MDIO_MCR_PHYAD_MASK) |
((reg << XAE_MDIO_MCR_REGAD_SHIFT) &
XAE_MDIO_MCR_REGAD_MASK) |
XAE_MDIO_MCR_INITIATE_MASK |
XAE_MDIO_MCR_OP_WRITE_MASK));
ret = axienet_mdio_wait_until_ready(lp);
if (ret < 0)
return ret;
return 0;
}
/**
* axienet_mdio_read - MDIO interface read function
* @bus: Pointer to mii bus structure
* @phy_id: Address of the PHY device
* @reg: PHY register to read
*
* returns: The register contents on success, -ETIMEDOUT on a timeout
*
* Reads the contents of the requested register from the requested PHY
* address by first writing the details into MCR register. After a while
* the register MRD is read to obtain the PHY register content.
*/
static int axienet_mdio_read(struct mii_bus *bus, int phy_id, int reg)
{
u32 rc;
int ret;
struct axienet_local *lp = bus->priv;
ret = axienet_mdio_wait_until_ready(lp);
if (ret < 0)
return ret;
axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
(((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
XAE_MDIO_MCR_PHYAD_MASK) |
((reg << XAE_MDIO_MCR_REGAD_SHIFT) &
XAE_MDIO_MCR_REGAD_MASK) |
XAE_MDIO_MCR_INITIATE_MASK |
XAE_MDIO_MCR_OP_READ_MASK));
ret = axienet_mdio_wait_until_ready(lp);
if (ret < 0)
return ret;
rc = axienet_ior(lp, XAE_MDIO_MRD_OFFSET) & 0x0000FFFF;
dev_dbg(lp->dev, "axienet_mdio_read(phy_id=%i, reg=%x) == %x\n",
phy_id, reg, rc);
return rc;
}
/**
* axienet_set_multicast_list - Prepare the multicast table
* @ndev: Pointer to the net_device structure
*
* This function is called to initialize the multicast table during
* initialization. The Axi Ethernet basic multicast support has a four-entry
* multicast table which is initialized here. Additionally this function
* goes into the net_device_ops structure entry ndo_set_multicast_list. This
* means whenever the multicast table entries need to be updated this
* function gets called.
*/
static void axienet_set_multicast_list(struct net_device *ndev)
{
int i;
u32 reg, af0reg, af1reg;
struct axienet_local *lp = netdev_priv(ndev);
if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
netdev_mc_count(ndev) > XAE_MULTICAST_CAM_TABLE_NUM) {
/* We must make the kernel realize we had to move into
* promiscuous mode. If it was a promiscuous mode request
* the flag is already set. If not we set it.
*/
ndev->flags |= IFF_PROMISC;
reg = axienet_ior(lp, XAE_FMI_OFFSET);
reg |= XAE_FMI_PM_MASK;
axienet_iow(lp, XAE_FMI_OFFSET, reg);
dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
} else if (!netdev_mc_empty(ndev)) {
struct netdev_hw_addr *ha;
i = 0;
netdev_for_each_mc_addr(ha, ndev) {
if (i >= XAE_MULTICAST_CAM_TABLE_NUM)
break;
af0reg = (ha->addr[0]);
af0reg |= (ha->addr[1] << 8);
af0reg |= (ha->addr[2] << 16);
af0reg |= (ha->addr[3] << 24);
af1reg = (ha->addr[4]);
af1reg |= (ha->addr[5] << 8);
reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
reg |= i;
axienet_iow(lp, XAE_FMI_OFFSET, reg);
axienet_iow(lp, XAE_AF0_OFFSET, af0reg);
axienet_iow(lp, XAE_AF1_OFFSET, af1reg);
i++;
}
} else {
/**
* axienet_set_mac_address - Write the MAC address
* @ndev: Pointer to the net_device structure
* @address: 6 byte Address to be written as MAC address
*
* This function is called to initialize the MAC address of the Axi Ethernet
* core. It writes to the UAW0 and UAW1 registers of the core.
*/
static void axienet_set_mac_address(struct net_device *ndev, void *address)
{
struct axienet_local *lp = netdev_priv(ndev);
if (address)
memcpy(ndev->dev_addr, address, ETH_ALEN);
if (!is_valid_ether_addr(ndev->dev_addr))
random_ether_addr(ndev->dev_addr);
axienet_iow(lp, XAE_UAW0_OFFSET,
(ndev->dev_addr[0]) |
(ndev->dev_addr[1] << 8) |
(ndev->dev_addr[2] << 16) |
(ndev->dev_addr[3] << 24));
axienet_iow(lp, XAE_UAW1_OFFSET,
(((axienet_ior(lp, XAE_UAW1_OFFSET)) &
~XAE_UAW1_UNICASTADDR_MASK) |
(ndev->dev_addr[4] |
(ndev->dev_addr[5] << 8))));
}
/**
* axienet_set_mac_address - Write the MAC address
* @ndev: Pointer to the net_device structure
* @address: 6 byte Address to be written as MAC address
*
* This function is called to initialize the MAC address of the Axi Ethernet
* core. It writes to the UAW0 and UAW1 registers of the core.
*/
static void axienet_set_mac_address(struct net_device *ndev,
const void *address)
{
struct axienet_local *lp = netdev_priv(ndev);
if (address)
memcpy(ndev->dev_addr, address, ETH_ALEN);
if (!is_valid_ether_addr(ndev->dev_addr))
eth_hw_addr_random(ndev);
/* Set up unicast MAC address filter set its mac address */
axienet_iow(lp, XAE_UAW0_OFFSET,
(ndev->dev_addr[0]) |
(ndev->dev_addr[1] << 8) |
(ndev->dev_addr[2] << 16) |
(ndev->dev_addr[3] << 24));
axienet_iow(lp, XAE_UAW1_OFFSET,
(((axienet_ior(lp, XAE_UAW1_OFFSET)) &
~XAE_UAW1_UNICASTADDR_MASK) |
(ndev->dev_addr[4] |
(ndev->dev_addr[5] << 8))));
}
/**
* axienet_mdio_setup - MDIO setup function
* @lp: Pointer to axienet local data structure.
* @np: Pointer to device node
*
* returns: 0 on success, -ETIMEDOUT on a timeout, -ENOMEM when
* mdiobus_alloc (to allocate memory for mii bus structure) fails.
*
* Sets up the MDIO interface by initializing the MDIO clock and enabling the
* MDIO interface in hardware. Register the MDIO interface.
**/
int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np)
{
int ret;
u32 clk_div, host_clock;
u32 *property_p;
struct mii_bus *bus;
struct resource res;
struct device_node *np1;
/* clk_div can be calculated by deriving it from the equation:
* fMDIO = fHOST / ((1 + clk_div) * 2)
*
* Where fMDIO <= 2500000, so we get:
* fHOST / ((1 + clk_div) * 2) <= 2500000
*
* Then we get:
* 1 / ((1 + clk_div) * 2) <= (2500000 / fHOST)
*
* Then we get:
* 1 / (1 + clk_div) <= ((2500000 * 2) / fHOST)
*
* Then we get:
* 1 / (1 + clk_div) <= (5000000 / fHOST)
*
* So:
* (1 + clk_div) >= (fHOST / 5000000)
*
* And finally:
* clk_div >= (fHOST / 5000000) - 1
*
* fHOST can be read from the flattened device tree as property
* "clock-frequency" from the CPU
*/
np1 = of_find_node_by_name(NULL, "cpu");
if (!np1) {
printk(KERN_WARNING "%s(): Could not find CPU device node.",
__func__);
printk(KERN_WARNING "Setting MDIO clock divisor to "
"default %d\n", DEFAULT_CLOCK_DIVISOR);
clk_div = DEFAULT_CLOCK_DIVISOR;
goto issue;
}
property_p = (u32 *) of_get_property(np1, "clock-frequency", NULL);
if (!property_p) {
printk(KERN_WARNING "%s(): Could not find CPU property: "
"clock-frequency.", __func__);
printk(KERN_WARNING "Setting MDIO clock divisor to "
"default %d\n", DEFAULT_CLOCK_DIVISOR);
clk_div = DEFAULT_CLOCK_DIVISOR;
of_node_put(np1);
goto issue;
}
host_clock = be32_to_cpup(property_p);
clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1;
/* If there is any remainder from the division of
* fHOST / (MAX_MDIO_FREQ * 2), then we need to add
* 1 to the clock divisor or we will surely be above 2.5 MHz */
if (host_clock % (MAX_MDIO_FREQ * 2))
clk_div++;
printk(KERN_DEBUG "%s(): Setting MDIO clock divisor to %u based "
"on %u Hz host clock.\n", __func__, clk_div, host_clock);
of_node_put(np1);
issue:
axienet_iow(lp, XAE_MDIO_MC_OFFSET,
(((u32) clk_div) | XAE_MDIO_MC_MDIOEN_MASK));
ret = axienet_mdio_wait_until_ready(lp);
if (ret < 0)
return ret;
bus = mdiobus_alloc();
if (!bus)
return -ENOMEM;
np1 = of_get_parent(lp->phy_node);
of_address_to_resource(np1, 0, &res);
snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
(unsigned long long) res.start);
bus->priv = lp;
bus->name = "Xilinx Axi Ethernet MDIO";
bus->read = axienet_mdio_read;
bus->write = axienet_mdio_write;
bus->parent = lp->dev;
bus->irq = lp->mdio_irqs; /* preallocated IRQ table */
lp->mii_bus = bus;
ret = of_mdiobus_register(bus, np1);
if (ret) {
mdiobus_free(bus);
return ret;
}
return 0;
}
/**
* axienet_mdio_setup - MDIO setup function
* @lp: Pointer to axienet local data structure.
* @np: Pointer to device node
*
* returns: 0 on success, -ETIMEDOUT on a timeout, -ENOMEM when
* mdiobus_alloc (to allocate memory for mii bus structure) fails.
*
* Sets up the MDIO interface by initializing the MDIO clock and enabling the
* MDIO interface in hardware. Register the MDIO interface.
**/
int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np)
{
int ret;
u32 clk_div;
struct mii_bus *bus;
struct resource res;
struct device_node *np1;
struct device_node *npp = 0; /* the ethernet controller device node */
/* clk_div can be calculated by deriving it from the equation:
* fMDIO = fHOST / ((1 + clk_div) * 2)
*
* Where fMDIO <= 2500000, so we get:
* fHOST / ((1 + clk_div) * 2) <= 2500000
*
* Then we get:
* 1 / ((1 + clk_div) * 2) <= (2500000 / fHOST)
*
* Then we get:
* 1 / (1 + clk_div) <= ((2500000 * 2) / fHOST)
*
* Then we get:
* 1 / (1 + clk_div) <= (5000000 / fHOST)
*
* So:
* (1 + clk_div) >= (fHOST / 5000000)
*
* And finally:
* clk_div >= (fHOST / 5000000) - 1
*
* fHOST can be read from the flattened device tree as property
* "clock-frequency" from the CPU
*/
np1 = of_get_parent(lp->phy_node);
if (np1)
npp = of_get_parent(np1);
if (!npp) {
dev_warn(lp->dev,
"Could not find ethernet controller device node.");
dev_warn(lp->dev, "Setting MDIO clock divisor to default %d\n",
DEFAULT_CLOCK_DIVISOR);
clk_div = DEFAULT_CLOCK_DIVISOR;
} else {
u32 *property_p;
property_p = (uint32_t *)of_get_property(npp,
"clock-frequency", NULL);
if (!property_p) {
dev_warn(lp->dev, "Could not find clock ethernet " \
"controller property.");
dev_warn(lp->dev,
"Setting MDIO clock divisor to default %d\n",
DEFAULT_CLOCK_DIVISOR);
clk_div = DEFAULT_CLOCK_DIVISOR;
} else {
u32 host_clock = be32_to_cpup(property_p);
clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1;
/* If there is any remainder from the division of
* fHOST / (MAX_MDIO_FREQ * 2), then we need to add 1
* to the clock divisor or we will surely be
* above 2.5 MHz */
if (host_clock % (MAX_MDIO_FREQ * 2))
clk_div++;
dev_dbg(lp->dev, "Setting MDIO clock divisor to %u " \
"based on %u Hz host clock.\n",
clk_div, host_clock);
}
}
axienet_iow(lp, XAE_MDIO_MC_OFFSET, (((u32)clk_div) |
XAE_MDIO_MC_MDIOEN_MASK));
ret = axienet_mdio_wait_until_ready(lp);
if (ret < 0)
return ret;
bus = mdiobus_alloc();
if (!bus)
return -ENOMEM;
of_address_to_resource(npp, 0, &res);
snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
(unsigned long long) res.start);
bus->priv = lp;
bus->name = "Xilinx Axi Ethernet MDIO";
bus->read = axienet_mdio_read;
bus->write = axienet_mdio_write;
bus->parent = lp->dev;
bus->irq = lp->mdio_irqs; /* preallocated IRQ table */
lp->mii_bus = bus;
ret = of_mdiobus_register(bus, np1);
if (ret) {
mdiobus_free(bus);
return ret;
}
return 0;
}
