/* Calibrate resistors in LPF of PLL? */ static void b43_radio_2059_rcal(struct b43_wldev *dev) { /* Enable */ b43_radio_set(dev, R2059_C3 | R2059_RCAL_CONFIG, 0x1); usleep_range(10, 20); b43_radio_set(dev, R2059_C3 | 0x0BF, 0x1); b43_radio_maskset(dev, R2059_C3 | 0x19B, 0x3, 0x2); /* Start */ b43_radio_set(dev, R2059_C3 | R2059_RCAL_CONFIG, 0x2); usleep_range(100, 200); /* Stop */ b43_radio_mask(dev, R2059_C3 | R2059_RCAL_CONFIG, ~0x2); if (!b43_radio_wait_value(dev, R2059_C3 | R2059_RCAL_STATUS, 1, 1, 100, 1000000)) b43err(dev->wl, "Radio 0x2059 rcal timeout\n"); /* Disable */ b43_radio_mask(dev, R2059_C3 | R2059_RCAL_CONFIG, ~0x1); b43_radio_set(dev, 0xa, 0x60); }
static void b43_radio_2059_init(struct b43_wldev *dev) { const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3 }; int i; /* Prepare (reset?) radio */ b43_radio_2059_init_pre(dev); r2059_upload_inittabs(dev); for (i = 0; i < ARRAY_SIZE(routing); i++) b43_radio_set(dev, routing[i] | 0x146, 0x3); /* Post init starts below */ b43_radio_set(dev, R2059_RFPLL_MISC_CAL_RESETN, 0x0078); b43_radio_set(dev, R2059_XTAL_CONFIG2, 0x0080); msleep(2); b43_radio_mask(dev, R2059_RFPLL_MISC_CAL_RESETN, ~0x0078); b43_radio_mask(dev, R2059_XTAL_CONFIG2, ~0x0080); if (1) { /* FIXME */ b43_radio_2059_rcal(dev); b43_radio_2057_rccal(dev); } b43_radio_mask(dev, R2059_RFPLL_MASTER, ~0x0008); }
static void b43_radio_2059_channel_setup(struct b43_wldev *dev, const struct b43_phy_ht_channeltab_e_radio2059 *e) { u8 i; u16 routing; b43_radio_write(dev, 0x16, e->radio_syn16); b43_radio_write(dev, 0x17, e->radio_syn17); b43_radio_write(dev, 0x22, e->radio_syn22); b43_radio_write(dev, 0x25, e->radio_syn25); b43_radio_write(dev, 0x27, e->radio_syn27); b43_radio_write(dev, 0x28, e->radio_syn28); b43_radio_write(dev, 0x29, e->radio_syn29); b43_radio_write(dev, 0x2c, e->radio_syn2c); b43_radio_write(dev, 0x2d, e->radio_syn2d); b43_radio_write(dev, 0x37, e->radio_syn37); b43_radio_write(dev, 0x41, e->radio_syn41); b43_radio_write(dev, 0x43, e->radio_syn43); b43_radio_write(dev, 0x47, e->radio_syn47); b43_radio_write(dev, 0x4a, e->radio_syn4a); b43_radio_write(dev, 0x58, e->radio_syn58); b43_radio_write(dev, 0x5a, e->radio_syn5a); b43_radio_write(dev, 0x6a, e->radio_syn6a); b43_radio_write(dev, 0x6d, e->radio_syn6d); b43_radio_write(dev, 0x6e, e->radio_syn6e); b43_radio_write(dev, 0x92, e->radio_syn92); b43_radio_write(dev, 0x98, e->radio_syn98); for (i = 0; i < 2; i++) { routing = i ? R2059_RXRX1 : R2059_TXRX0; b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a); b43_radio_write(dev, routing | 0x58, e->radio_rxtx58); b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a); b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a); b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d); b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e); b43_radio_write(dev, routing | 0x92, e->radio_rxtx92); b43_radio_write(dev, routing | 0x98, e->radio_rxtx98); } udelay(50); /* Calibration */ b43_radio_mask(dev, 0x2b, ~0x1); b43_radio_mask(dev, 0x2e, ~0x4); b43_radio_set(dev, 0x2e, 0x4); b43_radio_set(dev, 0x2b, 0x1); udelay(300); }
/* wlc_radio_2064_init */ static void b43_radio_2064_init(struct b43_wldev *dev) { if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { b43_radio_write(dev, 0x09c, 0x0020); b43_radio_write(dev, 0x105, 0x0008); } else { /* TODO */ } b43_radio_write(dev, 0x032, 0x0062); b43_radio_write(dev, 0x033, 0x0019); b43_radio_write(dev, 0x090, 0x0010); b43_radio_write(dev, 0x010, 0x0000); if (dev->phy.rev == 1) { b43_radio_write(dev, 0x060, 0x007f); b43_radio_write(dev, 0x061, 0x0072); b43_radio_write(dev, 0x062, 0x007f); } b43_radio_write(dev, 0x01d, 0x0002); b43_radio_write(dev, 0x01e, 0x0006); b43_phy_write(dev, 0x4ea, 0x4688); b43_phy_maskset(dev, 0x4eb, ~0x7, 0x2); b43_phy_mask(dev, 0x4eb, ~0x01c0); b43_phy_maskset(dev, 0x46a, 0xff00, 0x19); b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x55), 0); b43_radio_mask(dev, 0x05b, (u16) ~0xff02); b43_radio_set(dev, 0x004, 0x40); b43_radio_set(dev, 0x120, 0x10); b43_radio_set(dev, 0x078, 0x80); b43_radio_set(dev, 0x129, 0x2); b43_radio_set(dev, 0x057, 0x1); b43_radio_set(dev, 0x05b, 0x2); /* TODO: wait for some bit to be set */ b43_radio_read(dev, 0x05c); b43_radio_mask(dev, 0x05b, (u16) ~0xff02); b43_radio_mask(dev, 0x057, (u16) ~0xff01); b43_phy_write(dev, 0x933, 0x2d6b); b43_phy_write(dev, 0x934, 0x2d6b); b43_phy_write(dev, 0x935, 0x2d6b); b43_phy_write(dev, 0x936, 0x2d6b); b43_phy_write(dev, 0x937, 0x016b); b43_radio_mask(dev, 0x057, (u16) ~0xff02); b43_radio_write(dev, 0x0c2, 0x006f); }
/* Calibrate the internal RC oscillator? */ static void b43_radio_2057_rccal(struct b43_wldev *dev) { const u16 radio_values[3][2] = { { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 }, }; int i; for (i = 0; i < 3; i++) { b43_radio_write(dev, R2059_RCCAL_MASTER, radio_values[i][0]); b43_radio_write(dev, R2059_RCCAL_X1, 0x6E); b43_radio_write(dev, R2059_RCCAL_TRC0, radio_values[i][1]); /* Start */ b43_radio_write(dev, R2059_RCCAL_START_R1_Q1_P1, 0x55); /* Wait */ if (!b43_radio_wait_value(dev, R2059_RCCAL_DONE_OSCCAP, 2, 2, 500, 5000000)) b43err(dev->wl, "Radio 0x2059 rccal timeout\n"); /* Stop */ b43_radio_write(dev, R2059_RCCAL_START_R1_Q1_P1, 0x15); } b43_radio_mask(dev, R2059_RCCAL_MASTER, ~0x1); }
static void b43_radio_init2055_post(struct b43_wldev *dev) { struct ssb_sprom *sprom = &(dev->dev->bus->sprom); struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo); int i; u16 val; b43_radio_mask(dev, B2055_MASTER1, 0xFFF3); msleep(1); if ((sprom->revision != 4) || !(sprom->boardflags_hi & B43_BFH_RSSIINV)) { if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) || (binfo->type != 0x46D) || (binfo->rev < 0x41)) { b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F); b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F); msleep(1); } } b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C); msleep(1); b43_radio_write16(dev, B2055_CAL_MISC, 0x3C); msleep(1); b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE); msleep(1); b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80); msleep(1); b43_radio_set(dev, B2055_CAL_MISC, 0x1); msleep(1); b43_radio_set(dev, B2055_CAL_MISC, 0x40); msleep(1); for (i = 0; i < 100; i++) { val = b43_radio_read16(dev, B2055_CAL_COUT2); if (val & 0x80) break; udelay(10); } msleep(1); b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F); msleep(1); nphy_channel_switch(dev, dev->phy.channel); b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9); b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9); b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83); b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83); }
static void b43_radio_2059_channel_setup(struct b43_wldev *dev, const struct b43_phy_ht_channeltab_e_radio2059 *e) { static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3, }; u16 r; int core; b43_radio_write(dev, 0x16, e->radio_syn16); b43_radio_write(dev, 0x17, e->radio_syn17); b43_radio_write(dev, 0x22, e->radio_syn22); b43_radio_write(dev, 0x25, e->radio_syn25); b43_radio_write(dev, 0x27, e->radio_syn27); b43_radio_write(dev, 0x28, e->radio_syn28); b43_radio_write(dev, 0x29, e->radio_syn29); b43_radio_write(dev, 0x2c, e->radio_syn2c); b43_radio_write(dev, 0x2d, e->radio_syn2d); b43_radio_write(dev, 0x37, e->radio_syn37); b43_radio_write(dev, 0x41, e->radio_syn41); b43_radio_write(dev, 0x43, e->radio_syn43); b43_radio_write(dev, 0x47, e->radio_syn47); for (core = 0; core < 3; core++) { r = routing[core]; b43_radio_write(dev, r | 0x4a, e->radio_rxtx4a); b43_radio_write(dev, r | 0x58, e->radio_rxtx58); b43_radio_write(dev, r | 0x5a, e->radio_rxtx5a); b43_radio_write(dev, r | 0x6a, e->radio_rxtx6a); b43_radio_write(dev, r | 0x6d, e->radio_rxtx6d); b43_radio_write(dev, r | 0x6e, e->radio_rxtx6e); b43_radio_write(dev, r | 0x92, e->radio_rxtx92); b43_radio_write(dev, r | 0x98, e->radio_rxtx98); } udelay(50); /* Calibration */ b43_radio_mask(dev, R2059_RFPLL_MISC_EN, ~0x1); b43_radio_mask(dev, R2059_RFPLL_MISC_CAL_RESETN, ~0x4); b43_radio_set(dev, R2059_RFPLL_MISC_CAL_RESETN, 0x4); b43_radio_set(dev, R2059_RFPLL_MISC_EN, 0x1); udelay(300); }
static void aphy_channel_switch(struct b43_wldev *dev, unsigned int channel) { u16 freq, r8, tmp; freq = channel2freq_a(channel); r8 = b43_radio_read16(dev, 0x0008); b43_write16(dev, 0x03F0, freq); b43_radio_write16(dev, 0x0008, r8); //TODO: write max channel TX power? to Radio 0x2D tmp = b43_radio_read16(dev, 0x002E); tmp &= 0x0080; //TODO: OR tmp with the Power out estimation for this channel? b43_radio_write16(dev, 0x002E, tmp); if (freq >= 4920 && freq <= 5500) { /* * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F; * = (freq * 0.025862069 */ r8 = 3 * freq / 116; /* is equal to r8 = freq * 0.025862 */ } b43_radio_write16(dev, 0x0007, (r8 << 4) | r8); b43_radio_write16(dev, 0x0020, (r8 << 4) | r8); b43_radio_write16(dev, 0x0021, (r8 << 4) | r8); b43_radio_maskset(dev, 0x0022, 0x000F, (r8 << 4)); b43_radio_write16(dev, 0x002A, (r8 << 4)); b43_radio_write16(dev, 0x002B, (r8 << 4)); b43_radio_maskset(dev, 0x0008, 0x00F0, (r8 << 4)); b43_radio_maskset(dev, 0x0029, 0xFF0F, 0x00B0); b43_radio_write16(dev, 0x0035, 0x00AA); b43_radio_write16(dev, 0x0036, 0x0085); b43_radio_maskset(dev, 0x003A, 0xFF20, freq_r3A_value(freq)); b43_radio_mask(dev, 0x003D, 0x00FF); b43_radio_maskset(dev, 0x0081, 0xFF7F, 0x0080); b43_radio_mask(dev, 0x0035, 0xFFEF); b43_radio_maskset(dev, 0x0035, 0xFFEF, 0x0010); b43_radio_set_tx_iq(dev); //TODO: TSSI2dbm workaround //FIXME b43_phy_xmitpower(dev); }
static void aphy_channel_switch(struct b43_wldev *dev, unsigned int channel) { u16 freq, r8, tmp; freq = channel2freq_a(channel); r8 = b43_radio_read16(dev, 0x0008); b43_write16(dev, 0x03F0, freq); b43_radio_write16(dev, 0x0008, r8); tmp = b43_radio_read16(dev, 0x002E); tmp &= 0x0080; b43_radio_write16(dev, 0x002E, tmp); if (freq >= 4920 && freq <= 5500) { r8 = 3 * freq / 116; } b43_radio_write16(dev, 0x0007, (r8 << 4) | r8); b43_radio_write16(dev, 0x0020, (r8 << 4) | r8); b43_radio_write16(dev, 0x0021, (r8 << 4) | r8); b43_radio_maskset(dev, 0x0022, 0x000F, (r8 << 4)); b43_radio_write16(dev, 0x002A, (r8 << 4)); b43_radio_write16(dev, 0x002B, (r8 << 4)); b43_radio_maskset(dev, 0x0008, 0x00F0, (r8 << 4)); b43_radio_maskset(dev, 0x0029, 0xFF0F, 0x00B0); b43_radio_write16(dev, 0x0035, 0x00AA); b43_radio_write16(dev, 0x0036, 0x0085); b43_radio_maskset(dev, 0x003A, 0xFF20, freq_r3A_value(freq)); b43_radio_mask(dev, 0x003D, 0x00FF); b43_radio_maskset(dev, 0x0081, 0xFF7F, 0x0080); b43_radio_mask(dev, 0x0035, 0xFFEF); b43_radio_maskset(dev, 0x0035, 0xFFEF, 0x0010); b43_radio_set_tx_iq(dev); }
/* wlc_lcnphy_bu_tweaks */ static void b43_phy_lcn_bu_tweaks(struct b43_wldev *dev) { b43_phy_set(dev, 0x805, 0x1); b43_phy_maskset(dev, 0x42f, ~0x7, 0x3); b43_phy_maskset(dev, 0x030, ~0x7, 0x3); b43_phy_write(dev, 0x414, 0x1e10); b43_phy_write(dev, 0x415, 0x0640); b43_phy_maskset(dev, 0x4df, (u16) ~0xff00, 0xf700); b43_phy_set(dev, 0x44a, 0x44); b43_phy_write(dev, 0x44a, 0x80); b43_phy_maskset(dev, 0x434, ~0xff, 0xfd); b43_phy_maskset(dev, 0x420, ~0xff, 0x10); if (dev->dev->bus_sprom->board_rev >= 0x1204) b43_radio_set(dev, 0x09b, 0xf0); b43_phy_write(dev, 0x7d6, 0x0902); b43_phy_maskset(dev, 0x429, ~0xf, 0x9); b43_phy_maskset(dev, 0x429, ~(0x3f << 4), 0xe << 4); if (dev->phy.rev == 1) { b43_phy_maskset(dev, 0x423, ~0xff, 0x46); b43_phy_maskset(dev, 0x411, ~0xff, 1); b43_phy_set(dev, 0x434, 0xff); /* FIXME: update to wl */ /* TODO: wl operates on PHY 0x416, brcmsmac is outdated here */ b43_phy_maskset(dev, 0x656, ~0xf, 2); b43_phy_set(dev, 0x44d, 4); b43_radio_set(dev, 0x0f7, 0x4); b43_radio_mask(dev, 0x0f1, ~0x3); b43_radio_maskset(dev, 0x0f2, ~0xf8, 0x90); b43_radio_maskset(dev, 0x0f3, ~0x3, 0x2); b43_radio_maskset(dev, 0x0f3, ~0xf0, 0xa0); b43_radio_set(dev, 0x11f, 0x2); b43_phy_lcn_clear_tx_power_offsets(dev); /* TODO: something more? */ } }
static void b43_phy_ww(struct b43_wldev *dev) { u16 b, curr_s, best_s = 0xFFFF; int i; b43_phy_mask(dev, B43_PHY_CRS0, ~B43_PHY_CRS0_EN); b43_phy_set(dev, B43_PHY_OFDM(0x1B), 0x1000); b43_phy_maskset(dev, B43_PHY_OFDM(0x82), 0xF0FF, 0x0300); b43_radio_set(dev, 0x0009, 0x0080); b43_radio_maskset(dev, 0x0012, 0xFFFC, 0x0002); b43_wa_initgains(dev); b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5); b = b43_phy_read(dev, B43_PHY_PWRDOWN); b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005); b43_radio_set(dev, 0x0004, 0x0004); for (i = 0x10; i <= 0x20; i++) { b43_radio_write16(dev, 0x0013, i); curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF; if (!curr_s) { best_s = 0x0000; break; } else if (curr_s >= 0x0080) curr_s = 0x0100 - curr_s; if (curr_s < best_s) best_s = curr_s; } b43_phy_write(dev, B43_PHY_PWRDOWN, b); b43_radio_mask(dev, 0x0004, 0xFFFB); b43_radio_write16(dev, 0x0013, best_s); b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC); b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80); b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00); b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0); b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0); b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF); b43_phy_maskset(dev, B43_PHY_OFDM(0xBB), 0xF000, 0x0053); b43_phy_maskset(dev, B43_PHY_OFDM61, 0xFE1F, 0x0120); b43_phy_maskset(dev, B43_PHY_OFDM(0x13), 0x0FFF, 0x3000); b43_phy_maskset(dev, B43_PHY_OFDM(0x14), 0x0FFF, 0x3000); b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017); for (i = 0; i < 6; i++) b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F); b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E); b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011); b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013); b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030); b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN); }
static void b43_radio_init2060(struct b43_wldev *dev) { b43_radio_write16(dev, 0x0004, 0x00C0); b43_radio_write16(dev, 0x0005, 0x0008); b43_radio_write16(dev, 0x0009, 0x0040); b43_radio_write16(dev, 0x0005, 0x00AA); b43_radio_write16(dev, 0x0032, 0x008F); b43_radio_write16(dev, 0x0006, 0x008F); b43_radio_write16(dev, 0x0034, 0x008F); b43_radio_write16(dev, 0x002C, 0x0007); b43_radio_write16(dev, 0x0082, 0x0080); b43_radio_write16(dev, 0x0080, 0x0000); b43_radio_write16(dev, 0x003F, 0x00DA); b43_radio_mask(dev, 0x0005, ~0x0008); b43_radio_mask(dev, 0x0081, ~0x0010); b43_radio_mask(dev, 0x0081, ~0x0020); b43_radio_mask(dev, 0x0081, ~0x0020); msleep(1); /* delay 400usec */ b43_radio_maskset(dev, 0x0081, ~0x0020, 0x0010); msleep(1); /* delay 400usec */ b43_radio_maskset(dev, 0x0005, ~0x0008, 0x0008); b43_radio_mask(dev, 0x0085, ~0x0010); b43_radio_mask(dev, 0x0005, ~0x0008); b43_radio_mask(dev, 0x0081, ~0x0040); b43_radio_maskset(dev, 0x0081, ~0x0040, 0x0040); b43_radio_write16(dev, 0x0005, (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008); b43_phy_write(dev, 0x0063, 0xDDC6); b43_phy_write(dev, 0x0069, 0x07BE); b43_phy_write(dev, 0x006A, 0x0000); aphy_channel_switch(dev, dev->phy.ops->get_default_chan(dev)); msleep(1); }
static void b43_radio_2059_init(struct b43_wldev *dev) { const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 }; const u16 radio_values[3][2] = { { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 }, }; u16 i, j; b43_radio_write(dev, R2059_ALL | 0x51, 0x0070); b43_radio_write(dev, R2059_ALL | 0x5a, 0x0003); for (i = 0; i < ARRAY_SIZE(routing); i++) b43_radio_set(dev, routing[i] | 0x146, 0x3); b43_radio_set(dev, 0x2e, 0x0078); b43_radio_set(dev, 0xc0, 0x0080); msleep(2); b43_radio_mask(dev, 0x2e, ~0x0078); b43_radio_mask(dev, 0xc0, ~0x0080); if (1) { /* FIXME */ b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x1); udelay(10); b43_radio_set(dev, R2059_RXRX1 | 0x0BF, 0x1); b43_radio_maskset(dev, R2059_RXRX1 | 0x19B, 0x3, 0x2); b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x2); udelay(100); b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x2); for (i = 0; i < 10000; i++) { if (b43_radio_read(dev, R2059_RXRX1 | 0x145) & 1) { i = 0; break; } udelay(100); } if (i) b43err(dev->wl, "radio 0x945 timeout\n"); b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x1); b43_radio_set(dev, 0xa, 0x60); for (i = 0; i < 3; i++) { b43_radio_write(dev, 0x17F, radio_values[i][0]); b43_radio_write(dev, 0x13D, 0x6E); b43_radio_write(dev, 0x13E, radio_values[i][1]); b43_radio_write(dev, 0x13C, 0x55); for (j = 0; j < 10000; j++) { if (b43_radio_read(dev, 0x140) & 2) { j = 0; break; } udelay(500); } if (j) b43err(dev->wl, "radio 0x140 timeout\n"); b43_radio_write(dev, 0x13C, 0x15); } b43_radio_mask(dev, 0x17F, ~0x1); } b43_radio_mask(dev, 0x11, ~0x0008); }