コード例 #1
0
ファイル: gpio.c プロジェクト: 0s4l/u-boot-xlnx
static void portmux_setup(unsigned short per)
{
	u16 y, offset, muxreg, mask;
	u16 function = P_FUNCT2MUX(per);

	for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
		if (port_mux_lut[y].res == per) {

			/* SET PORTMUX REG */

			offset = port_mux_lut[y].offset;
			muxreg = bfin_read_PORT_MUX();

			if (offset == 1)
				mask = 3;
			else
				mask = 1;

			muxreg &= ~(mask << offset);
			muxreg |= ((function & mask) << offset);
			bfin_write_PORT_MUX(muxreg);
		}
	}
}
コード例 #2
0
ファイル: bfspi.c プロジェクト: netson99/package_bfspi
void bfspi_hardware_init(int baud, u16 new_chip_select_mask) 
{
	u16 ctl_reg, flag;
	int cs, bit;

  	if (baud < 4) {
    		printk("\nkern>>baud = %d may mean SPI clock too fast for Si labs 3050"
	   		"consider baud == 4 or greater", baud);
  	}

	PRINTK("\nkern>> bfspi_spi_init\n");
	PRINTK("kern>>   new_chip_select_mask = 0x%04x\n", new_chip_select_mask);
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
	PRINTK("kern>>   FIOD_DIR = 0x%04x\n", bfin_read_FIO_DIR());
#endif

#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
	PRINTK("  FIOD_DIR = 0x%04x\n", bfin_read_PORTFIO_DIR());
#endif
	/* grab SPISEL/GPIO pins for SPI, keep level of SPISEL pins H */
	chip_select_mask |= new_chip_select_mask;

	flag = 0xff00 | (chip_select_mask & 0xff);

	/* set up chip selects greater than PF7 */

  	if (chip_select_mask & 0xff00) {
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
	  bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (chip_select_mask & 0xff00)); 
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
	bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | (chip_select_mask & 0xff00));
#endif
   	  __builtin_bfin_ssync();
	}
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
	PRINTK("kern>>   After FIOD_DIR = 0x%04x\n", bfin_read_FIO_DIR());
#endif

#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
	PRINTK("  After FIOD_DIR = 0x%04x\n",bfin_read_PORTFIO_DIR());

	/* we need to work thru each bit in mask and set the MUX regs */

	for(bit=0; bit<8; bit++) {
	  if (chip_select_mask & (1<<bit)) {
	    PRINTK("SPI CS bit: %d enabled\n", bit);
	    cs = bit;
	    if (cs == 1) {
	      PRINTK("set for chip select 1\n");
	      bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3c00);
	      __builtin_bfin_ssync();

	    } else if (cs == 2 || cs == 3) {
	      PRINTK("set for chip select 2\n");
	      bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJSE_SPI);
	      __builtin_bfin_ssync();
	      bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
	      __builtin_bfin_ssync();

	    } else if (cs == 4) {
	      bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS4E_SPI);
	      __builtin_bfin_ssync();
	      bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3840);
	      __builtin_bfin_ssync();

	    } else if (cs == 5) {
	      bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS5E_SPI);
	      __builtin_bfin_ssync();
	      bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3820);
	      __builtin_bfin_ssync();

	    } else if (cs == 6) {
	      bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS6E_SPI);
	      __builtin_bfin_ssync();
	      bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3810);
	      __builtin_bfin_ssync();

	    } else if (cs == 7) {
	      bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJCE_SPI);
	      __builtin_bfin_ssync();
	      bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
	      __builtin_bfin_ssync();
	    }
	  }
	}
#endif

  	/* note TIMOD = 00 - reading SPI_RDBR kicks off transfer */
  	//Undefines flags lets patch it for now. BFSI is kind of obsolate. 
	//Will be replaced in teh future
	ctl_reg = 0xD004;   //0101 1100 0000  0100  SPE | MSTR | CPOL | CPHA | SZ;
	ctl_reg |= (spimode << 10);
  	bfin_write_SPI_FLG(flag);
  	bfin_write_SPI_BAUD(baud);
  	bfin_write_SPI_CTL(ctl_reg);
}
コード例 #3
0
ファイル: bfin_spi.c プロジェクト: Aircell/asp-u-boot
static void spi_portmux(struct spi_slave *slave)
{
#if defined(__ADSPBF51x__)
#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func)
	u16 f_mux = bfin_read_PORTF_MUX();
	u16 f_fer = bfin_read_PORTF_FER();
	u16 g_mux = bfin_read_PORTG_MUX();
	u16 g_fer = bfin_read_PORTG_FER();
	u16 h_mux = bfin_read_PORTH_MUX();
	u16 h_fer = bfin_read_PORTH_FER();
	switch (slave->bus) {
	case 0:
		/* set SCK/MISO/MOSI */
		SET_MUX(g, 7, 1);
		g_fer |= PG12 | PG13 | PG14;
		switch (slave->cs) {
			case 1: SET_MUX(f, 2, 1); f_fer |= PF7;  break;
			case 2: /* see G above */ g_fer |= PG15; break;
			case 3: SET_MUX(h, 1, 3); f_fer |= PH4;  break;
			case 4: /* no muxing */   h_fer |= PH8;  break;
			case 5: SET_MUX(g, 1, 3); h_fer |= PG3;  break;
			case 6: /* no muxing */                  break;
			case 7: /* no muxing */                  break;
		}
	case 1:
		/* set SCK/MISO/MOSI */
		SET_MUX(h, 0, 2);
		h_fer |= PH1 | PH2 | PH3;
		switch (slave->cs) {
			case 1: SET_MUX(h, 2, 3); h_fer |= PH6;  break;
			case 2: SET_MUX(f, 0, 3); f_fer |= PF0;  break;
			case 3: SET_MUX(g, 0, 3); g_fer |= PG0;  break;
			case 4: SET_MUX(f, 3, 3); f_fer |= PF8;  break;
			case 5: SET_MUX(g, 6, 3); h_fer |= PG11; break;
			case 6: /* no muxing */                  break;
			case 7: /* no muxing */                  break;
		}
	}
	bfin_write_PORTF_MUX(f_mux);
	bfin_write_PORTF_FER(f_fer);
	bfin_write_PORTG_MUX(g_mux);
	bfin_write_PORTG_FER(g_fer);
	bfin_write_PORTH_MUX(h_mux);
	bfin_write_PORTH_FER(h_fer);
#elif defined(__ADSPBF52x__)
#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func)
	u16 f_mux = bfin_read_PORTF_MUX();
	u16 f_fer = bfin_read_PORTF_FER();
	u16 g_mux = bfin_read_PORTG_MUX();
	u16 g_fer = bfin_read_PORTG_FER();
	u16 h_mux = bfin_read_PORTH_MUX();
	u16 h_fer = bfin_read_PORTH_FER();
	/* set SCK/MISO/MOSI */
	SET_MUX(g, 0, 3);
	g_fer |= PG2 | PG3 | PG4;
	switch (slave->cs) {
		case 1: /* see G above */ g_fer |= PG1;  break;
		case 2: SET_MUX(f, 4, 3); f_fer |= PF12; break;
		case 3: SET_MUX(f, 4, 3); f_fer |= PF13; break;
		case 4: SET_MUX(h, 1, 1); h_fer |= PH8;  break;
		case 5: SET_MUX(h, 2, 1); h_fer |= PH9;  break;
		case 6: SET_MUX(f, 1, 3); f_fer |= PF9;  break;
		case 7: SET_MUX(f, 2, 3); f_fer |= PF10; break;
	}
	bfin_write_PORTF_MUX(f_mux);
	bfin_write_PORTF_FER(f_fer);
	bfin_write_PORTG_MUX(g_mux);
	bfin_write_PORTG_FER(g_fer);
	bfin_write_PORTH_MUX(h_mux);
	bfin_write_PORTH_FER(h_fer);
#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
	u16 mux = bfin_read_PORT_MUX();
	u16 f_fer = bfin_read_PORTF_FER();
	/* set SCK/MISO/MOSI */
	f_fer |= PF11 | PF12 | PF13;
	switch (slave->cs) {
		case 1: f_fer |= PF10; break;
		case 2: mux |= PJSE; break;
		case 3: mux |= PJSE; break;
		case 4: mux |= PFS4E; f_fer |= PF6; break;
		case 5: mux |= PFS5E; f_fer |= PF5; break;
		case 6: mux |= PFS6E; f_fer |= PF4; break;
		case 7: mux |= PJCE_SPI; break;
	}
	bfin_write_PORT_MUX(mux);
	bfin_write_PORTF_FER(f_fer);
#elif defined(__ADSPBF538__) || defined(__ADSPBF539__)
	u16 fer, pins;
	if (slave->bus == 1)
		pins = PD0 | PD1 | PD2 | (slave->cs == 1 ? PD4 : 0);
	else if (slave->bus == 2)
		pins = PD5 | PD6 | PD7 | (slave->cs == 1 ? PD9 : 0);
	else
		pins = 0;
	if (pins) {
		fer = bfin_read_PORTDIO_FER();
		fer &= ~pins;
		bfin_write_PORTDIO_FER(fer);
	}
#elif defined(__ADSPBF54x__)
#define DO_MUX(port, pin) \
	mux = ((mux & ~PORT_x_MUX_##pin##_MASK) | PORT_x_MUX_##pin##_FUNC_1); \
	fer |= P##port##pin;
	u32 mux;
	u16 fer;
	switch (slave->bus) {
	case 0:
		mux = bfin_read_PORTE_MUX();
		fer = bfin_read_PORTE_FER();
		/* set SCK/MISO/MOSI */
		DO_MUX(E, 0);
		DO_MUX(E, 1);
		DO_MUX(E, 2);
		switch (slave->cs) {
			case 1: DO_MUX(E, 4); break;
			case 2: DO_MUX(E, 5); break;
			case 3: DO_MUX(E, 6); break;
		}
		bfin_write_PORTE_MUX(mux);
		bfin_write_PORTE_FER(fer);
		break;
	case 1:
		mux = bfin_read_PORTG_MUX();
		fer = bfin_read_PORTG_FER();
		/* set SCK/MISO/MOSI */
		DO_MUX(G, 8);
		DO_MUX(G, 9);
		DO_MUX(G, 10);
		switch (slave->cs) {
			case 1: DO_MUX(G, 5); break;
			case 2: DO_MUX(G, 6); break;
			case 3: DO_MUX(G, 7); break;
		}
		bfin_write_PORTG_MUX(mux);
		bfin_write_PORTG_FER(fer);
		break;
	case 2:
		mux = bfin_read_PORTB_MUX();
		fer = bfin_read_PORTB_FER();
		/* set SCK/MISO/MOSI */
		DO_MUX(B, 12);
		DO_MUX(B, 13);
		DO_MUX(B, 14);
		switch (slave->cs) {
			case 1: DO_MUX(B, 9);  break;
			case 2: DO_MUX(B, 10); break;
			case 3: DO_MUX(B, 11); break;
		}
		bfin_write_PORTB_MUX(mux);
		bfin_write_PORTB_FER(fer);
		break;
	}
#endif
}