int do_icache_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int cache_status = icache_status();
if (cache_status)
icache_disable();
uint32_t cmd_base, tag, cache_upper, cache_lower;
size_t way, way_start = 0, way_end = 3;
size_t sbnk, sbnk_start = 0, sbnk_end = 3;
size_t set, set_start = 0, set_end = 31;
size_t dw;
if (argc > 1) {
way_start = way_end = simple_strtoul(argv[1], NULL, 10);
if (argc > 2) {
sbnk_start = sbnk_end = simple_strtoul(argv[2], NULL, 10);
if (argc > 3)
set_start = set_end = simple_strtoul(argv[3], NULL, 10);
}
}
if (check_limit("way", 0, 3, way_start, way_end) || \
check_limit("subbank", 0, 3, sbnk_start, sbnk_end) || \
check_limit("set", 0, 31, set_start, set_end))
return 1;
puts("Way:Subbank:Set: [valid-tag lower upper] {invalid-tag lower upper}...\n");
for (way = way_start; way <= way_end; ++way) {
for (sbnk = sbnk_start; sbnk <= sbnk_end; ++sbnk) {
for (set = set_start; set <= set_end; ++set) {
printf("%zu:%zu:%2zu: ", way, sbnk, set);
for (dw = 0; dw < 4; ++dw) {
if (ctrlc())
return 1;
cmd_base = \
(way << 26) | \
(sbnk << 16) | \
(set << 5) | \
(dw << 3);
/* first read the tag */
bfin_write_ITEST_COMMAND(cmd_base | 0x0);
SSYNC();
tag = bfin_read_ITEST_DATA0();
printf("%c%08x ", (tag & 0x1 ? ' ' : '{'), tag);
/* grab the data at this loc */
bfin_write_ITEST_COMMAND(cmd_base | 0x4);
SSYNC();
cache_lower = bfin_read_ITEST_DATA0();
cache_upper = bfin_read_ITEST_DATA1();
printf("%08x %08x%c ", cache_lower, cache_upper, (tag & 0x1 ? ' ' : '}'));
}
puts("\n");
}
}
}
if (cache_status)
icache_enable();
return 0;
}
/*
* irq_panic - calls panic with string setup
*/
asmlinkage void irq_panic(int reason, struct pt_regs *regs)
{
#ifdef CONFIG_DEBUG_ICACHE_CHECK
unsigned int cmd, tag, ca, cache_hi, cache_lo, *pa;
unsigned short i, j, die;
unsigned int bad[10][6];
/* check entire cache for coherency
* Since printk is in cacheable memory,
* don't call it until you have checked everything
*/
die = 0;
i = 0;
/* check icache */
for (ca = L1_ICACHE_START; ca <= L1_ICACHE_END && i < 10; ca += 32) {
/* Grab various address bits for the itest_cmd fields */
cmd = (((ca & 0x3000) << 4) | /* ca[13:12] for SBNK[1:0] */
((ca & 0x0c00) << 16) | /* ca[11:10] for WAYSEL[1:0] */
((ca & 0x3f8)) | /* ca[09:03] for SET[4:0] and DW[1:0] */
0); /* Access Tag, Read access */
SSYNC();
bfin_write_ITEST_COMMAND(cmd);
SSYNC();
tag = bfin_read_ITEST_DATA0();
SSYNC();
/* if tag is marked as valid, check it */
if (tag & 1) {
/* The icache is arranged in 4 groups of 64-bits */
for (j = 0; j < 32; j += 8) {
cmd = ((((ca + j) & 0x3000) << 4) | /* ca[13:12] for SBNK[1:0] */
(((ca + j) & 0x0c00) << 16) | /* ca[11:10] for WAYSEL[1:0] */
(((ca + j) & 0x3f8)) | /* ca[09:03] for SET[4:0] and DW[1:0] */
4); /* Access Data, Read access */
SSYNC();
bfin_write_ITEST_COMMAND(cmd);
SSYNC();
cache_hi = bfin_read_ITEST_DATA1();
cache_lo = bfin_read_ITEST_DATA0();
pa = ((unsigned int *)((tag & 0xffffcc00) |
((ca + j) & ~(0xffffcc00))));
/*
* Debugging this, enable
*
* printk("addr: %08x %08x%08x | %08x%08x\n",
* ((unsigned int *)((tag & 0xffffcc00) | ((ca+j) & ~(0xffffcc00)))),
* cache_hi, cache_lo, *(pa+1), *pa);
*/
if (cache_hi != *(pa + 1) || cache_lo != *pa) {
/* Since icache is not working, stay out of it, by not printing */
die = 1;
bad[i][0] = (ca + j);
bad[i][1] = cache_hi;
bad[i][2] = cache_lo;
bad[i][3] = ((tag & 0xffffcc00) |
((ca + j) & ~(0xffffcc00)));
bad[i][4] = *(pa + 1);
bad[i][5] = *(pa);
i++;
}
}
}
}
if (die) {
printk(KERN_EMERG "icache coherency error\n");
for (j = 0; j <= i; j++) {
printk(KERN_EMERG
"cache address : %08x cache value : %08x%08x\n",
bad[j][0], bad[j][1], bad[j][2]);
printk(KERN_EMERG
"physical address: %08x SDRAM value : %08x%08x\n",
bad[j][3], bad[j][4], bad[j][5]);
}
panic("icache coherency error");
} else {
printk(KERN_EMERG "icache checked, and OK\n");
}
#endif
}
