static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y) { if (dcache_status()) blackfin_dcache_flush_range(logo->data, logo->data + logo->size); bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); /* Setup destination start address */ bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE) + (y * LCD_X_RES * LCD_PIXEL_SIZE)); /* Setup destination xcount */ bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16); /* Setup destination xmodify */ bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16); /* Setup destination ycount */ bfin_write_MDMA_D0_Y_COUNT(logo->height); /* Setup destination ymodify */ bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16); /* Setup Source start address */ bfin_write_MDMA_S0_START_ADDR(logo->data); /* Setup Source xcount */ bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16); /* Setup Source xmodify */ bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16); /* Setup Source ycount */ bfin_write_MDMA_S0_Y_COUNT(logo->height); /* Setup Source ymodify */ bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16); /* Enable source DMA */ bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D); SSYNC(); bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D); while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN); bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR); bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR); }
void __init early_dma_memcpy_done(void) { early_shadow_stamp(); while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) || (bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE))) continue; bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); bfin_write_MDMA_D1_IRQ_STATUS(DMA_DONE | DMA_ERR); /* * Now that DMA is done, we would normally flush cache, but * i/d cache isn't running this early, so we don't bother, * and just clear out the DMA channel for next time */ bfin_write_MDMA_S0_CONFIG(0); bfin_write_MDMA_S1_CONFIG(0); bfin_write_MDMA_D0_CONFIG(0); bfin_write_MDMA_D1_CONFIG(0); __builtin_bfin_ssync(); }