static int
bhndb_pci_attach(device_t dev)
{
struct bhndb_pci_softc *sc;
int error, reg;
sc = device_get_softc(dev);
sc->dev = dev;
/* Enable PCI bus mastering */
pci_enable_busmaster(device_get_parent(dev));
/* Determine our bridge device class */
sc->pci_devclass = BHND_DEVCLASS_PCI;
if (pci_find_cap(device_get_parent(dev), PCIY_EXPRESS, ®) == 0)
sc->pci_devclass = BHND_DEVCLASS_PCIE;
/* Determine the basic set of applicable quirks. This will be updated
* in bhndb_pci_init_full_config() once the PCI device core has
* been enumerated. */
sc->quirks = bhndb_pci_discover_quirks(sc, NULL);
/* Using the discovered quirks, apply any WARs required for basic
* register access. */
if ((error = bhndb_pci_wars_register_access(sc)))
return (error);
/* Use siba(4)-compatible regwin handling until we know
* what kind of bus is attached */
sc->set_regwin = bhndb_pci_compat_setregwin;
/* Perform full bridge attach. This should call back into our
* bhndb_pci_init_full_config() implementation once the bridged
* bhnd(4) bus has been enumerated, but before any devices have been
* probed or attached. */
if ((error = bhndb_attach(dev, sc->pci_devclass)))
return (error);
/* If supported, switch to the faster regwin handling */
if (sc->bhndb.chipid.chip_type != BHND_CHIPTYPE_SIBA) {
atomic_store_rel_ptr((volatile void *) &sc->set_regwin,
(uintptr_t) &bhndb_pci_fast_setregwin);
}
return (0);
}
static int
bhndb_pci_attach(device_t dev)
{
struct bhndb_pci_softc *sc;
struct bhnd_chipid cid;
struct bhnd_core_info *cores, hostb_core;
bhnd_erom_class_t *erom_class;
struct bhndb_pci_probe *probe;
u_int ncores;
int irq_rid;
int error;
sc = device_get_softc(dev);
sc->dev = dev;
sc->parent = device_get_parent(dev);
sc->pci_devclass = bhndb_expected_pci_devclass(dev);
sc->pci_quirks = 0;
sc->set_regwin = NULL;
BHNDB_PCI_LOCK_INIT(sc);
probe = NULL;
cores = NULL;
/* Enable PCI bus mastering */
pci_enable_busmaster(sc->parent);
/* Enable clocks (if required by this hardware) */
if ((error = bhndb_enable_pci_clocks(sc->dev)))
goto cleanup;
/* Identify the chip and enumerate the bridged cores */
error = bhndb_pci_probe_alloc(&probe, dev, sc->pci_devclass);
if (error)
goto cleanup;
sc->pci_quirks = bhndb_pci_get_core_quirks(&probe->cid,
&probe->hostb_core);
/* Select the appropriate register window handler */
if (probe->cid.chip_type == BHND_CHIPTYPE_SIBA) {
sc->set_regwin = bhndb_pci_compat_setregwin;
} else {
sc->set_regwin = bhndb_pci_fast_setregwin;
}
/*
* Fix up our PCI base address in the SPROM shadow, if necessary.
*
* This must be done prior to accessing any static register windows
* that map the PCI core.
*/
if ((error = bhndb_pci_srsh_pi_war(sc, probe)))
goto cleanup;
/* Set up PCI interrupt handling */
if (bhndb_pci_alloc_msi(sc, &sc->msi_count) == 0) {
/* MSI uses resource IDs starting at 1 */
irq_rid = 1;
device_printf(dev, "Using MSI interrupts on %s\n",
device_get_nameunit(sc->parent));
} else {
sc->msi_count = 0;
irq_rid = 0;
device_printf(dev, "Using INTx interrupts on %s\n",
device_get_nameunit(sc->parent));
}
sc->isrc = bhndb_alloc_intr_isrc(sc->parent, irq_rid, 0, RM_MAX_END, 1,
RF_SHAREABLE | RF_ACTIVE);
if (sc->isrc == NULL) {
device_printf(sc->dev, "failed to allocate interrupt "
"resource\n");
error = ENXIO;
goto cleanup;
}
/*
* Copy out the probe results and then free our probe state, releasing
* its exclusive ownership of host bridge resources.
*
* This must be done prior to full configuration of the bridge via
* bhndb_attach().
*/
cid = probe->cid;
erom_class = probe->erom_class;
hostb_core = probe->hostb_core;
error = bhndb_pci_probe_copy_core_table(probe, &cores, &ncores);
if (error) {
cores = NULL;
goto cleanup;
}
bhndb_pci_probe_free(probe);
probe = NULL;
/* Perform bridge attach */
error = bhndb_attach(dev, &cid, cores, ncores, &hostb_core, erom_class);
if (error)
goto cleanup;
/* Add any additional child devices */
if ((error = bhndb_pci_add_children(sc)))
goto cleanup;
/* Probe and attach our children */
if ((error = bus_generic_attach(dev)))
goto cleanup;
bhndb_pci_probe_free_core_table(cores);
return (0);
cleanup:
device_delete_children(dev);
if (sc->isrc != NULL)
bhndb_free_intr_isrc(sc->isrc);
if (sc->msi_count > 0)
pci_release_msi(sc->parent);
if (cores != NULL)
bhndb_pci_probe_free_core_table(cores);
if (probe != NULL)
bhndb_pci_probe_free(probe);
bhndb_disable_pci_clocks(sc->dev);
pci_disable_busmaster(sc->parent);
BHNDB_PCI_LOCK_DESTROY(sc);
return (error);
}
