static __cpuinit void ispram_store_data(unsigned int offset, unsigned int datalo, unsigned int datahi) { unsigned int errctl; /* enable SPRAM tag access */ errctl = bis_c0_errctl(ERRCTL_SPRAM); ehb(); #ifdef CONFIG_CPU_BIG_ENDIAN write_c0_idatalo(datahi); ehb(); write_c0_idatahi(datalo); ehb(); #else write_c0_idatalo(datalo); ehb(); write_c0_idatahi(datahi); ehb(); #endif cache_op(MIPS34K_Index_Store_Data_I, CKSEG0|offset); ehb(); write_c0_errctl(errctl); ehb(); }
static __cpuinit void dspram_store_tag(unsigned int offset, unsigned int data) { unsigned int errctl; /* enable SPRAM tag access */ errctl = bis_c0_errctl(ERRCTL_SPRAM); ehb(); write_c0_dtaglo(data); ehb(); cache_op(Index_Store_Tag_D, CKSEG0 | offset); ehb(); write_c0_errctl(errctl); ehb(); }
static __cpuinit unsigned int dspram_load_tag(unsigned int offset) { unsigned int data; unsigned int errctl; errctl = bis_c0_errctl(ERRCTL_SPRAM); ehb(); cache_op(Index_Load_Tag_D, CKSEG0 | offset); ehb(); data = read_c0_dtaglo(); ehb(); write_c0_errctl(errctl); ehb(); return data; }
static unsigned int ispram_load_tag(unsigned int offset) { unsigned int data; unsigned int errctl; /* enable SPRAM tag access */ errctl = bis_c0_errctl(ERRCTL_SPRAM); ehb(); cache_op(Index_Load_Tag_I, CKSEG0 | offset); ehb(); data = read_c0_taglo(); ehb(); write_c0_errctl(errctl); ehb(); return data; }