/** Enables a breakpoint. * @param bp_num Hardware breakpoint ID. Usually an integer from 0..N. */ static void enableBreakpoint(tcb_t *t, uint16_t bp_num) { word_t enable_bit; assert(t != NULL); assert(bp_num < X86_DEBUG_BP_N_REGS); switch (bp_num) { case 0: enable_bit = X86_DEBUG_BP0_ENABLE_BIT; break; case 1: enable_bit = X86_DEBUG_BP1_ENABLE_BIT; break; case 2: enable_bit = X86_DEBUG_BP2_ENABLE_BIT; break; default: enable_bit = X86_DEBUG_BP3_ENABLE_BIT; break; } bitwiseOrDr7Context(t, enable_bit); }
/** Backend for the seL4_TCB_SetBreakpoint invocation. * * @param uds Arch TCB register context structure. * @param bp_num Hardware breakpoint ID. * @param vaddr USerspace virtual address on which you'd like this breakpoing * to trigger. * @param types One of the seL4_BreakpointType values. * @param size positive integer indicating the byte-range size that should * trigger the breakpoint. 0 is valid for Instruction breakpoints. * @param rw Access type that should trigger the BP (read/write). */ void setBreakpoint(tcb_t *t, uint16_t bp_num, word_t vaddr, word_t types, word_t size, word_t rw) { word_t dr7val; assert(t != NULL); dr7val = convertTypeAndAccessToArch(bp_num, types, rw); dr7val |= convertSizeToArch(bp_num, types, size); setBpVaddrContext(t, bp_num, vaddr); unsetDr7BitsFor(t, bp_num); bitwiseOrDr7Context(t, dr7val); enableBreakpoint(t, bp_num); }