static int ce4100_conf_read(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 *value) { int i; WARN_ON(seg); if (bus == 1) { for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) { if (bus1_fixups[i].dev_func == devfn && bus1_fixups[i].reg == (reg & ~3) && bus1_fixups[i].read) { bus1_fixups[i].read(&(bus1_fixups[i]), value); extract_bytes(value, reg, len); return 0; } } } if (bus == 0 && (PCI_DEVFN(1, 0) == devfn) && !bridge_read(devfn, reg, len, value)) return 0; return pci_direct_conf1.read(seg, bus, devfn, reg, len, value); }
static unsigned int startup_bridge_irq(struct irq_data *d) { struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); struct bridge_controller *bc; nasid_t nasid; u32 device; int pin; if (!hd) return -EINVAL; pin = hd->pin; bc = hd->bc; nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(hd->cpu)); bridge_write(bc, b_int_addr[pin].addr, (0x20000 | hd->bit | (nasid << 8))); bridge_set(bc, b_int_enable, (1 << pin)); bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */ /* * Enable sending of an interrupt clear packt to the hub on a high to * low transition of the interrupt pin. * * IRIX sets additional bits in the address which are documented as * reserved in the bridge docs. */ bridge_set(bc, b_int_mode, (1UL << pin)); /* * We assume the bridge to have a 1:1 mapping between devices * (slots) and intr pins. */ device = bridge_read(bc, b_int_device); device &= ~(7 << (pin*3)); device |= (pin << (pin*3)); bridge_write(bc, b_int_device, device); bridge_read(bc, b_wid_tflush); enable_hub_irq(d); return 0; /* Never anything pending. */ }
static void shutdown_bridge_irq(struct irq_data *d) { struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); struct bridge_controller *bc; int pin = hd->pin; if (!hd) return; disable_hub_irq(d); bc = hd->bc; bridge_clr(bc, b_int_enable, (1 << pin)); bridge_read(bc, b_wid_tflush); }