static void northbridge_dmi_init(pci_dev_t dev) { /* Clear error status bits */ writel(0xffffffff, DMIBAR_REG(0x1c4)); writel(0xffffffff, DMIBAR_REG(0x1d0)); /* Steps prior to DMI ASPM */ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20), 1 << 21); } setbits_le32(DMIBAR_REG(0x238), 1 << 29); if (bridge_silicon_revision() >= SNB_STEP_D0) { setbits_le32(DMIBAR_REG(0x1f8), 1 << 16); } else if (bridge_silicon_revision() >= SNB_STEP_D1) { clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16); setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23)); } /* Enable ASPM on SNB link, should happen before PCH link */ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) setbits_le32(DMIBAR_REG(0xd04), 1 << 4); setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0)); }
static void add_fixed_resources(struct device *dev, int index) { struct resource *resource; u32 pcie_config_base, pcie_config_size; mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " "size=0x%x\n", pcie_config_base, pcie_config_size); resource = new_resource(dev, index++); resource->base = (resource_t) pcie_config_base; resource->size = (resource_t) pcie_config_size; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k); reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); #if CONFIG_CHROMEOS_RAMOOPS reserved_ram_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); #endif if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { /* Required for SandyBridge sighting 3715511 */ bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10); bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); }
static int bd82x6x_northbridge_probe(struct udevice *dev) { int rev; if (!(gd->flags & GD_FLG_RELOC)) return bd82x6x_northbridge_early_init(dev); rev = bridge_silicon_revision(dev); northbridge_init(dev, rev); return 0; }
void northbridge_init(pci_dev_t dev) { u32 bridge_type; add_fixed_resources(dev, 6); northbridge_dmi_init(dev); bridge_type = readl(MCHBAR_REG(0x5f10)); bridge_type &= ~0xff; if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { /* Enable Power Aware Interrupt Routing - fixed priority */ clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4); /* 30h for IvyBridge */ bridge_type |= 0x30; } else { /* 20h for Sandybridge */ bridge_type |= 0x20; } writel(bridge_type, MCHBAR_REG(0x5f10)); /* * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU * that BIOS has initialized memory and power management */ setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1); debug("Set BIOS_RESET_CPL\n"); /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); set_power_limits(28); /* * CPUs with configurable TDP also need power limits set * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. */ if (cpu_config_tdp_levels()) { msr_t msr = msr_read(MSR_PKG_POWER_LIMIT); writel(msr.lo, MCHBAR_REG(0x59A0)); writel(msr.hi, MCHBAR_REG(0x59A4)); } /* Set here before graphics PM init */ writel(0x00100001, MCHBAR_REG(0x5500)); }
static void gma_pm_init_post_vbios(struct device *dev) { struct northbridge_intel_sandybridge_config *conf = dev->chip_info; u32 reg32; printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); /* 15: Deassert Force Wake */ if (bridge_silicon_revision() < IVB_STEP_C0) { gtt_write(0xa18c, gtt_read(0xa18c) & ~1); gtt_poll(0x130090, (1 << 0), (0 << 0)); } else { gtt_write(0xa188, 0x1fffe); if (gtt_poll(0x130040, (1 << 0), (0 << 0))) gtt_write(0xa188, gtt_read(0xa188) | 1); } /* 16: SW RC Control */ gtt_write(0xa094, 0x00060000); /* Setup Digital Port Hotplug */ reg32 = gtt_read(0xc4030); if (!reg32) { reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; gtt_write(0xc4030, reg32); } /* Setup Panel Power On Delays */ reg32 = gtt_read(0xc7208); if (!reg32) { reg32 = (conf->gpu_panel_port_select & 0x3) << 30; reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); gtt_write(0xc7208, reg32); } /* Setup Panel Power Off Delays */ reg32 = gtt_read(0xc720c); if (!reg32) { reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); gtt_write(0xc720c, reg32); } /* Setup Panel Power Cycle Delay */ if (conf->gpu_panel_power_cycle_delay) { reg32 = gtt_read(0xc7210); reg32 &= ~0xff; reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; gtt_write(0xc7210, reg32); } /* Enable Backlight if needed */ if (conf->gpu_cpu_backlight) { gtt_write(0x48250, (1 << 31)); gtt_write(0x48254, conf->gpu_cpu_backlight); } if (conf->gpu_pch_backlight) { gtt_write(0xc8250, (1 << 31)); gtt_write(0xc8254, conf->gpu_pch_backlight); } }
static void gma_pm_init_pre_vbios(struct device *dev) { u32 reg32; printk(BIOS_DEBUG, "GT Power Management Init\n"); gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!gtt_res || !gtt_res->base) return; if (bridge_silicon_revision() < IVB_STEP_C0) { /* 1: Enable force wake */ gtt_write(0xa18c, 0x00000001); gtt_poll(0x130090, (1 << 0), (1 << 0)); } else { gtt_write(0xa180, 1 << 5); gtt_write(0xa188, 0xffff0001); gtt_poll(0x130040, (1 << 0), (1 << 0)); } if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ reg32 = gtt_read(0x42004); reg32 |= (1 << 14) | (1 << 15); gtt_write(0x42004, reg32); } if (bridge_silicon_revision() >= IVB_STEP_A0) { /* Display Reset Acknowledge Settings */ reg32 = gtt_read(0x45010); reg32 |= (1 << 1) | (1 << 0); gtt_write(0x45010, reg32); } /* 2: Get GT SKU from GTT+0x911c[13] */ reg32 = gtt_read(0x911c); if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { if (reg32 & (1 << 13)) { printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n"); gtt_write_powermeter(snb_pm_gt1); } else { printk(BIOS_DEBUG, "SNB GT2 Power Meter Weights\n"); gtt_write_powermeter(snb_pm_gt2); } } else { u32 unit = MCHBAR32(0x5938) & 0xf; if (reg32 & (1 << 13)) { /* GT1 SKU */ printk(BIOS_DEBUG, "IVB GT1 Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt1); } else { /* GT2 SKU */ u32 tdp = MCHBAR32(0x5930) & 0x7fff; tdp /= (1 << unit); if (tdp <= 17) { /* <=17W ULV */ printk(BIOS_DEBUG, "IVB GT2 17W " "Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt2_17w); } else if ((tdp >= 25) && (tdp <= 35)) { /* 25W-35W */ printk(BIOS_DEBUG, "IVB GT2 25W-35W " "Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt2_35w); } else { /* All others */ printk(BIOS_DEBUG, "IVB GT2 35W " "Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt2_35w); } } } /* 3: Gear ratio map */ gtt_write(0xa004, 0x00000010); /* 4: GFXPAUSE */ gtt_write(0xa000, 0x00070020); /* 5: Dynamic EU trip control */ gtt_write(0xa080, 0x00000004); /* 6: ECO bits */ reg32 = gtt_read(0xa180); reg32 |= (1 << 26) | (1 << 31); /* (bit 20=1 for SNB step D1+ / IVB A0+) */ if (bridge_silicon_revision() >= SNB_STEP_D1) reg32 |= (1 << 20); gtt_write(0xa180, reg32); /* 6a: for SnB step D2+ only */ if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && (bridge_silicon_revision() >= SNB_STEP_D2)) { reg32 = gtt_read(0x9400); reg32 |= (1 << 7); gtt_write(0x9400, reg32); reg32 = gtt_read(0x941c); reg32 &= 0xf; reg32 |= (1 << 1); gtt_write(0x941c, reg32); gtt_poll(0x941c, (1 << 1), (0 << 1)); } if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { reg32 = gtt_read(0x907c); reg32 |= (1 << 16); gtt_write(0x907c, reg32); /* 6b: Clocking reset controls */ gtt_write(0x9424, 0x00000001); } else { /* 6b: Clocking reset controls */ gtt_write(0x9424, 0x00000000); } /* 7 */ if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { gtt_write(0x138128, 0x00000029); /* Mailbox Data */ gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */ if (gtt_poll(0x138124, (1 << 31), (0 << 31))) gtt_write(0x138124, 0x8000000a); gtt_poll(0x138124, (1 << 31), (0 << 31)); } /* 8 */ gtt_write(0xa090, 0x00000000); /* RC Control */ gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */ gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */ gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */ /* 9 */ gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */ gtt_write(0x12054,0x0000000a); /* Video Idle Max Count */ gtt_write(0x22054,0x0000000a); /* Blitter Idle Max Count */ /* 10 */ gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */ gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */ gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */ gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */ gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */ /* 11 */ gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */ gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */ gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */ gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */ gtt_write(0xa068, 0x000186a0); /* RP Up EI */ gtt_write(0xa06c, 0x000493e0); /* RP Down EI */ gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */ /* 11a: Enable Render Standby (RC6) */ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { /* * IvyBridge should also support DeepRenderStandby. * * Unfortunately it does not work reliably on all SKUs so * disable it here and it can be enabled by the kernel. */ gtt_write(0xa090, 0x88040000); /* HW RC Control */ } else { gtt_write(0xa090, 0x88040000); /* HW RC Control */ } /* 12: Normal Frequency Request */ /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */ /* only the lower 7 bits are used and shifted left by 25 */ reg32 = MCHBAR32(0x5998); reg32 >>= 16; reg32 &= 0x7f; reg32 <<= 25; gtt_write(0xa008, reg32); /* 13: RP Control */ gtt_write(0xa024, 0x00000592); /* 14: Enable PM Interrupts */ gtt_write(0x4402c, 0x03000076); /* Clear 0x6c024 [8:6] */ reg32 = gtt_read(0x6c024); reg32 &= ~0x000001c0; gtt_write(0x6c024, reg32); /* Initialize DP buffer translation with recommended defaults */ gtt_write(0xe4f00, 0x0100030c); gtt_write(0xe4f04, 0x00b8230c); gtt_write(0xe4f08, 0x06f8930c); gtt_write(0xe4f0c, 0x05f8e38e); gtt_write(0xe4f10, 0x00b8030c); gtt_write(0xe4f14, 0x0b78830c); gtt_write(0xe4f18, 0x09f8d3cf); gtt_write(0xe4f1c, 0x01e8030c); gtt_write(0xe4f20, 0x09f863cf); gtt_write(0xe4f24, 0x0ff803cf); }