static int
ti_edma3_attach(device_t dev)
{
struct ti_edma3_softc *sc = device_get_softc(dev);
uint32_t reg;
int err;
int i;
if (ti_edma3_sc)
return (ENXIO);
ti_edma3_sc = sc;
sc->sc_dev = dev;
/* Request the memory resources */
err = bus_alloc_resources(dev, ti_edma3_mem_spec, sc->mem_res);
if (err) {
device_printf(dev, "Error: could not allocate mem resources\n");
return (ENXIO);
}
/* Request the IRQ resources */
err = bus_alloc_resources(dev, ti_edma3_irq_spec, sc->irq_res);
if (err) {
device_printf(dev, "Error: could not allocate irq resources\n");
return (ENXIO);
}
/* Enable Channel Controller */
ti_prcm_clk_enable(EDMA_TPCC_CLK);
reg = ti_edma3_cc_rd_4(TI_EDMA3CC_PID);
device_printf(dev, "EDMA revision %08x\n", reg);
/* Attach interrupt handlers */
for (i = 0; i < TI_EDMA3_NUM_IRQS; ++i) {
err = bus_setup_intr(dev, sc->irq_res[i], INTR_TYPE_MISC |
INTR_MPSAFE, NULL, *ti_edma3_intrs[i].handler,
sc, &sc->ih_cookie[i]);
if (err) {
device_printf(dev, "could not setup %s\n",
ti_edma3_intrs[i].description);
return (err);
}
}
return (0);
}
static int
combiner_attach(device_t dev)
{
struct combiner_softc *sc;
int err;
int i;
sc = device_get_softc(dev);
sc->dev = dev;
if (bus_alloc_resources(dev, combiner_spec, sc->res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
/* Memory interface */
sc->bst = rman_get_bustag(sc->res[0]);
sc->bsh = rman_get_bushandle(sc->res[0]);
combiner_sc = sc;
/* Setup interrupt handler */
for (i = 0; i < NGRP; i++) {
err = bus_setup_intr(dev, sc->res[1+i], INTR_TYPE_BIO | \
INTR_MPSAFE, NULL, combiner_intr, sc, &sc->ih[i]);
if (err) {
device_printf(dev, "Unable to alloc int resource.\n");
return (ENXIO);
}
}
return (0);
}
static int
mv_wdt_attach(device_t dev)
{
struct mv_wdt_softc *sc;
int error;
if (wdt_softc != NULL)
return (ENXIO);
sc = device_get_softc(dev);
wdt_softc = sc;
error = bus_alloc_resources(dev, mv_wdt_spec, &sc->wdt_res);
if (error) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
mtx_init(&sc->wdt_mtx, "watchdog", NULL, MTX_DEF);
mv_watchdog_disable();
EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
return (0);
}
/**
* ti_scm_attach - attaches the timer to the simplebus
* @dev: new device
*
* Reserves memory and interrupt resources, stores the softc structure
* globally and registers both the timecount and eventtimer objects.
*
* RETURNS
* Zero on sucess or ENXIO if an error occuried.
*/
static int
ti_scm_attach(device_t dev)
{
struct ti_scm_softc *sc = device_get_softc(dev);
if (ti_scm_sc)
return (ENXIO);
sc->sc_dev = dev;
if (bus_alloc_resources(dev, ti_scm_res_spec, sc->sc_res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
/* Global timer interface */
sc->sc_bst = rman_get_bustag(sc->sc_res[0]);
sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]);
ti_scm_sc = sc;
ti_scm_padconf_init_from_fdt(sc);
return (0);
}
static int
aw_sid_attach(device_t dev)
{
struct aw_sid_softc *sc;
sc = device_get_softc(dev);
if (bus_alloc_resources(dev, aw_sid_spec, &sc->res) != 0) {
device_printf(dev, "cannot allocate resources for device\n");
return (ENXIO);
}
aw_sid_sc = sc;
sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
switch (sc->type) {
case A83T_SID:
sc->root_key_off = A83T_ROOT_KEY_OFF;
break;
default:
sc->root_key_off = A10_ROOT_KEY_OFF;
break;
}
SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
OID_AUTO, "rootkey",
CTLTYPE_STRING | CTLFLAG_RD,
dev, AW_SID_ROOT_KEY, aw_sid_sysctl, "A", "Root Key");
return (0);
}
static int
pxa_icu_attach(device_t dev)
{
int error;
struct pxa_icu_softc *sc;
sc = (struct pxa_icu_softc *)device_get_softc(dev);
if (pxa_icu_softc != NULL)
return (ENXIO);
pxa_icu_softc = sc;
error = bus_alloc_resources(dev, pxa_icu_spec, sc->pi_res);
if (error) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
sc->pi_bst = rman_get_bustag(sc->pi_res[0]);
sc->pi_bsh = rman_get_bushandle(sc->pi_res[0]);
/* Disable all interrupts. */
pxa_icu_set_icmr(0);
/* Route all interrupts to IRQ rather than FIQ. */
pxa_icu_set_iclr(0);
/* XXX: This should move to configure_final or something. */
enable_interrupts(I32_bit|F32_bit);
return (0);
}
static int
al_serdes_attach(device_t dev)
{
struct al_serdes_softc *sc;
int err;
sc = device_get_softc(dev);
err = bus_alloc_resources(dev, al_serdes_spec, &sc->res);
if (err != 0) {
device_printf(dev, "could not allocate resources\n");
return (err);
}
/* Initialize Serdes group locks and mode */
for (int i = 0; i < nitems(alpine_serdes_eth_group_mode); i++) {
mtx_init(&alpine_serdes_eth_group_mode[i].lock, "AlSerdesMtx",
NULL, MTX_DEF);
alpine_serdes_eth_group_mode[i].mode_set = false;
}
serdes_base = (void *)rman_get_bushandle(sc->res);
return (0);
}
static int
htif_attach(device_t dev)
{
struct htif_softc *sc;
int error;
sc = device_get_softc(dev);
sc->dev = dev;
if (bus_alloc_resources(dev, htif_spec, sc->res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
/* Setup IRQs handler */
error = bus_setup_intr(dev, sc->res[0], INTR_TYPE_CLK,
htif_intr, NULL, sc, &sc->ihl[0]);
if (error) {
device_printf(dev, "Unable to alloc int resource.\n");
return (ENXIO);
}
csr_set(sie, SIE_SSIE);
return (htif_enumerate(sc));
}
static int
ti_aintc_attach(device_t dev)
{
struct ti_aintc_softc *sc = device_get_softc(dev);
uint32_t x;
sc->sc_dev = dev;
if (ti_aintc_sc)
return (ENXIO);
if (bus_alloc_resources(dev, ti_aintc_spec, sc->aintc_res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
sc->aintc_bst = rman_get_bustag(sc->aintc_res[0]);
sc->aintc_bsh = rman_get_bushandle(sc->aintc_res[0]);
ti_aintc_sc = sc;
x = aintc_read_4(INTC_REVISION);
device_printf(dev, "Revision %u.%u\n",(x >> 4) & 0xF, x & 0xF);
/* SoftReset */
aintc_write_4(INTC_SYSCONFIG, 2);
/* Wait for reset to complete */
while(!(aintc_read_4(INTC_SYSSTATUS) & 1));
/*Set Priority Threshold */
aintc_write_4(INTC_THRESHOLD, 0xFF);
return (0);
}
static int
aw_ts_attach(device_t dev)
{
struct aw_ts_softc *sc;
sc = device_get_softc(dev);
sc->dev = dev;
if (bus_alloc_resources(dev, aw_ts_spec, sc->res) != 0) {
device_printf(dev, "could not allocate memory resource\n");
return (ENXIO);
}
if (bus_setup_intr(dev, sc->res[1],
INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_ts_intr, sc,
&sc->intrhand)) {
bus_release_resources(dev, aw_ts_spec, sc->res);
device_printf(dev, "cannot setup interrupt handler\n");
return (ENXIO);
}
/*
* Thoses magic values were taken from linux which take them from
* the allwinner SDK or found them by deduction
*/
switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
case A10_TS:
sc->temp_offset = 257000;
sc->temp_step = 133;
break;
case A13_TS:
sc->temp_offset = 144700;
sc->temp_step = 100;
break;
}
/* Enable clock and set divisers */
WRITE(sc, TP_CTRL0, TP_CTRL0_CLK_SELECT(0) |
TP_CTRL0_CLK_DIV(2) |
TP_CTRL0_FS_DIV(7) |
TP_CTRL0_TACQ(63));
/* Enable TS module */
WRITE(sc, TP_CTRL1, TP_CTRL1_MODE_EN);
/* Enable Temperature, period is ~2s */
WRITE(sc, TP_TPR, TP_TPR_TEMP_EN | TP_TPR_TEMP_PERIOD(1953));
/* Enable temp irq */
WRITE(sc, TP_FIFOC, TP_FIFOC_TEMP_IRQ_ENABLE);
/* Add sysctl */
SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD,
&sc->temp_data, 0, sysctl_handle_int,
"IK3", "CPU Temperature");
return (0);
}
static int
aml8726_ccm_attach(device_t dev)
{
struct aml8726_ccm_softc *sc = device_get_softc(dev);
sc->dev = dev;
switch (aml8726_soc_hw_rev) {
case AML_SOC_HW_REV_M3:
sc->soc = aml8726_m3_ccm;
break;
case AML_SOC_HW_REV_M6:
sc->soc = aml8726_m6_ccm;
break;
case AML_SOC_HW_REV_M8:
sc->soc = aml8726_m8_ccm;
break;
case AML_SOC_HW_REV_M8B:
sc->soc = aml8726_m8b_ccm;
break;
default:
device_printf(dev, "unsupported SoC\n");
return (ENXIO);
/* NOTREACHED */
}
if (bus_alloc_resources(dev, aml8726_ccm_spec, sc->res)) {
device_printf(dev, "can not allocate resources for device\n");
return (ENXIO);
}
AML_CCM_LOCK_INIT(sc);
return (aml8726_ccm_configure_gates(sc));
}
static int
gem_sbus_attach(device_t dev)
{
struct gem_softc *sc;
int burst;
uint32_t val;
sc = device_get_softc(dev);
sc->sc_variant = GEM_SUN_GEM;
sc->sc_dev = dev;
/* All known SBus models use a SERDES. */
sc->sc_flags = GEM_SERDES;
if (bus_alloc_resources(dev, gem_sbus_res_spec, sc->sc_res)) {
device_printf(dev, "failed to allocate resources\n");
bus_release_resources(dev, gem_sbus_res_spec, sc->sc_res);
return (ENXIO);
}
GEM_LOCK_INIT(sc, device_get_nameunit(dev));
OF_getetheraddr(dev, sc->sc_enaddr);
burst = sbus_get_burstsz(dev);
val = GEM_SBUS_CFG_PARITY;
if ((burst & SBUS_BURST64_MASK) != 0) {
val |= GEM_SBUS_CFG_64BIT;
burst >>= SBUS_BURST64_SHIFT;
}
static int
schppm_attach(device_t dev)
{
struct schppm_softc *sc;
sc = device_get_softc(dev);
if (bus_alloc_resources(dev, schppm_res_spec, sc->sc_res)) {
device_printf(dev, "failed to allocate resources\n");
bus_release_resources(dev, schppm_res_spec, sc->sc_res);
return (ENXIO);
}
if (bootverbose) {
device_printf(dev, "running at ");
switch (SCHPPM_READ(sc, SCHPPM_ESTAR, SCHPPM_ESTAR_CTRL) &
SCHPPM_ESTAR_CTRL_MASK) {
case SCHPPM_ESTAR_CTRL_1:
printf("full");
break;
case SCHPPM_ESTAR_CTRL_2:
printf("half");
break;
case SCHPPM_ESTAR_CTRL_32:
printf("1/32");
break;
default:
printf("unknown");
break;
}
printf(" speed\n");
}
return (0);
}
/**
* ti_pinmux_attach - attaches the pinmux to the simplebus
* @dev: new device
*
* RETURNS
* Zero on success or ENXIO if an error occuried.
*/
static int
ti_pinmux_attach(device_t dev)
{
struct ti_pinmux_softc *sc = device_get_softc(dev);
#if 0
if (ti_pinmux_sc)
return (ENXIO);
#endif
sc->sc_dev = dev;
if (bus_alloc_resources(dev, ti_pinmux_res_spec, sc->sc_res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
sc->sc_bst = rman_get_bustag(sc->sc_res[0]);
sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]);
if (ti_pinmux_sc == NULL)
ti_pinmux_sc = sc;
fdt_pinctrl_register(dev, "pinctrl-single,pins");
fdt_pinctrl_configure_tree(dev);
return (0);
}
static int
mv_twsi_attach(device_t dev)
{
struct mv_twsi_softc *sc;
sc = device_get_softc(dev);
sc->dev = dev;
mtx_init(&sc->mutex, device_get_nameunit(dev), MV_TWSI_NAME, MTX_DEF);
/* Allocate IO resources */
if (bus_alloc_resources(dev, res_spec, sc->res)) {
device_printf(dev, "could not allocate resources\n");
mv_twsi_detach(dev);
return (ENXIO);
}
sc->iicbus = device_add_child(dev, "iicbus", -1);
if (sc->iicbus == NULL) {
device_printf(dev, "could not add iicbus child\n");
mv_twsi_detach(dev);
return (ENXIO);
}
bus_generic_attach(dev);
return (0);
}
static int
i2c_attach(device_t dev)
{
struct i2c_softc *sc;
sc = device_get_softc(dev);
sc->dev = dev;
mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF);
if (bus_alloc_resources(dev, i2c_spec, sc->res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
/* Memory interface */
sc->bst = rman_get_bustag(sc->res[0]);
sc->bsh = rman_get_bushandle(sc->res[0]);
WRITE1(sc, I2C_IBIC, IBIC_BIIE);
sc->iicbus = device_add_child(dev, "iicbus", -1);
if (sc->iicbus == NULL) {
device_printf(dev, "could not add iicbus child");
mtx_destroy(&sc->mutex);
return (ENXIO);
}
bus_generic_attach(dev);
return (0);
}
static int
pio_attach(device_t dev)
{
struct pio_softc *sc;
struct fdt_ic *fic;
phandle_t node;
sc = device_get_softc(dev);
sc->dev = dev;
if (bus_alloc_resources(dev, pio_spec, sc->res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
/* Memory interface */
sc->bst = rman_get_bustag(sc->res[0]);
sc->bsh = rman_get_bushandle(sc->res[0]);
if ((node = ofw_bus_get_node(sc->dev)) == -1)
return (ENXIO);
fic = malloc(sizeof(*fic), M_DEVBUF, M_WAITOK|M_ZERO);
fic->iph = node;
fic->dev = dev;
SLIST_INSERT_HEAD(&fdt_ic_list_head, fic, fdt_ics);
return (0);
}
int
twsi_attach(device_t dev)
{
struct twsi_softc *sc;
sc = device_get_softc(dev);
sc->dev = dev;
mtx_init(&sc->mutex, device_get_nameunit(dev), "twsi", MTX_DEF);
if (bus_alloc_resources(dev, res_spec, sc->res)) {
device_printf(dev, "could not allocate resources\n");
twsi_detach(dev);
return (ENXIO);
}
/* Attach the iicbus. */
if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
device_printf(dev, "could not allocate iicbus instance\n");
twsi_detach(dev);
return (ENXIO);
}
bus_generic_attach(dev);
return (0);
}
static int
mv_cp110_icu_attach(device_t dev)
{
struct mv_cp110_icu_softc *sc;
phandle_t node, msi_parent;
sc = device_get_softc(dev);
sc->dev = dev;
node = ofw_bus_get_node(dev);
if (OF_getencprop(node, "msi-parent", &msi_parent,
sizeof(phandle_t)) <= 0) {
device_printf(dev, "cannot find msi-parent property\n");
return (ENXIO);
}
if ((sc->parent = OF_device_from_xref(msi_parent)) == NULL) {
device_printf(dev, "cannot find msi-parent device\n");
return (ENXIO);
}
if (bus_alloc_resources(dev, mv_cp110_icu_res_spec, &sc->res) != 0) {
device_printf(dev, "cannot allocate resources for device\n");
return (ENXIO);
}
if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) {
device_printf(dev, "Cannot register ICU\n");
goto fail;
}
return (0);
fail:
bus_release_resources(dev, mv_cp110_icu_res_spec, &sc->res);
return (ENXIO);
}
static int
spi_attach(device_t dev)
{
struct spi_softc *sc;
uint32_t reg;
sc = device_get_softc(dev);
if (bus_alloc_resources(dev, spi_spec, sc->res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
/* Memory interface */
sc->bst = rman_get_bustag(sc->res[0]);
sc->bsh = rman_get_bushandle(sc->res[0]);
reg = READ4(sc, SPI_MCR);
reg |= MCR_MSTR;
reg &= ~(MCR_CONT_SCKE | MCR_MDIS | MCR_FRZ);
reg &= ~(MCR_PCSIS_M << MCR_PCSIS_S);
reg |= (MCR_PCSIS_M << MCR_PCSIS_S); /* PCS Active low */
reg |= (MCR_CLR_TXF | MCR_CLR_RXF);
WRITE4(sc, SPI_MCR, reg);
reg = READ4(sc, SPI_RSER);
reg |= RSER_EOQF_RE;
WRITE4(sc, SPI_RSER, reg);
reg = READ4(sc, SPI_MCR);
reg &= ~MCR_HALT;
WRITE4(sc, SPI_MCR, reg);
reg = READ4(sc, SPI_CTAR0);
reg &= ~(CTAR_FMSZ_M << CTAR_FMSZ_S);
reg |= (CTAR_FMSZ_8 << CTAR_FMSZ_S);
/*
* TODO: calculate BR
* SCK baud rate = ( fsys / PBR ) * (1 + DBR) / BR
*
* reg &= ~(CTAR_BR_M << CTAR_BR_S);
*/
reg &= ~CTAR_CPOL; /* Polarity */
reg |= CTAR_CPHA;
/*
* Set LSB (Less significant bit first)
* must be used for some applications, e.g. some LCDs
*/
reg |= CTAR_LSBFE;
WRITE4(sc, SPI_CTAR0, reg);
reg = READ4(sc, SPI_CTAR0);
reg &= ~(CTAR_PBR_M << CTAR_PBR_S);
reg |= (CTAR_PBR_7 << CTAR_PBR_S);
WRITE4(sc, SPI_CTAR0, reg);
device_add_child(dev, "spibus", 0);
return (bus_generic_attach(dev));
}
static int
mtk_pic_attach(device_t dev)
{
struct mtk_pic_softc *sc;
intptr_t xref = pic_xref(dev);
sc = device_get_softc(dev);
if (bus_alloc_resources(dev, mtk_pic_spec, sc->pic_res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
sc->pic_dev = dev;
/* Initialize mutex */
mtx_init(&sc->mutex, "PIC lock", "", MTX_SPIN);
/* Set the number of interrupts */
sc->nirqs = nitems(sc->pic_irqs);
/* Mask all interrupts */
WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF);
/* But enable interrupt generation/masking */
WRITE4(sc, MTK_INTENA, 0x00000000);
/* Set all interrupts to type 0 */
WRITE4(sc, MTK_INTTYPE, 0xFFFFFFFF);
/* Register the interrupts */
if (mtk_pic_register_isrcs(sc) != 0) {
device_printf(dev, "could not register PIC ISRCs\n");
goto cleanup;
}
/*
* Now, when everything is initialized, it's right time to
* register interrupt controller to interrupt framefork.
*/
if (intr_pic_register(dev, xref) == NULL) {
device_printf(dev, "could not register PIC\n");
goto cleanup;
}
if (bus_setup_intr(dev, sc->pic_res[1], INTR_TYPE_CLK,
mtk_pic_intr, NULL, sc, &sc->pic_intrhand)) {
device_printf(dev, "could not setup irq handler\n");
intr_pic_deregister(dev, xref);
goto cleanup;
}
return (0);
cleanup:
bus_release_resources(dev, mtk_pic_spec, sc->pic_res);
return(ENXIO);
}
static int
jzsmb_attach(device_t dev)
{
struct jzsmb_softc *sc;
phandle_t node;
int error;
sc = device_get_softc(dev);
node = ofw_bus_get_node(dev);
mtx_init(&sc->mtx, device_get_nameunit(dev), "jzsmb", MTX_DEF);
error = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
if (error != 0) {
device_printf(dev, "cannot get clock\n");
goto fail;
}
error = clk_enable(sc->clk);
if (error != 0) {
device_printf(dev, "cannot enable clock\n");
goto fail;
}
error = clk_get_freq(sc->clk, &sc->bus_freq);
if (error != 0 || sc->bus_freq == 0) {
device_printf(dev, "cannot get bus frequency\n");
return (error);
}
if (bus_alloc_resources(dev, jzsmb_spec, &sc->res) != 0) {
device_printf(dev, "cannot allocate resources for device\n");
error = ENXIO;
goto fail;
}
if (OF_getencprop(node, "clock-frequency", &sc->i2c_freq,
sizeof(sc->i2c_freq)) != 0 || sc->i2c_freq == 0)
sc->i2c_freq = 100000; /* Default to standard mode */
sc->iicbus = device_add_child(dev, "iicbus", -1);
if (sc->iicbus == NULL) {
device_printf(dev, "cannot add iicbus child device\n");
error = ENXIO;
goto fail;
}
bus_generic_attach(dev);
return (0);
fail:
bus_release_resources(dev, jzsmb_spec, &sc->res);
if (sc->clk != NULL)
clk_release(sc->clk);
mtx_destroy(&sc->mtx);
return (error);
}
static int
a10dmac_attach(device_t dev)
{
struct a10dmac_softc *sc;
unsigned int index;
int error;
sc = device_get_softc(dev);
if (bus_alloc_resources(dev, a10dmac_spec, sc->sc_res)) {
device_printf(dev, "cannot allocate resources for device\n");
return (ENXIO);
}
mtx_init(&sc->sc_mtx, "a10 dmac", NULL, MTX_SPIN);
/* Activate DMA controller clock */
a10_clk_dmac_activate();
/* Disable all interrupts and clear pending status */
DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, 0);
DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, ~0);
/* Initialize channels */
for (index = 0; index < NDMA_CHANNELS; index++) {
sc->sc_ndma_channels[index].ch_sc = sc;
sc->sc_ndma_channels[index].ch_index = index;
sc->sc_ndma_channels[index].ch_type = CH_NDMA;
sc->sc_ndma_channels[index].ch_callback = NULL;
sc->sc_ndma_channels[index].ch_callbackarg = NULL;
sc->sc_ndma_channels[index].ch_regoff = AWIN_NDMA_REG(index);
DMACH_WRITE(&sc->sc_ndma_channels[index], AWIN_NDMA_CTL_REG, 0);
}
for (index = 0; index < DDMA_CHANNELS; index++) {
sc->sc_ddma_channels[index].ch_sc = sc;
sc->sc_ddma_channels[index].ch_index = index;
sc->sc_ddma_channels[index].ch_type = CH_DDMA;
sc->sc_ddma_channels[index].ch_callback = NULL;
sc->sc_ddma_channels[index].ch_callbackarg = NULL;
sc->sc_ddma_channels[index].ch_regoff = AWIN_DDMA_REG(index);
DMACH_WRITE(&sc->sc_ddma_channels[index], AWIN_DDMA_CTL_REG, 0);
}
error = bus_setup_intr(dev, sc->sc_res[1], INTR_MPSAFE | INTR_TYPE_MISC,
NULL, a10dmac_intr, sc, &sc->sc_ih);
if (error != 0) {
device_printf(dev, "could not setup interrupt handler\n");
bus_release_resources(dev, a10dmac_spec, sc->sc_res);
mtx_destroy(&sc->sc_mtx);
return (ENXIO);
}
return (0);
}
static int
imx6_anatop_attach(device_t dev)
{
struct imx6_anatop_softc *sc;
int err;
sc = device_get_softc(dev);
sc->dev = dev;
/* Allocate bus_space resources. */
if (bus_alloc_resources(dev, imx6_anatop_spec, sc->res)) {
device_printf(dev, "Cannot allocate resources\n");
err = ENXIO;
goto out;
}
err = bus_setup_intr(dev, sc->res[IRQRES], INTR_TYPE_MISC | INTR_MPSAFE,
tempmon_intr, NULL, sc, &sc->temp_intrhand);
if (err != 0)
goto out;
SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
OID_AUTO, "cpu_voltage", CTLFLAG_RD,
&sc->cpu_curmv, 0, "Current CPU voltage in millivolts");
imx6_anatop_sc = sc;
/*
* Other code seen on the net sets this SELFBIASOFF flag around the same
* time the temperature sensor is set up, although it's unclear how the
* two are related (if at all).
*/
imx6_anatop_write_4(IMX6_ANALOG_PMU_MISC0_SET,
IMX6_ANALOG_PMU_MISC0_SELFBIASOFF);
cpufreq_initialize(sc);
initialize_tempmon(sc);
if (bootverbose) {
device_printf(sc->dev, "CPU %uMHz @ %umV\n", sc->cpu_curmhz,
sc->cpu_curmv);
}
err = 0;
out:
if (err != 0) {
bus_release_resources(dev, imx6_anatop_spec, sc->res);
}
return (err);
}
static int
aw_nmi_attach(device_t dev)
{
struct aw_nmi_softc *sc;
phandle_t xref;
sc = device_get_softc(dev);
sc->dev = dev;
if (bus_alloc_resources(dev, aw_nmi_res_spec, sc->res) != 0) {
device_printf(dev, "can't allocate device resources\n");
return (ENXIO);
}
if ((bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC,
aw_nmi_intr, NULL, sc, &sc->intrcookie))) {
device_printf(dev, "unable to register interrupt handler\n");
bus_release_resources(dev, aw_nmi_res_spec, sc->res);
return (ENXIO);
}
switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
case A20_NMI:
sc->enable_reg = A20_NMI_IRQ_ENABLE_REG;
break;
case A31_NMI:
sc->enable_reg = A31_NMI_IRQ_ENABLE_REG;
break;
}
/* Disable and clear interrupts */
SC_NMI_WRITE(sc, sc->enable_reg, !NMI_IRQ_ENABLE);
SC_NMI_WRITE(sc, NMI_IRQ_PENDING_REG, NMI_IRQ_ACK);
xref = OF_xref_from_node(ofw_bus_get_node(dev));
/* Register our isrc */
sc->intr.irq = 0;
sc->intr.pol = INTR_POLARITY_CONFORM;
sc->intr.tri = INTR_TRIGGER_CONFORM;
if (intr_isrc_register(&sc->intr.isrc, sc->dev, 0, "%s,%u",
device_get_nameunit(sc->dev), sc->intr.irq) != 0)
goto error;
if (intr_pic_register(dev, (intptr_t)xref) == NULL) {
device_printf(dev, "could not register pic\n");
goto error;
}
return (0);
error:
bus_teardown_intr(dev, sc->res[1], sc->intrcookie);
bus_release_resources(dev, aw_nmi_res_spec, sc->res);
return (ENXIO);
}
static int
imx6_anatop_attach(device_t dev)
{
struct imx6_anatop_softc *sc;
int err;
sc = device_get_softc(dev);
sc->dev = dev;
/* Allocate bus_space resources. */
if (bus_alloc_resources(dev, imx6_anatop_spec, sc->res)) {
device_printf(dev, "Cannot allocate resources\n");
err = ENXIO;
goto out;
}
sc->intr_setup_hook.ich_func = intr_setup;
sc->intr_setup_hook.ich_arg = sc;
config_intrhook_establish(&sc->intr_setup_hook);
SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
OID_AUTO, "cpu_voltage", CTLFLAG_RD,
&sc->cpu_curmv, 0, "Current CPU voltage in millivolts");
imx6_anatop_sc = sc;
/*
* Other code seen on the net sets this SELFBIASOFF flag around the same
* time the temperature sensor is set up, although it's unclear how the
* two are related (if at all).
*/
imx6_anatop_write_4(IMX6_ANALOG_PMU_MISC0_SET,
IMX6_ANALOG_PMU_MISC0_SELFBIASOFF);
/*
* Some day, when we're ready to deal with the actual anatop regulators
* that are described in fdt data as children of this "bus", this would
* be the place to invoke a simplebus helper routine to instantiate the
* children from the fdt data.
*/
err = 0;
out:
if (err != 0) {
bus_release_resources(dev, imx6_anatop_spec, sc->res);
}
return (err);
}
static int
edma_attach(device_t dev)
{
struct edma_softc *sc;
phandle_t node;
int dts_value;
int len;
sc = device_get_softc(dev);
sc->dev = dev;
if ((node = ofw_bus_get_node(sc->dev)) == -1)
return (ENXIO);
if ((len = OF_getproplen(node, "device-id")) <= 0)
return (ENXIO);
OF_getprop(node, "device-id", &dts_value, len);
sc->device_id = fdt32_to_cpu(dts_value);
sc->dma_stop = dma_stop;
sc->dma_setup = dma_setup;
sc->dma_request = dma_request;
sc->channel_configure = channel_configure;
sc->channel_free = channel_free;
if (bus_alloc_resources(dev, edma_spec, sc->res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
/* Memory interface */
sc->bst = rman_get_bustag(sc->res[0]);
sc->bsh = rman_get_bushandle(sc->res[0]);
sc->bst_tcd = rman_get_bustag(sc->res[1]);
sc->bsh_tcd = rman_get_bushandle(sc->res[1]);
/* Setup interrupt handlers */
if (bus_setup_intr(dev, sc->res[2], INTR_TYPE_BIO | INTR_MPSAFE,
NULL, edma_transfer_complete_intr, sc, &sc->tc_ih)) {
device_printf(dev, "Unable to alloc DMA intr resource.\n");
return (ENXIO);
}
if (bus_setup_intr(dev, sc->res[3], INTR_TYPE_BIO | INTR_MPSAFE,
NULL, edma_err_intr, sc, &sc->err_ih)) {
device_printf(dev, "Unable to alloc DMA Err intr resource.\n");
return (ENXIO);
}
return (0);
}
static int
jz4780_dme_attach(device_t dev)
{
struct jz4780_dme_softc *sc = device_get_softc(dev);
sc->dev = dev;
if (bus_alloc_resources(dev, jz4780_dme_spec, sc->res)) {
device_printf(dev, "could not allocate resources for device\n");
return (ENXIO);
}
return (0);
}
static int
pcii_attach(device_t dev)
{
struct pcii_softc *sc;
u_long start, count;
int unit;
int rid;
int error = 0;
unit = device_get_unit(dev);
sc = device_get_softc(dev);
memset(sc, 0, sizeof *sc);
device_set_desc(dev, "PCII IEEE-4888 controller");
if (bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &count) != 0) {
printf("pcii_attach: cannot obtain IRQ number\n");
return ENXIO;
}
error = bus_alloc_resources(dev, pcii_res_spec, sc->res);
if (error)
return (error);
error = bus_setup_intr(dev, sc->res[0],
INTR_TYPE_MISC | INTR_MPSAFE, NULL,
upd7210intr, &sc->upd7210, &sc->intr_handler);
if (error) {
bus_release_resources(dev, pcii_res_spec, sc->res);
return (error);
}
for (rid = 0; rid < 8; rid++) {
sc->upd7210.reg_res[rid] = sc->res[2 + rid];
sc->upd7210.reg_offset[rid] = 0;
}
sc->upd7210.irq_clear_res = sc->res[10];
sc->upd7210.use_fifo = 0;
if (sc->res[1] == NULL)
sc->upd7210.dmachan = -1;
else
sc->upd7210.dmachan = rman_get_start(sc->res[1]);
upd7210attach(&sc->upd7210);
device_printf(dev, "attached gpib%d\n", sc->upd7210.unit);
return (0);
}
static int
tegra_lic_attach(device_t dev)
{
struct tegra_lic_sc *sc;
phandle_t node;
phandle_t parent_xref;
int i, rv;
sc = device_get_softc(dev);
sc->dev = dev;
node = ofw_bus_get_node(dev);
rv = OF_getencprop(node, "interrupt-parent", &parent_xref,
sizeof(parent_xref));
if (rv <= 0) {
device_printf(dev, "Cannot read parent node property\n");
goto fail;
}
sc->parent = OF_device_from_xref(parent_xref);
if (sc->parent == NULL) {
device_printf(dev, "Cannott find parent controller\n");
goto fail;
}
if (bus_alloc_resources(dev, lic_spec, sc->mem_res)) {
device_printf(dev, "Cannott allocate resources\n");
goto fail;
}
/* Disable all interrupts, route all to irq */
for (i = 0; i < nitems(lic_spec); i++) {
if (sc->mem_res[i] == NULL)
continue;
WR4(sc, i, LIC_CPU_IER_CLR, 0xFFFFFFFF);
WR4(sc, i, LIC_CPU_IEP_CLASS, 0);
}
if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) {
device_printf(dev, "Cannot register PIC\n");
goto fail;
}
return (0);
fail:
bus_release_resources(dev, lic_spec, sc->mem_res);
return (ENXIO);
}
