static int
sfxge_intr_bus_enable(struct sfxge_softc *sc)
{
struct sfxge_intr *intr;
struct sfxge_intr_hdl *table;
driver_filter_t *filter;
driver_intr_t *handler;
int index;
int err;
intr = &sc->intr;
table = intr->table;
switch (intr->type) {
case EFX_INTR_MESSAGE:
filter = NULL; /* not shared */
handler = sfxge_intr_message;
break;
case EFX_INTR_LINE:
filter = sfxge_intr_line_filter;
handler = sfxge_intr_line;
break;
default:
KASSERT(0, ("Invalid interrupt type"));
return EINVAL;
}
/* Try to add the handlers */
for (index = 0; index < intr->n_alloc; index++) {
if ((err = bus_setup_intr(sc->dev, table[index].eih_res,
INTR_MPSAFE|INTR_TYPE_NET, filter, handler,
sc->evq[index], &table[index].eih_tag)) != 0) {
goto fail;
}
#ifdef SFXGE_HAVE_DESCRIBE_INTR
if (intr->n_alloc > 1)
bus_describe_intr(sc->dev, table[index].eih_res,
table[index].eih_tag, "%d", index);
#endif
bus_bind_intr(sc->dev, table[index].eih_res, index);
}
return (0);
fail:
/* Remove remaining handlers */
while (--index >= 0)
bus_teardown_intr(sc->dev, table[index].eih_res,
table[index].eih_tag);
return (err);
}
static int
gx_attach(device_t dev)
{
struct ifnet *ifp;
struct gx_softc *sc;
uint8_t mac[6];
int error;
int rid;
sc = device_get_softc(dev);
sc->sc_dev = dev;
sc->sc_port = device_get_unit(dev);
/* Read MAC address. */
GXEMUL_ETHER_DEV_WRITE(GXEMUL_ETHER_DEV_MAC, (uintptr_t)mac);
/* Allocate and establish interrupt. */
rid = 0;
sc->sc_intr = bus_alloc_resource(sc->sc_dev, SYS_RES_IRQ, &rid,
GXEMUL_ETHER_DEV_IRQ - 2, GXEMUL_ETHER_DEV_IRQ - 2, 1, RF_ACTIVE);
if (sc->sc_intr == NULL) {
device_printf(dev, "unable to allocate IRQ.\n");
return (ENXIO);
}
error = bus_setup_intr(sc->sc_dev, sc->sc_intr, INTR_TYPE_NET, NULL,
gx_rx_intr, sc, &sc->sc_intr_cookie);
if (error != 0) {
device_printf(dev, "unable to setup interrupt.\n");
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_intr);
return (ENXIO);
}
bus_describe_intr(sc->sc_dev, sc->sc_intr, sc->sc_intr_cookie, "rx");
ifp = if_alloc(IFT_ETHER);
if (ifp == NULL) {
device_printf(dev, "cannot allocate ifnet.\n");
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_intr);
return (ENOMEM);
}
if_initname(ifp, device_get_name(dev), device_get_unit(dev));
ifp->if_mtu = ETHERMTU;
ifp->if_init = gx_init;
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | IFF_ALLMULTI;
ifp->if_ioctl = gx_ioctl;
sc->sc_ifp = ifp;
sc->sc_flags = ifp->if_flags;
ifmedia_init(&sc->sc_ifmedia, 0, gx_medchange, gx_medstat);
ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO);
mtx_init(&sc->sc_mtx, "GXemul Ethernet", NULL, MTX_DEF);
ether_ifattach(ifp, mac);
ifp->if_transmit = gx_transmit;
return (bus_generic_attach(dev));
}
static int
octm_attach(device_t dev)
{
struct ifnet *ifp;
struct octm_softc *sc;
cvmx_mixx_irhwm_t mixx_irhwm;
cvmx_mixx_intena_t mixx_intena;
uint64_t mac;
int error;
int irq;
int rid;
sc = device_get_softc(dev);
sc->sc_dev = dev;
sc->sc_port = device_get_unit(dev);
switch (sc->sc_port) {
case 0:
irq = OCTEON_IRQ_MII;
break;
case 1:
irq = OCTEON_IRQ_MII1;
break;
default:
device_printf(dev, "unsupported management port %u.\n", sc->sc_port);
return (ENXIO);
}
/*
* Set MAC address for this management port.
*/
mac = 0;
memcpy((u_int8_t *)&mac + 2, cvmx_sysinfo_get()->mac_addr_base, 6);
mac += sc->sc_port;
cvmx_mgmt_port_set_mac(sc->sc_port, mac);
/* No watermark for input ring. */
mixx_irhwm.u64 = 0;
cvmx_write_csr(CVMX_MIXX_IRHWM(sc->sc_port), mixx_irhwm.u64);
/* Enable input ring interrupts. */
mixx_intena.u64 = 0;
mixx_intena.s.ithena = 1;
cvmx_write_csr(CVMX_MIXX_INTENA(sc->sc_port), mixx_intena.u64);
/* Allocate and establish interrupt. */
rid = 0;
sc->sc_intr = bus_alloc_resource(sc->sc_dev, SYS_RES_IRQ, &rid,
irq, irq, 1, RF_ACTIVE);
if (sc->sc_intr == NULL) {
device_printf(dev, "unable to allocate IRQ.\n");
return (ENXIO);
}
error = bus_setup_intr(sc->sc_dev, sc->sc_intr, INTR_TYPE_NET, NULL,
octm_rx_intr, sc, &sc->sc_intr_cookie);
if (error != 0) {
device_printf(dev, "unable to setup interrupt.\n");
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_intr);
return (ENXIO);
}
bus_describe_intr(sc->sc_dev, sc->sc_intr, sc->sc_intr_cookie, "rx");
/* XXX Possibly should enable TX interrupts. */
ifp = if_alloc(IFT_ETHER);
if (ifp == NULL) {
device_printf(dev, "cannot allocate ifnet.\n");
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_intr);
return (ENOMEM);
}
if_initname(ifp, device_get_name(dev), device_get_unit(dev));
ifp->if_mtu = ETHERMTU;
ifp->if_init = octm_init;
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | IFF_ALLMULTI;
ifp->if_ioctl = octm_ioctl;
sc->sc_ifp = ifp;
sc->sc_flags = ifp->if_flags;
ifmedia_init(&sc->sc_ifmedia, 0, octm_medchange, octm_medstat);
ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO);
ether_ifattach(ifp, (const u_int8_t *)&mac + 2);
ifp->if_transmit = octm_transmit;
ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
ifp->if_capabilities = IFCAP_VLAN_MTU;
ifp->if_capenable = ifp->if_capabilities;
IFQ_SET_MAXLEN(&ifp->if_snd, CVMX_MGMT_PORT_NUM_TX_BUFFERS);
ifp->if_snd.ifq_drv_maxlen = CVMX_MGMT_PORT_NUM_TX_BUFFERS;
IFQ_SET_READY(&ifp->if_snd);
return (bus_generic_attach(dev));
}
static int
dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx)
{
device_t pcib;
struct dmar_msi_data *dmd;
uint64_t msi_addr;
uint32_t msi_data;
int error;
dmd = &unit->intrs[idx];
pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */
error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq);
if (error != 0) {
device_printf(dev, "cannot allocate %s interrupt, %d\n",
dmd->name, error);
goto err1;
}
error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid,
dmd->irq, 1);
if (error != 0) {
device_printf(dev, "cannot set %s interrupt resource, %d\n",
dmd->name, error);
goto err2;
}
dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&dmd->irq_rid, RF_ACTIVE);
if (dmd->irq_res == NULL) {
device_printf(dev,
"cannot allocate resource for %s interrupt\n", dmd->name);
error = ENXIO;
goto err3;
}
error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC,
dmd->handler, NULL, unit, &dmd->intr_handle);
if (error != 0) {
device_printf(dev, "cannot setup %s interrupt, %d\n",
dmd->name, error);
goto err4;
}
bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name);
error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data);
if (error != 0) {
device_printf(dev, "cannot map %s interrupt, %d\n",
dmd->name, error);
goto err5;
}
dmar_write4(unit, dmd->msi_data_reg, msi_data);
dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
/* Only for xAPIC mode */
dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
return (0);
err5:
bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
err4:
bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
err3:
bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
err2:
PCIB_RELEASE_MSIX(pcib, dev, dmd->irq);
dmd->irq = -1;
err1:
return (error);
}