static int
mv_mpic_attach(device_t dev)
{
struct mv_mpic_softc *sc;
int error;
uint32_t val;
sc = (struct mv_mpic_softc *)device_get_softc(dev);
if (mv_mpic_sc != NULL)
return (ENXIO);
mv_mpic_sc = sc;
sc->sc_dev = dev;
mtx_init(&sc->mtx, "MPIC lock", NULL, MTX_SPIN);
error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res);
if (error) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
#ifdef INTRNG
if (sc->mpic_res[3] == NULL)
device_printf(dev, "No interrupt to use.\n");
else
bus_setup_intr(dev, sc->mpic_res[3], INTR_TYPE_CLK,
mpic_intr, NULL, sc, &sc->intr_hand);
#endif
sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]);
sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]);
sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]);
sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]);
if (sc->mpic_res[2] != NULL) {
/* This is required only if MSIs are used. */
sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]);
sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]);
}
bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh,
MPIC_CTRL, 1);
MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0);
val = MPIC_READ(mv_mpic_sc, MPIC_CTRL);
sc->nirqs = MPIC_CTRL_NIRQS(val);
#ifdef INTRNG
if (mv_mpic_register_isrcs(sc) != 0) {
device_printf(dev, "could not register PIC ISRCs\n");
bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
return (ENXIO);
}
if (intr_pic_register(dev, OF_xref_from_device(dev)) != 0) {
device_printf(dev, "could not register PIC\n");
bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
return (ENXIO);
}
#endif
mpic_unmask_msi();
return (0);
}
static int
octusb_octeon_attach(device_t dev)
{
struct octusb_octeon_softc *sc = device_get_softc(dev);
int err;
int rid;
int nports;
int i;
/* setup controller interface softc */
/* initialise some bus fields */
sc->sc_dci.sc_bus.parent = dev;
sc->sc_dci.sc_bus.devices = sc->sc_dci.sc_devices;
sc->sc_dci.sc_bus.devices_max = OCTUSB_MAX_DEVICES;
sc->sc_dci.sc_bus.dma_bits = 32;
/* get all DMA memory */
if (usb_bus_mem_alloc_all(&sc->sc_dci.sc_bus,
USB_GET_DMA_TAG(dev), NULL)) {
return (ENOMEM);
}
nports = cvmx_usb_get_num_ports();
if (nports > OCTUSB_MAX_PORTS)
panic("octusb: too many USB ports %d", nports);
for (i = 0; i < nports; i++) {
rid = 0;
sc->sc_dci.sc_irq_res[i] =
bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
OCTEON_IRQ_USB0 + i, OCTEON_IRQ_USB0 + i, 1, RF_ACTIVE);
if (!(sc->sc_dci.sc_irq_res[i])) {
goto error;
}
#if (__FreeBSD_version >= 700031)
err = bus_setup_intr(dev, sc->sc_dci.sc_irq_res[i], INTR_TYPE_BIO | INTR_MPSAFE,
NULL, (driver_intr_t *)octusb_interrupt, sc, &sc->sc_dci.sc_intr_hdl[i]);
#else
err = bus_setup_intr(dev, sc->sc_dci.sc_irq_res[i], INTR_TYPE_BIO | INTR_MPSAFE,
(driver_intr_t *)octusb_interrupt, sc, &sc->sc_dci.sc_intr_hdl[i]);
#endif
if (err) {
sc->sc_dci.sc_intr_hdl[i] = NULL;
goto error;
}
}
sc->sc_dci.sc_bus.bdev = device_add_child(dev, "usbus", -1);
if (!(sc->sc_dci.sc_bus.bdev)) {
goto error;
}
device_set_ivars(sc->sc_dci.sc_bus.bdev, &sc->sc_dci.sc_bus);
err = octusb_init(&sc->sc_dci);
if (!err) {
err = device_probe_and_attach(sc->sc_dci.sc_bus.bdev);
}
if (err) {
goto error;
}
return (0);
error:
octusb_octeon_detach(dev);
return (ENXIO);
}
int
openpic_attach(device_t dev)
{
struct openpic_softc *sc;
u_int cpu, ipi, irq;
u_int32_t x;
sc = device_get_softc(dev);
sc->sc_dev = dev;
sc->sc_rid = 0;
sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
RF_ACTIVE);
if (sc->sc_memr == NULL) {
device_printf(dev, "Could not alloc mem resource!\n");
return (ENXIO);
}
sc->sc_bt = rman_get_bustag(sc->sc_memr);
sc->sc_bh = rman_get_bushandle(sc->sc_memr);
/* Reset the PIC */
x = openpic_read(sc, OPENPIC_CONFIG);
x |= OPENPIC_CONFIG_RESET;
openpic_write(sc, OPENPIC_CONFIG, x);
while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
powerpc_sync();
DELAY(100);
}
/* Check if this is a cascaded PIC */
sc->sc_irq = 0;
sc->sc_intr = NULL;
do {
struct resource_list *rl;
rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev);
if (rl == NULL)
break;
if (resource_list_find(rl, SYS_RES_IRQ, 0) == NULL)
break;
sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&sc->sc_irq, RF_ACTIVE);
/* XXX Cascaded PICs pass NULL trapframes! */
bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE,
openpic_intr, NULL, dev, &sc->sc_icookie);
} while (0);
/* Reset the PIC */
x = openpic_read(sc, OPENPIC_CONFIG);
x |= OPENPIC_CONFIG_RESET;
openpic_write(sc, OPENPIC_CONFIG, x);
while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
powerpc_sync();
DELAY(100);
}
x = openpic_read(sc, OPENPIC_FEATURE);
switch (x & OPENPIC_FEATURE_VERSION_MASK) {
case 1:
sc->sc_version = "1.0";
break;
case 2:
sc->sc_version = "1.2";
break;
case 3:
sc->sc_version = "1.3";
break;
default:
sc->sc_version = "unknown";
break;
}
sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >>
OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1;
sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >>
OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1;
/*
* PSIM seems to report 1 too many IRQs and CPUs
*/
if (sc->sc_psim) {
sc->sc_nirq--;
sc->sc_ncpu--;
}
if (bootverbose)
device_printf(dev,
"Version %s, supports %d CPUs and %d irqs\n",
sc->sc_version, sc->sc_ncpu, sc->sc_nirq);
for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 15);
/* Reset and disable all interrupts. */
for (irq = 0; irq < sc->sc_nirq; irq++) {
x = irq; /* irq == vector. */
x |= OPENPIC_IMASK;
x |= OPENPIC_POLARITY_NEGATIVE;
x |= OPENPIC_SENSE_LEVEL;
x |= 8 << OPENPIC_PRIORITY_SHIFT;
openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
}
/* Reset and disable all IPIs. */
for (ipi = 0; ipi < 4; ipi++) {
x = sc->sc_nirq + ipi;
x |= OPENPIC_IMASK;
x |= 15 << OPENPIC_PRIORITY_SHIFT;
openpic_write(sc, OPENPIC_IPI_VECTOR(ipi), x);
}
/* we don't need 8259 passthrough mode */
x = openpic_read(sc, OPENPIC_CONFIG);
x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
openpic_write(sc, OPENPIC_CONFIG, x);
/* send all interrupts to cpu 0 */
for (irq = 0; irq < sc->sc_nirq; irq++)
openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0);
/* clear all pending interrupts from cpu 0 */
for (irq = 0; irq < sc->sc_nirq; irq++) {
(void)openpic_read(sc, OPENPIC_PCPU_IACK(0));
openpic_write(sc, OPENPIC_PCPU_EOI(0), 0);
}
for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0);
powerpc_register_pic(dev, sc->sc_nirq);
/* If this is not a cascaded PIC, it must be the root PIC */
if (sc->sc_intr == NULL)
root_pic = dev;
return (0);
}
static int
ti_i2c_attach(device_t dev)
{
int err, rid;
phandle_t node;
struct ti_i2c_softc *sc;
struct sysctl_ctx_list *ctx;
struct sysctl_oid_list *tree;
uint16_t fifosz;
sc = device_get_softc(dev);
sc->sc_dev = dev;
/* Get the i2c device id from FDT. */
node = ofw_bus_get_node(dev);
if ((OF_getencprop(node, "i2c-device-id", &sc->device_id,
sizeof(sc->device_id))) <= 0) {
device_printf(dev, "missing i2c-device-id attribute in FDT\n");
return (ENXIO);
}
/* Get the memory resource for the register mapping. */
rid = 0;
sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (sc->sc_mem_res == NULL) {
device_printf(dev, "Cannot map registers.\n");
return (ENXIO);
}
/* Allocate our IRQ resource. */
rid = 0;
sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_ACTIVE | RF_SHAREABLE);
if (sc->sc_irq_res == NULL) {
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
device_printf(dev, "Cannot allocate interrupt.\n");
return (ENXIO);
}
TI_I2C_LOCK_INIT(sc);
/* First of all, we _must_ activate the H/W. */
err = ti_i2c_activate(dev);
if (err) {
device_printf(dev, "ti_i2c_activate failed\n");
goto out;
}
/* Read the version number of the I2C module */
sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff;
/* Get the fifo size. */
fifosz = ti_i2c_read_2(sc, I2C_REG_BUFSTAT);
fifosz >>= I2C_BUFSTAT_FIFODEPTH_SHIFT;
fifosz &= I2C_BUFSTAT_FIFODEPTH_MASK;
device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n",
sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz);
/* Set the FIFO threshold to 5 for now. */
sc->sc_fifo_trsh = 5;
ctx = device_get_sysctl_ctx(dev);
tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_clock",
CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_MPSAFE, dev, 0,
ti_i2c_sysctl_clk, "IU", "I2C bus clock");
/* Activate the interrupt. */
err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
NULL, ti_i2c_intr, sc, &sc->sc_irq_h);
if (err)
goto out;
/* Attach the iicbus. */
if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
device_printf(dev, "could not allocate iicbus instance\n");
err = ENXIO;
goto out;
}
/* Probe and attach the iicbus */
bus_generic_attach(dev);
out:
if (err) {
ti_i2c_deactivate(dev);
TI_I2C_LOCK_DESTROY(sc);
}
return (err);
}
static int
at91_mci_attach(device_t dev)
{
struct at91_mci_softc *sc = device_get_softc(dev);
struct sysctl_ctx_list *sctx;
struct sysctl_oid *soid;
device_t child;
int err, i;
sctx = device_get_sysctl_ctx(dev);
soid = device_get_sysctl_tree(dev);
sc->dev = dev;
sc->sc_cap = 0;
if (at91_is_rm92())
sc->sc_cap |= CAP_NEEDS_BYTESWAP;
/*
* MCI1 Rev 2 controllers need some workarounds, flag if so.
*/
if (at91_mci_is_mci1rev2xx())
sc->sc_cap |= CAP_MCI1_REV2XX;
err = at91_mci_activate(dev);
if (err)
goto out;
AT91_MCI_LOCK_INIT(sc);
at91_mci_fini(dev);
at91_mci_init(dev);
/*
* Allocate DMA tags and maps and bounce buffers.
*
* The parms in the tag_create call cause the dmamem_alloc call to
* create each bounce buffer as a single contiguous buffer of BBSIZE
* bytes aligned to a 4096 byte boundary.
*
* Do not use DMA_COHERENT for these buffers because that maps the
* memory as non-cachable, which prevents cache line burst fills/writes,
* which is something we need since we're trying to overlap the
* byte-swapping with the DMA operations.
*/
err = bus_dma_tag_create(bus_get_dma_tag(dev), 4096, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
BBSIZE, 1, BBSIZE, 0, NULL, NULL, &sc->dmatag);
if (err != 0)
goto out;
for (i = 0; i < BBCOUNT; ++i) {
err = bus_dmamem_alloc(sc->dmatag, (void **)&sc->bbuf_vaddr[i],
BUS_DMA_NOWAIT, &sc->bbuf_map[i]);
if (err != 0)
goto out;
}
/*
* Activate the interrupt
*/
err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
NULL, at91_mci_intr, sc, &sc->intrhand);
if (err) {
AT91_MCI_LOCK_DESTROY(sc);
goto out;
}
/*
* Allow 4-wire to be initially set via #define.
* Allow a device hint to override that.
* Allow a sysctl to override that.
*/
#if defined(AT91_MCI_HAS_4WIRE) && AT91_MCI_HAS_4WIRE != 0
sc->has_4wire = 1;
#endif
resource_int_value(device_get_name(dev), device_get_unit(dev),
"4wire", &sc->has_4wire);
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "4wire",
CTLFLAG_RW, &sc->has_4wire, 0, "has 4 wire SD Card bus");
if (sc->has_4wire)
sc->sc_cap |= CAP_HAS_4WIRE;
sc->allow_overclock = AT91_MCI_ALLOW_OVERCLOCK;
resource_int_value(device_get_name(dev), device_get_unit(dev),
"allow_overclock", &sc->allow_overclock);
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "allow_overclock",
CTLFLAG_RW, &sc->allow_overclock, 0,
"Allow up to 30MHz clock for 25MHz request when next highest speed 15MHz or less.");
/*
* Our real min freq is master_clock/512, but upper driver layers are
* going to set the min speed during card discovery, and the right speed
* for that is 400kHz, so advertise a safe value just under that.
*
* For max speed, while the rm9200 manual says the max is 50mhz, it also
* says it supports only the SD v1.0 spec, which means the real limit is
* 25mhz. On the other hand, historical use has been to slightly violate
* the standard by running the bus at 30MHz. For more information on
* that, see the comments at the top of this file.
*/
sc->host.f_min = 375000;
sc->host.f_max = at91_master_clock / 2;
if (sc->host.f_max > 25000000)
sc->host.f_max = 25000000;
sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
sc->host.caps = 0;
if (sc->sc_cap & CAP_HAS_4WIRE)
sc->host.caps |= MMC_CAP_4_BIT_DATA;
child = device_add_child(dev, "mmc", 0);
device_set_ivars(dev, &sc->host);
err = bus_generic_attach(dev);
out:
if (err)
at91_mci_deactivate(dev);
return (err);
}
static int
ohci_pci_attach(device_t self)
{
ohci_softc_t *sc = device_get_softc(self);
int err;
int rid;
/* XXX where does it say so in the spec? */
sc->sc_bus.usbrev = USBREV_1_0;
pci_enable_busmaster(self);
/*
* Some Sun PCIO-2 USB controllers have their intpin register
* bogusly set to 0, although it should be 4. Correct that.
*/
if (pci_get_devid(self) == PCI_OHCI_DEVICEID_PCIO2USB &&
pci_get_intpin(self) == 0)
pci_set_intpin(self, 4);
rid = PCI_CBMEM;
sc->io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->io_res) {
device_printf(self, "Could not map memory\n");
return ENXIO;
}
sc->iot = rman_get_bustag(sc->io_res);
sc->ioh = rman_get_bushandle(sc->io_res);
rid = 0;
sc->irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->irq_res == NULL) {
device_printf(self, "Could not allocate irq\n");
ohci_pci_detach(self);
return ENXIO;
}
sc->sc_bus.bdev = device_add_child(self, "usb", -1);
if (!sc->sc_bus.bdev) {
device_printf(self, "Could not add USB device\n");
ohci_pci_detach(self);
return ENOMEM;
}
device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
/* ohci_pci_match will never return NULL if ohci_pci_probe succeeded */
device_set_desc(sc->sc_bus.bdev, ohci_pci_match(self));
switch (pci_get_vendor(self)) {
case PCI_OHCI_VENDORID_ACERLABS:
sprintf(sc->sc_vendor, "AcerLabs");
break;
case PCI_OHCI_VENDORID_AMD:
sprintf(sc->sc_vendor, "AMD");
break;
case PCI_OHCI_VENDORID_APPLE:
sprintf(sc->sc_vendor, "Apple");
break;
case PCI_OHCI_VENDORID_ATI:
sprintf(sc->sc_vendor, "ATI");
break;
case PCI_OHCI_VENDORID_CMDTECH:
sprintf(sc->sc_vendor, "CMDTECH");
break;
case PCI_OHCI_VENDORID_NEC:
sprintf(sc->sc_vendor, "NEC");
break;
case PCI_OHCI_VENDORID_NVIDIA:
case PCI_OHCI_VENDORID_NVIDIA2:
sprintf(sc->sc_vendor, "nVidia");
break;
case PCI_OHCI_VENDORID_OPTI:
sprintf(sc->sc_vendor, "OPTi");
break;
case PCI_OHCI_VENDORID_SIS:
sprintf(sc->sc_vendor, "SiS");
break;
default:
if (bootverbose)
device_printf(self, "(New OHCI DeviceId=0x%08x)\n",
pci_get_devid(self));
sprintf(sc->sc_vendor, "(0x%04x)", pci_get_vendor(self));
}
err = bus_setup_intr(self, sc->irq_res, INTR_TYPE_BIO, NULL, ohci_intr,
sc, &sc->ih);
if (err) {
device_printf(self, "Could not setup irq, %d\n", err);
sc->ih = NULL;
ohci_pci_detach(self);
return ENXIO;
}
/* Allocate a parent dma tag for DMA maps */
err = bus_dma_tag_create(bus_get_dma_tag(self), 1, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
BUS_SPACE_MAXSIZE_32BIT, USB_DMA_NSEG, BUS_SPACE_MAXSIZE_32BIT, 0,
NULL, NULL, &sc->sc_bus.parent_dmatag);
if (err) {
device_printf(self, "Could not allocate parent DMA tag (%d)\n",
err);
ohci_pci_detach(self);
return ENXIO;
}
/* Allocate a dma tag for transfer buffers */
err = bus_dma_tag_create(sc->sc_bus.parent_dmatag, 1, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
BUS_SPACE_MAXSIZE_32BIT, USB_DMA_NSEG, BUS_SPACE_MAXSIZE_32BIT, 0,
busdma_lock_mutex, &Giant, &sc->sc_bus.buffer_dmatag);
if (err) {
device_printf(self, "Could not allocate transfer tag (%d)\n",
err);
ohci_pci_detach(self);
return ENXIO;
}
err = ohci_init(sc);
if (!err) {
sc->sc_flags |= OHCI_SCFLG_DONEINIT;
err = device_probe_and_attach(sc->sc_bus.bdev);
}
if (err) {
device_printf(self, "USB init failed\n");
ohci_pci_detach(self);
return EIO;
}
return 0;
}
int cvm_oct_rgmii_init(struct ifnet *ifp)
{
struct octebus_softc *sc;
cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
int error;
int rid;
if (cvm_oct_common_init(ifp) != 0)
return ENXIO;
priv->open = cvm_oct_common_open;
priv->stop = cvm_oct_common_stop;
priv->stop(ifp);
/* Due to GMX errata in CN3XXX series chips, it is necessary to take the
link down immediately whne the PHY changes state. In order to do this
we call the poll function every time the RGMII inband status changes.
This may cause problems if the PHY doesn't implement inband status
properly */
if (number_rgmii_ports == 0) {
sc = device_get_softc(device_get_parent(priv->dev));
rid = 0;
sc->sc_rgmii_irq = bus_alloc_resource(sc->sc_dev, SYS_RES_IRQ,
&rid, OCTEON_IRQ_RML,
OCTEON_IRQ_RML, 1,
RF_ACTIVE);
if (sc->sc_rgmii_irq == NULL) {
device_printf(sc->sc_dev, "could not allocate RGMII irq");
return ENXIO;
}
error = bus_setup_intr(sc->sc_dev, sc->sc_rgmii_irq,
INTR_TYPE_NET | INTR_MPSAFE,
cvm_oct_rgmii_rml_interrupt, NULL,
&number_rgmii_ports, NULL);
if (error != 0) {
device_printf(sc->sc_dev, "could not setup RGMII irq");
return error;
}
}
number_rgmii_ports++;
/* Only true RGMII ports need to be polled. In GMII mode, port 0 is really
a RGMII port */
if (((priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII) && (priv->port == 0)) ||
(priv->imode == CVMX_HELPER_INTERFACE_MODE_RGMII)) {
if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) {
cvmx_gmxx_rxx_int_en_t gmx_rx_int_en;
int interface = INTERFACE(priv->port);
int index = INDEX(priv->port);
/* Enable interrupts on inband status changes for this port */
gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(index, interface));
gmx_rx_int_en.s.phy_dupx = 1;
gmx_rx_int_en.s.phy_link = 1;
gmx_rx_int_en.s.phy_spd = 1;
cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, interface), gmx_rx_int_en.u64);
priv->poll = cvm_oct_rgmii_poll;
}
}
return 0;
}
static int
iir_pci_attach(device_t dev)
{
struct gdt_softc *gdt;
struct resource *io = NULL, *irq = NULL;
int retries, rid, error = 0;
void *ih;
u_int8_t protocol;
/* map DPMEM */
rid = PCI_DPMEM;
io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
if (io == NULL) {
device_printf(dev, "can't allocate register resources\n");
error = ENOMEM;
goto err;
}
/* get IRQ */
rid = 0;
irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_ACTIVE | RF_SHAREABLE);
if (irq == NULL) {
device_printf(dev, "can't find IRQ value\n");
error = ENOMEM;
goto err;
}
gdt = device_get_softc(dev);
gdt->sc_devnode = dev;
gdt->sc_init_level = 0;
gdt->sc_dpmemt = rman_get_bustag(io);
gdt->sc_dpmemh = rman_get_bushandle(io);
gdt->sc_dpmembase = rman_get_start(io);
gdt->sc_hanum = device_get_unit(dev);
gdt->sc_bus = pci_get_bus(dev);
gdt->sc_slot = pci_get_slot(dev);
gdt->sc_vendor = pci_get_vendor(dev);
gdt->sc_device = pci_get_device(dev);
gdt->sc_subdevice = pci_get_subdevice(dev);
gdt->sc_class = GDT_MPR;
/* no FC ctr.
if (gdt->sc_device >= GDT_PCI_PRODUCT_FC)
gdt->sc_class |= GDT_FC;
*/
/* initialize RP controller */
/* check and reset interface area */
bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC,
htole32(GDT_MPR_MAGIC));
if (bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC) !=
htole32(GDT_MPR_MAGIC)) {
printf("cannot access DPMEM at 0x%jx (shadowed?)\n",
(uintmax_t)gdt->sc_dpmembase);
error = ENXIO;
goto err;
}
bus_space_set_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_I960_SZ, htole32(0),
GDT_MPR_SZ >> 2);
/* Disable everything */
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN,
bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
GDT_EDOOR_EN) | 4);
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff);
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
0);
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_CMD_INDEX,
0);
bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO,
htole32(gdt->sc_dpmembase));
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
0xff);
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
DELAY(20);
retries = GDT_RETRIES;
while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
GDT_MPR_IC + GDT_S_STATUS) != 0xff) {
if (--retries == 0) {
printf("DEINIT failed\n");
error = ENXIO;
goto err;
}
DELAY(1);
}
protocol = (uint8_t)le32toh(bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
GDT_MPR_IC + GDT_S_INFO));
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
0);
if (protocol != GDT_PROTOCOL_VERSION) {
printf("unsupported protocol %d\n", protocol);
error = ENXIO;
goto err;
}
/* special commnd to controller BIOS */
bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO,
htole32(0));
bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), htole32(0));
bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t),
htole32(1));
bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t),
htole32(0));
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
0xfe);
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
DELAY(20);
retries = GDT_RETRIES;
while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
GDT_MPR_IC + GDT_S_STATUS) != 0xfe) {
if (--retries == 0) {
printf("initialization error\n");
error = ENXIO;
goto err;
}
DELAY(1);
}
bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
0);
gdt->sc_ic_all_size = GDT_MPR_SZ;
gdt->sc_copy_cmd = gdt_mpr_copy_cmd;
gdt->sc_get_status = gdt_mpr_get_status;
gdt->sc_intr = gdt_mpr_intr;
gdt->sc_release_event = gdt_mpr_release_event;
gdt->sc_set_sema0 = gdt_mpr_set_sema0;
gdt->sc_test_busy = gdt_mpr_test_busy;
/* Allocate a dmatag representing the capabilities of this attachment */
if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev),
/*alignemnt*/1, /*boundary*/0,
/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
/*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
/*nsegments*/GDT_MAXSG,
/*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
/*flags*/0, /*lockfunc*/busdma_lock_mutex,
/*lockarg*/&Giant, &gdt->sc_parent_dmat) != 0) {
error = ENXIO;
goto err;
}
gdt->sc_init_level++;
if (iir_init(gdt) != 0) {
iir_free(gdt);
error = ENXIO;
goto err;
}
/* Register with the XPT */
iir_attach(gdt);
/* associate interrupt handler */
if (bus_setup_intr( dev, irq, INTR_TYPE_CAM,
NULL, iir_intr, gdt, &ih )) {
device_printf(dev, "Unable to register interrupt handler\n");
error = ENXIO;
goto err;
}
gdt_pci_enable_intr(gdt);
return (0);
err:
if (irq)
bus_release_resource( dev, SYS_RES_IRQ, 0, irq );
/*
if (io)
bus_release_resource( dev, SYS_RES_MEMORY, rid, io );
*/
return (error);
}
static int
digi_pci_attach(device_t dev)
{
struct digi_softc *sc;
u_int32_t device_id;
#ifdef DIGI_INTERRUPT
int retVal = 0;
#endif
sc = device_get_softc(dev);
KASSERT(sc, ("digi%d: softc not allocated in digi_pci_attach\n",
device_get_unit(dev)));
bzero(sc, sizeof(*sc));
sc->dev = dev;
sc->res.unit = device_get_unit(dev);
device_id = pci_get_devid(dev);
switch (device_id >> 16) {
case PCI_DEVICE_EPC:
sc->name = "Digiboard PCI EPC/X ASIC";
sc->res.mrid = 0x10;
sc->model = PCIEPCX;
sc->module = "EPCX_PCI";
break;
case PCI_DEVICE_XEM:
sc->name = "Digiboard PCI PC/Xem ASIC";
sc->res.mrid = 0x10;
sc->model = PCXEM;
sc->module = "Xem";
break;
case PCI_DEVICE_XR:
sc->name = "Digiboard PCI PC/Xr ASIC";
sc->res.mrid = 0x10;
sc->model = PCIXR;
sc->module = "Xr";
break;
case PCI_DEVICE_CX:
sc->name = "Digiboard PCI C/X ASIC";
sc->res.mrid = 0x10;
sc->model = PCCX;
sc->module = "CX_PCI";
break;
case PCI_DEVICE_XRJ:
sc->name = "Digiboard PCI PC/Xr PLX";
sc->res.mrid = 0x18;
sc->model = PCIXR;
sc->module = "Xr";
break;
case PCI_DEVICE_EPCJ:
sc->name = "Digiboard PCI EPC/X PLX";
sc->res.mrid = 0x18;
sc->model = PCIEPCX;
sc->module = "EPCX_PCI";
break;
case PCI_DEVICE_920_4: /* Digi PCI4r 920 */
sc->name = "Digiboard PCI4r 920";
sc->res.mrid = 0x10;
sc->model = PCIXR;
sc->module = "Xr";
break;
case PCI_DEVICE_920_8: /* Digi PCI8r 920 */
sc->name = "Digiboard PCI8r 920";
sc->res.mrid = 0x10;
sc->model = PCIXR;
sc->module = "Xr";
break;
case PCI_DEVICE_920_2: /* Digi PCI2r 920 */
sc->name = "Digiboard PCI2r 920";
sc->res.mrid = 0x10;
sc->model = PCIXR;
sc->module = "Xr";
break;
default:
device_printf(dev, "Unknown device id = %08x\n", device_id);
return (ENXIO);
}
pci_write_config(dev, 0x40, 0, 4);
pci_write_config(dev, 0x46, 0, 4);
sc->res.mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->res.mrid,
RF_ACTIVE);
#ifdef DIGI_INTERRUPT
sc->res.irqrid = 0;
sc->res.irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->res.irqrid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->res.irq == NULL) {
device_printf(dev, "couldn't map interrupt\n");
return (ENXIO);
}
retVal = bus_setup_intr(dev, sc->res.irq, INTR_TYPE_TTY,
digiintr, sc, &sc->res.irqHandler);
#else
DLOG(DIGIDB_IRQ, (sc->dev, "Interrupt support compiled out\n"));
#endif
sc->vmem = rman_get_virtual(sc->res.mem);
sc->pmem = vtophys(sc->vmem);
sc->pcibus = 1;
sc->win_size = 0x200000;
sc->win_bits = 21;
sc->csigs = &digi_normal_signals;
sc->status = DIGI_STATUS_NOTINIT;
callout_handle_init(&sc->callout);
callout_handle_init(&sc->inttest);
sc->setwin = digi_pci_setwin;
sc->hidewin = digi_pci_hidewin;
sc->towin = digi_pci_towin;
PCIPORT = FEPRST;
return (digi_attach(sc));
}
static int
dpt_eisa_attach (device_t dev)
{
dpt_softc_t * dpt;
int error = 0;
dpt = device_get_softc(dev);
dpt->dev = dev;
dpt_alloc(dev);
dpt->io_rid = 0;
dpt->io_type = SYS_RES_IOPORT;
dpt->irq_rid = 0;
error = dpt_alloc_resources(dev);
if (error) {
goto bad;
}
/* Allocate a dmatag representing the capabilities of this attachment */
if (bus_dma_tag_create( /* parent */ bus_get_dma_tag(dev),
/* alignemnt */ 1,
/* boundary */ 0,
/* lowaddr */ BUS_SPACE_MAXADDR_32BIT,
/* highaddr */ BUS_SPACE_MAXADDR,
/* filter */ NULL,
/* filterarg */ NULL,
/* maxsize */ BUS_SPACE_MAXSIZE_32BIT,
/* nsegments */ ~0,
/* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT,
/* flags */ 0,
/* lockfunc */ NULL,
/* lockarg */ NULL,
&dpt->parent_dmat) != 0) {
error = ENXIO;
goto bad;
}
if (dpt_init(dpt) != 0) {
error = ENXIO;
goto bad;
}
/* Register with the XPT */
dpt_attach(dpt);
if (bus_setup_intr(dev, dpt->irq_res, INTR_TYPE_CAM | INTR_ENTROPY |
INTR_MPSAFE, NULL, dpt_intr, dpt, &dpt->ih)) {
device_printf(dev, "Unable to register interrupt handler\n");
error = ENXIO;
goto bad;
}
return (error);
bad:
dpt_release_resources(dev);
dpt_free(dpt);
return (error);
}
static int
pcf_ebus_attach(device_t dev)
{
struct pcf_softc *sc;
int rv = ENXIO;
phandle_t node;
uint64_t own_addr;
sc = DEVTOSOFTC(dev);
mtx_init(&sc->pcf_lock, device_get_nameunit(dev), "pcf", MTX_DEF);
/* get OFW node of the pcf */
if ((node = ofw_bus_get_node(dev)) == -1) {
device_printf(dev, "cannot get OFW node\n");
goto error;
}
/* IO port is mandatory */
sc->res_ioport = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&sc->rid_ioport, RF_ACTIVE);
if (sc->res_ioport == 0) {
device_printf(dev, "cannot reserve I/O port range\n");
goto error;
}
sc->pcf_flags = device_get_flags(dev);
/*
* XXX use poll-mode property?
*/
if (!(sc->pcf_flags & IIC_POLLED)) {
sc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&sc->rid_irq, RF_ACTIVE);
if (sc->res_irq == 0) {
device_printf(dev, "can't reserve irq, polled mode.\n");
sc->pcf_flags |= IIC_POLLED;
}
}
/*
* XXX on AXmp there's probably a second IRQ which is the fan fail
* interrupt genererated by the PCF8574 at 0x78.
*/
/* get address of the pcf */
if (OF_getprop(node, "own-address", &own_addr, sizeof(own_addr)) ==
-1) {
device_printf(dev, "cannot get own address\n");
goto error;
}
if (bootverbose)
device_printf(dev, "PCF8584 address: 0x%08llx\n", (unsigned
long long)own_addr);
/* reset the chip */
pcf_rst_card(dev, IIC_FASTEST, own_addr, NULL);
if (sc->res_irq) {
rv = bus_setup_intr(dev, sc->res_irq,
INTR_TYPE_NET /* | INTR_ENTROPY */, NULL, pcf_intr, sc,
&sc->intr_cookie);
if (rv) {
device_printf(dev, "could not setup IRQ\n");
goto error;
}
}
if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL)
device_printf(dev, "could not allocate iicbus instance\n");
/* probe and attach the iicbus */
bus_generic_attach(dev);
return (0);
error:
if (sc->res_irq != 0) {
bus_release_resource(dev, SYS_RES_IRQ, sc->rid_irq,
sc->res_irq);
}
if (sc->res_ioport != 0) {
bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ioport,
sc->res_ioport);
}
mtx_destroy(&sc->pcf_lock);
return (rv);
}
static int
ohci_atmelarm_attach(device_t dev)
{
struct at91_ohci_softc *sc = device_get_softc(dev);
int err;
int rid;
/* initialise some bus fields */
sc->sc_ohci.sc_bus.parent = dev;
sc->sc_ohci.sc_bus.devices = sc->sc_ohci.sc_devices;
sc->sc_ohci.sc_bus.devices_max = OHCI_MAX_DEVICES;
sc->sc_ohci.sc_bus.dma_bits = 32;
/* get all DMA memory */
if (usb_bus_mem_alloc_all(&sc->sc_ohci.sc_bus,
USB_GET_DMA_TAG(dev), &ohci_iterate_hw_softc)) {
return (ENOMEM);
}
sc->mclk = at91_pmc_clock_ref("mck");
sc->iclk = at91_pmc_clock_ref("ohci_clk");
sc->fclk = at91_pmc_clock_ref("uhpck");
sc->sc_ohci.sc_dev = dev;
rid = MEM_RID;
sc->sc_ohci.sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&rid, RF_ACTIVE);
if (!(sc->sc_ohci.sc_io_res)) {
err = ENOMEM;
goto error;
}
sc->sc_ohci.sc_io_tag = rman_get_bustag(sc->sc_ohci.sc_io_res);
sc->sc_ohci.sc_io_hdl = rman_get_bushandle(sc->sc_ohci.sc_io_res);
sc->sc_ohci.sc_io_size = rman_get_size(sc->sc_ohci.sc_io_res);
rid = 0;
sc->sc_ohci.sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_ACTIVE);
if (!(sc->sc_ohci.sc_irq_res)) {
goto error;
}
sc->sc_ohci.sc_bus.bdev = device_add_child(dev, "usbus", -1);
if (!(sc->sc_ohci.sc_bus.bdev)) {
goto error;
}
device_set_ivars(sc->sc_ohci.sc_bus.bdev, &sc->sc_ohci.sc_bus);
strlcpy(sc->sc_ohci.sc_vendor, "Atmel", sizeof(sc->sc_ohci.sc_vendor));
err = bus_setup_intr(dev, sc->sc_ohci.sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
NULL, (driver_intr_t *)ohci_interrupt, sc, &sc->sc_ohci.sc_intr_hdl);
if (err) {
sc->sc_ohci.sc_intr_hdl = NULL;
goto error;
}
/*
* turn on the clocks from the AT91's point of view. Keep the unit in reset.
*/
at91_pmc_clock_enable(sc->mclk);
at91_pmc_clock_enable(sc->iclk);
at91_pmc_clock_enable(sc->fclk);
bus_space_write_4(sc->sc_ohci.sc_io_tag, sc->sc_ohci.sc_io_hdl,
OHCI_CONTROL, 0);
err = ohci_init(&sc->sc_ohci);
if (!err) {
err = device_probe_and_attach(sc->sc_ohci.sc_bus.bdev);
}
if (err) {
goto error;
}
return (0);
error:
ohci_atmelarm_detach(dev);
return (ENXIO);
}
static int
lpc_fb_attach(device_t dev)
{
struct lpc_fb_softc *sc = device_get_softc(dev);
struct lpc_fb_dmamap_arg ctx;
phandle_t node;
int mode, rid, err = 0;
sc->lf_dev = dev;
mtx_init(&sc->lf_mtx, "lpcfb", "fb", MTX_DEF);
rid = 0;
sc->lf_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->lf_mem_res) {
device_printf(dev, "cannot allocate memory window\n");
return (ENXIO);
}
sc->lf_bst = rman_get_bustag(sc->lf_mem_res);
sc->lf_bsh = rman_get_bushandle(sc->lf_mem_res);
rid = 0;
sc->lf_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_ACTIVE);
if (!sc->lf_irq_res) {
device_printf(dev, "cannot allocate interrupt\n");
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lf_mem_res);
return (ENXIO);
}
if (bus_setup_intr(dev, sc->lf_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
NULL, lpc_fb_intr, sc, &sc->lf_intrhand))
{
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lf_mem_res);
bus_release_resource(dev, SYS_RES_IRQ, 1, sc->lf_irq_res);
device_printf(dev, "cannot setup interrupt handler\n");
return (ENXIO);
}
node = ofw_bus_get_node(dev);
err = lpc_fb_read_lcd_config(node, &sc->lf_lcd_config);
if (err) {
device_printf(dev, "cannot read LCD configuration\n");
goto fail;
}
sc->lf_buffer_size = sc->lf_lcd_config.lc_xres *
sc->lf_lcd_config.lc_yres *
(sc->lf_lcd_config.lc_bpp == 24 ? 3 : 2);
device_printf(dev, "%dx%d LCD, %d bits per pixel, %dkHz pixel clock\n",
sc->lf_lcd_config.lc_xres, sc->lf_lcd_config.lc_yres,
sc->lf_lcd_config.lc_bpp, sc->lf_lcd_config.lc_pixelclock / 1000);
err = bus_dma_tag_create(
bus_get_dma_tag(sc->lf_dev),
4, 0, /* alignment, boundary */
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
sc->lf_buffer_size, 1, /* maxsize, nsegments */
sc->lf_buffer_size, 0, /* maxsegsize, flags */
NULL, NULL, /* lockfunc, lockarg */
&sc->lf_dma_tag);
err = bus_dmamem_alloc(sc->lf_dma_tag, (void **)&sc->lf_buffer,
0, &sc->lf_dma_map);
if (err) {
device_printf(dev, "cannot allocate framebuffer\n");
goto fail;
}
err = bus_dmamap_load(sc->lf_dma_tag, sc->lf_dma_map, sc->lf_buffer,
sc->lf_buffer_size, lpc_fb_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
if (err) {
device_printf(dev, "cannot load DMA map\n");
goto fail;
}
switch (sc->lf_lcd_config.lc_bpp) {
case 12:
mode = LPC_CLKPWR_LCDCLK_CTRL_MODE_12;
break;
case 15:
mode = LPC_CLKPWR_LCDCLK_CTRL_MODE_15;
break;
case 16:
mode = LPC_CLKPWR_LCDCLK_CTRL_MODE_16;
break;
case 24:
mode = LPC_CLKPWR_LCDCLK_CTRL_MODE_24;
break;
default:
panic("unsupported bpp");
}
lpc_pwr_write(sc->lf_dev, LPC_CLKPWR_LCDCLK_CTRL,
LPC_CLKPWR_LCDCLK_CTRL_MODE(mode) |
LPC_CLKPWR_LCDCLK_CTRL_HCLKEN);
sc->lf_buffer_phys = ctx.lf_dma_busaddr;
sc->lf_cdev = make_dev(&lpc_fb_cdevsw, 0, UID_ROOT, GID_WHEEL,
0600, "lpcfb");
sc->lf_cdev->si_drv1 = sc;
return (0);
fail:
return (ENXIO);
}
static int
hme_sbus_attach(device_t dev)
{
struct hme_sbus_softc *hsc;
struct hme_softc *sc;
u_long start, count;
uint32_t burst;
int i, error = 0;
hsc = device_get_softc(dev);
sc = &hsc->hsc_hme;
mtx_init(&sc->sc_lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF);
/*
* Map five register banks:
*
* bank 0: HME SEB registers
* bank 1: HME ETX registers
* bank 2: HME ERX registers
* bank 3: HME MAC registers
* bank 4: HME MIF registers
*
*/
i = 0;
hsc->hsc_seb_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&i, RF_ACTIVE);
if (hsc->hsc_seb_res == NULL) {
device_printf(dev, "cannot map SEB registers\n");
error = ENXIO;
goto fail_mtx_res;
}
sc->sc_sebt = rman_get_bustag(hsc->hsc_seb_res);
sc->sc_sebh = rman_get_bushandle(hsc->hsc_seb_res);
i = 1;
hsc->hsc_etx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&i, RF_ACTIVE);
if (hsc->hsc_etx_res == NULL) {
device_printf(dev, "cannot map ETX registers\n");
error = ENXIO;
goto fail_seb_res;
}
sc->sc_etxt = rman_get_bustag(hsc->hsc_etx_res);
sc->sc_etxh = rman_get_bushandle(hsc->hsc_etx_res);
i = 2;
hsc->hsc_erx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&i, RF_ACTIVE);
if (hsc->hsc_erx_res == NULL) {
device_printf(dev, "cannot map ERX registers\n");
error = ENXIO;
goto fail_etx_res;
}
sc->sc_erxt = rman_get_bustag(hsc->hsc_erx_res);
sc->sc_erxh = rman_get_bushandle(hsc->hsc_erx_res);
i = 3;
hsc->hsc_mac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&i, RF_ACTIVE);
if (hsc->hsc_mac_res == NULL) {
device_printf(dev, "cannot map MAC registers\n");
error = ENXIO;
goto fail_erx_res;
}
sc->sc_mact = rman_get_bustag(hsc->hsc_mac_res);
sc->sc_mach = rman_get_bushandle(hsc->hsc_mac_res);
/*
* At least on some HMEs, the MIF registers seem to be inside the MAC
* range, so try to kludge around it.
*/
i = 4;
hsc->hsc_mif_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&i, RF_ACTIVE);
if (hsc->hsc_mif_res == NULL) {
if (bus_get_resource(dev, SYS_RES_MEMORY, i,
&start, &count) != 0) {
device_printf(dev, "cannot get MIF registers\n");
error = ENXIO;
goto fail_mac_res;
}
if (start < rman_get_start(hsc->hsc_mac_res) ||
start + count - 1 > rman_get_end(hsc->hsc_mac_res)) {
device_printf(dev, "cannot move MIF registers to MAC "
"bank\n");
error = ENXIO;
goto fail_mac_res;
}
sc->sc_mift = sc->sc_mact;
bus_space_subregion(sc->sc_mact, sc->sc_mach,
start - rman_get_start(hsc->hsc_mac_res), count,
&sc->sc_mifh);
} else {
sc->sc_mift = rman_get_bustag(hsc->hsc_mif_res);
sc->sc_mifh = rman_get_bushandle(hsc->hsc_mif_res);
}
i = 0;
hsc->hsc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&i, RF_SHAREABLE | RF_ACTIVE);
if (hsc->hsc_ires == NULL) {
device_printf(dev, "could not allocate interrupt\n");
error = ENXIO;
goto fail_mif_res;
}
OF_getetheraddr(dev, sc->sc_enaddr);
burst = sbus_get_burstsz(dev);
/* Translate into plain numerical format */
if ((burst & SBUS_BURST_64))
sc->sc_burst = 64;
else if ((burst & SBUS_BURST_32))
sc->sc_burst = 32;
else if ((burst & SBUS_BURST_16))
sc->sc_burst = 16;
else
sc->sc_burst = 0;
sc->sc_dev = dev;
sc->sc_flags = 0;
if ((error = hme_config(sc)) != 0) {
device_printf(dev, "could not be configured\n");
goto fail_ires;
}
if ((error = bus_setup_intr(dev, hsc->hsc_ires, INTR_TYPE_NET |
INTR_MPSAFE, NULL, hme_intr, sc, &hsc->hsc_ih)) != 0) {
device_printf(dev, "couldn't establish interrupt\n");
hme_detach(sc);
goto fail_ires;
}
return (0);
fail_ires:
bus_release_resource(dev, SYS_RES_IRQ,
rman_get_rid(hsc->hsc_ires), hsc->hsc_ires);
fail_mif_res:
if (hsc->hsc_mif_res != NULL) {
bus_release_resource(dev, SYS_RES_MEMORY,
rman_get_rid(hsc->hsc_mif_res), hsc->hsc_mif_res);
}
fail_mac_res:
bus_release_resource(dev, SYS_RES_MEMORY,
rman_get_rid(hsc->hsc_mac_res), hsc->hsc_mac_res);
fail_erx_res:
bus_release_resource(dev, SYS_RES_MEMORY,
rman_get_rid(hsc->hsc_erx_res), hsc->hsc_erx_res);
fail_etx_res:
bus_release_resource(dev, SYS_RES_MEMORY,
rman_get_rid(hsc->hsc_etx_res), hsc->hsc_etx_res);
fail_seb_res:
bus_release_resource(dev, SYS_RES_MEMORY,
rman_get_rid(hsc->hsc_seb_res), hsc->hsc_seb_res);
fail_mtx_res:
mtx_destroy(&sc->sc_lock);
return (error);
}
static int
sbni_attach_isa(device_t dev)
{
struct sbni_softc *sc;
struct sbni_flags flags;
int error;
sc = device_get_softc(dev);
sc->dev = dev;
sc->irq_res = bus_alloc_resource_any(
dev, SYS_RES_IRQ, &sc->irq_rid, RF_ACTIVE);
#ifndef SBNI_DUAL_COMPOUND
if (sc->irq_res == NULL) {
device_printf(dev, "irq conflict!\n");
sbni_release_resources(sc);
return (ENOENT);
}
#else /* SBNI_DUAL_COMPOUND */
if (sc->irq_res) {
sbni_add(sc);
} else {
struct sbni_softc *master;
if ((master = connect_to_master(sc)) == 0) {
device_printf(dev, "failed to alloc irq\n");
sbni_release_resources(sc);
return (ENXIO);
} else {
device_printf(dev, "shared irq with %s\n",
master->ifp->if_xname);
}
}
#endif /* SBNI_DUAL_COMPOUND */
*(u_int32_t*)&flags = device_get_flags(dev);
error = sbni_attach(sc, device_get_unit(dev) * 2, flags);
if (error) {
device_printf(dev, "cannot initialize driver\n");
sbni_release_resources(sc);
return (error);
}
if (sc->irq_res) {
error = bus_setup_intr(
dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE,
NULL, sbni_intr, sc, &sc->irq_handle);
if (error) {
device_printf(dev, "bus_setup_intr\n");
sbni_detach(sc);
sbni_release_resources(sc);
return (error);
}
}
return (0);
}
static int
imx_gpt_attach(device_t dev)
{
struct imx_gpt_softc *sc;
int err;
sc = device_get_softc(dev);
if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
sc->sc_dev = dev;
sc->sc_clksrc = GPT_CR_CLKSRC_IPG;
sc->sc_iot = rman_get_bustag(sc->res[0]);
sc->sc_ioh = rman_get_bushandle(sc->res[0]);
switch (sc->sc_clksrc) {
case GPT_CR_CLKSRC_NONE:
device_printf(dev, "can't run timer without clock source\n");
return (EINVAL);
case GPT_CR_CLKSRC_EXT:
device_printf(dev, "Not implemented. Geve me the way to get "
"external clock source frequency\n");
return (EINVAL);
case GPT_CR_CLKSRC_32K:
sc->clkfreq = 32768;
break;
case GPT_CR_CLKSRC_IPG_HIGH:
sc->clkfreq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT) * 2;
break;
default:
sc->clkfreq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT);
}
device_printf(dev, "Run on %dKHz clock.\n", sc->clkfreq / 1000);
/* Reset */
WRITE4(sc, IMX_GPT_CR, GPT_CR_SWR);
/* Enable and setup counters */
WRITE4(sc, IMX_GPT_CR,
GPT_CR_CLKSRC_IPG | /* Use IPG clock */
GPT_CR_FRR | /* Just count (FreeRunner mode) */
GPT_CR_STOPEN | /* Run in STOP mode */
GPT_CR_WAITEN | /* Run in WAIT mode */
GPT_CR_DBGEN); /* Run in DEBUG mode */
/* Disable interrupts */
WRITE4(sc, IMX_GPT_IR, 0);
/* Tick every 10us */
/* XXX: must be calculated from clock source frequency */
WRITE4(sc, IMX_GPT_PR, 665);
/* Use 100 KHz */
sc->clkfreq = 100000;
/* Setup and enable the timer interrupt */
err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr,
NULL, sc, &sc->sc_ih);
if (err != 0) {
bus_release_resources(dev, imx_gpt_spec, sc->res);
device_printf(dev, "Unable to setup the clock irq handler, "
"err = %d\n", err);
return (ENXIO);
}
sc->et.et_name = "i.MXxxx GPT Eventtimer";
sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
sc->et.et_quality = 1000;
sc->et.et_frequency = sc->clkfreq;
sc->et.et_min_period = (MIN_PERIOD << 32) / sc->et.et_frequency;
sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
sc->et.et_start = imx_gpt_timer_start;
sc->et.et_stop = imx_gpt_timer_stop;
sc->et.et_priv = sc;
et_register(&sc->et);
/* Disable interrupts */
WRITE4(sc, IMX_GPT_IR, 0);
/* ACK any panding interrupts */
WRITE4(sc, IMX_GPT_SR, (GPT_IR_ROV << 1) - 1);
if (device_get_unit(dev) == 0)
imx_gpt_sc = sc;
imx_gpt_timecounter.tc_frequency = sc->clkfreq;
tc_init(&imx_gpt_timecounter);
printf("clock: hz=%d stathz = %d\n", hz, stathz);
device_printf(sc->sc_dev, "timer clock frequency %d\n", sc->clkfreq);
imx_gpt_delay_count = imx51_get_clock(IMX51CLK_ARM_ROOT) / 4000000;
SET4(sc, IMX_GPT_CR, GPT_CR_EN);
return (0);
}
static int
mecia_attach(device_t dev)
{
int error;
int irq;
void *ih;
device_t kid;
struct resource *r;
int rid;
struct slot *slt;
struct mecia_slot *sp;
sp = MECIA_DEVICE2SOFTC(dev);
sp->unit = validunits++;
kid = device_add_child(dev, NULL, -1);
if (kid == NULL) {
device_printf(dev, "Can't add pccard bus slot 0\n");
return (ENXIO);
}
device_probe_and_attach(kid);
slt = pccard_init_slot(kid, &mecia_cinfo);
if (slt == 0) {
device_printf(dev, "Can't get pccard info slot 0\n");
return (ENXIO);
}
slt->cdata = sp;
sp->slt = slt;
validunits++;
rid = 0;
r = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1, RF_ACTIVE);
if (!r)
return (ENXIO);
irq = bus_get_resource_start(dev, SYS_RES_IRQ, 0);
if (irq == 0) {
/* See if the user has requested a specific IRQ */
if (!getenv_int("machdep.pccard.mecia_irq", &irq))
irq = 0;
}
rid = 0;
r = 0;
if (irq > 0) {
r = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, irq,
irq, 1, RF_ACTIVE);
}
if (r && ((1 << (rman_get_start(r))) & MECIA_INT_MASK_ALLOWED) == 0) {
device_printf(dev,
"Hardware does not support irq %d, trying polling.\n",
irq);
bus_release_resource(dev, SYS_RES_IRQ, rid, r);
r = 0;
irq = 0;
}
if (r) {
error = bus_setup_intr(dev, r, INTR_TYPE_MISC,
meciaintr, (void *) sp, &ih);
if (error) {
bus_release_resource(dev, SYS_RES_IRQ, rid, r);
return (error);
}
irq = rman_get_start(r);
device_printf(dev, "management irq %d\n", irq);
} else {
irq = 0;
}
if (irq == 0) {
meciatimeout_ch = timeout(meciatimeout, (void *) sp, hz/2);
device_printf(dev, "Polling mode\n");
}
sp->last_reg1 = inb(MECIA_REG1);
if (sp->last_reg1 & MECIA_CARDEXIST) {
/* PCMCIA card exist */
sp->slt->laststate = sp->slt->state = filled;
pccard_event(sp->slt, card_inserted);
} else {
sp->slt->laststate = sp->slt->state = empty;
}
sp->slt->irq = irq;
return (bus_generic_attach(dev));
}
int
ata_attach(device_t dev)
{
struct ata_channel *ch = device_get_softc(dev);
int error, rid;
struct cam_devq *devq;
const char *res;
char buf[64];
int i, mode;
/* check that we have a virgin channel to attach */
if (ch->r_irq)
return EEXIST;
/* initialize the softc basics */
ch->dev = dev;
ch->state = ATA_IDLE;
bzero(&ch->state_mtx, sizeof(struct mtx));
mtx_init(&ch->state_mtx, "ATA state lock", NULL, MTX_DEF);
TASK_INIT(&ch->conntask, 0, ata_conn_event, dev);
for (i = 0; i < 16; i++) {
ch->user[i].revision = 0;
snprintf(buf, sizeof(buf), "dev%d.sata_rev", i);
if (resource_int_value(device_get_name(dev),
device_get_unit(dev), buf, &mode) != 0 &&
resource_int_value(device_get_name(dev),
device_get_unit(dev), "sata_rev", &mode) != 0)
mode = -1;
if (mode >= 0)
ch->user[i].revision = mode;
ch->user[i].mode = 0;
snprintf(buf, sizeof(buf), "dev%d.mode", i);
if (resource_string_value(device_get_name(dev),
device_get_unit(dev), buf, &res) == 0)
mode = ata_str2mode(res);
else if (resource_string_value(device_get_name(dev),
device_get_unit(dev), "mode", &res) == 0)
mode = ata_str2mode(res);
else
mode = -1;
if (mode >= 0)
ch->user[i].mode = mode;
if (ch->flags & ATA_SATA)
ch->user[i].bytecount = 8192;
else
ch->user[i].bytecount = MAXPHYS;
ch->user[i].caps = 0;
ch->curr[i] = ch->user[i];
if (ch->flags & ATA_SATA) {
if (ch->pm_level > 0)
ch->user[i].caps |= CTS_SATA_CAPS_H_PMREQ;
if (ch->pm_level > 1)
ch->user[i].caps |= CTS_SATA_CAPS_D_PMREQ;
} else {
if (!(ch->flags & ATA_NO_48BIT_DMA))
ch->user[i].caps |= CTS_ATA_CAPS_H_DMA48;
}
}
callout_init(&ch->poll_callout, 1);
/* allocate DMA resources if DMA HW present*/
if (ch->dma.alloc)
ch->dma.alloc(dev);
/* setup interrupt delivery */
rid = ATA_IRQ_RID;
ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (!ch->r_irq) {
device_printf(dev, "unable to allocate interrupt\n");
return ENXIO;
}
if ((error = bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
ata_interrupt, ch, &ch->ih))) {
bus_release_resource(dev, SYS_RES_IRQ, rid, ch->r_irq);
device_printf(dev, "unable to setup interrupt\n");
return error;
}
if (ch->flags & ATA_PERIODIC_POLL)
callout_reset(&ch->poll_callout, hz, ata_periodic_poll, ch);
mtx_lock(&ch->state_mtx);
/* Create the device queue for our SIM. */
devq = cam_simq_alloc(1);
if (devq == NULL) {
device_printf(dev, "Unable to allocate simq\n");
error = ENOMEM;
goto err1;
}
/* Construct SIM entry */
ch->sim = cam_sim_alloc(ataaction, atapoll, "ata", ch,
device_get_unit(dev), &ch->state_mtx, 1, 0, devq);
if (ch->sim == NULL) {
device_printf(dev, "unable to allocate sim\n");
cam_simq_free(devq);
error = ENOMEM;
goto err1;
}
if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
device_printf(dev, "unable to register xpt bus\n");
error = ENXIO;
goto err2;
}
if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
device_printf(dev, "unable to create path\n");
error = ENXIO;
goto err3;
}
mtx_unlock(&ch->state_mtx);
return (0);
err3:
xpt_bus_deregister(cam_sim_path(ch->sim));
err2:
cam_sim_free(ch->sim, /*free_devq*/TRUE);
ch->sim = NULL;
err1:
bus_release_resource(dev, SYS_RES_IRQ, rid, ch->r_irq);
mtx_unlock(&ch->state_mtx);
if (ch->flags & ATA_PERIODIC_POLL)
callout_drain(&ch->poll_callout);
return (error);
}
static int
ohci_pci_attach(device_t self)
{
ohci_softc_t *sc = device_get_softc(self);
int err;
int rid;
/* XXX where does it say so in the spec? */
sc->sc_bus.usbrev = USBREV_1_0;
pci_enable_busmaster(self);
/*
* Some Sun PCIO-2 USB controllers have their intpin register
* bogusly set to 0, although it should be 4. Correct that.
*/
if (pci_get_devid(self) == PCI_OHCI_DEVICEID_PCIO2USB &&
pci_get_intpin(self) == 0)
pci_set_intpin(self, 4);
rid = PCI_CBMEM;
sc->io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->io_res) {
device_printf(self, "Could not map memory\n");
return ENXIO;
}
sc->iot = rman_get_bustag(sc->io_res);
sc->ioh = rman_get_bushandle(sc->io_res);
rid = 0;
sc->irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->irq_res == NULL) {
device_printf(self, "Could not allocate irq\n");
ohci_pci_detach(self);
return ENXIO;
}
sc->sc_bus.bdev = device_add_child(self, "usb", -1);
if (!sc->sc_bus.bdev) {
device_printf(self, "Could not add USB device\n");
ohci_pci_detach(self);
return ENOMEM;
}
device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
/* ohci_pci_match will never return NULL if ohci_pci_probe succeeded */
device_set_desc(sc->sc_bus.bdev, ohci_pci_match(self));
switch (pci_get_vendor(self)) {
case PCI_OHCI_VENDORID_ACERLABS:
ksprintf(sc->sc_vendor, "AcerLabs");
break;
case PCI_OHCI_VENDORID_AMD:
ksprintf(sc->sc_vendor, "AMD");
break;
case PCI_OHCI_VENDORID_APPLE:
ksprintf(sc->sc_vendor, "Apple");
break;
case PCI_OHCI_VENDORID_ATI:
ksprintf(sc->sc_vendor, "ATI");
break;
case PCI_OHCI_VENDORID_CMDTECH:
ksprintf(sc->sc_vendor, "CMDTECH");
break;
case PCI_OHCI_VENDORID_NEC:
ksprintf(sc->sc_vendor, "NEC");
break;
case PCI_OHCI_VENDORID_NVIDIA:
case PCI_OHCI_VENDORID_NVIDIA2:
ksprintf(sc->sc_vendor, "nVidia");
break;
case PCI_OHCI_VENDORID_OPTI:
ksprintf(sc->sc_vendor, "OPTi");
break;
case PCI_OHCI_VENDORID_SIS:
ksprintf(sc->sc_vendor, "SiS");
break;
default:
if (bootverbose)
device_printf(self, "(New OHCI DeviceId=0x%08x)\n",
pci_get_devid(self));
ksprintf(sc->sc_vendor, "(0x%04x)", pci_get_vendor(self));
}
err = bus_setup_intr(self, sc->irq_res, 0,
(driver_intr_t *) ohci_intr, sc, &sc->ih, NULL);
if (err) {
device_printf(self, "Could not setup irq, %d\n", err);
sc->ih = NULL;
ohci_pci_detach(self);
return ENXIO;
}
/*
* OHCI interrupts which occur early will leave them disabled,
* so run the interrupt manually once we're done with the init.
*/
err = ohci_init(sc);
if (err == 0)
err = device_probe_and_attach(sc->sc_bus.bdev);
if (err) {
device_printf(self, "USB init failed\n");
ohci_pci_detach(self);
return EIO;
}
return 0;
}
/**
* Configure common hardware for all interfaces
*/
static void cvm_oct_configure_common_hw(device_t bus)
{
struct octebus_softc *sc;
int pko_queues;
int error;
int rid;
sc = device_get_softc(bus);
/* Setup the FPA */
cvmx_fpa_enable();
cvm_oct_mem_fill_fpa(CVMX_FPA_PACKET_POOL, CVMX_FPA_PACKET_POOL_SIZE,
num_packet_buffers);
cvm_oct_mem_fill_fpa(CVMX_FPA_WQE_POOL, CVMX_FPA_WQE_POOL_SIZE,
num_packet_buffers);
if (CVMX_FPA_OUTPUT_BUFFER_POOL != CVMX_FPA_PACKET_POOL) {
/*
* If the FPA uses different pools for output buffers and
* packets, size the output buffer pool based on the number
* of PKO queues.
*/
if (OCTEON_IS_MODEL(OCTEON_CN38XX))
pko_queues = 128;
else if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
pko_queues = 32;
else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
pko_queues = 32;
else
pko_queues = 256;
cvm_oct_num_output_buffers = 4 * pko_queues;
cvm_oct_mem_fill_fpa(CVMX_FPA_OUTPUT_BUFFER_POOL,
CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE,
cvm_oct_num_output_buffers);
}
if (USE_RED)
cvmx_helper_setup_red(num_packet_buffers/4,
num_packet_buffers/8);
/* Enable the MII interface */
if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)
cvmx_write_csr(CVMX_SMI_EN, 1);
/* Register an IRQ hander for to receive POW interrupts */
rid = 0;
sc->sc_rx_irq = bus_alloc_resource(bus, SYS_RES_IRQ, &rid,
OCTEON_IRQ_WORKQ0 + pow_receive_group,
OCTEON_IRQ_WORKQ0 + pow_receive_group,
1, RF_ACTIVE);
if (sc->sc_rx_irq == NULL) {
device_printf(bus, "could not allocate workq irq");
return;
}
error = bus_setup_intr(bus, sc->sc_rx_irq, INTR_TYPE_NET | INTR_MPSAFE,
cvm_oct_do_interrupt, NULL, cvm_oct_device,
&sc->sc_rx_intr_cookie);
if (error != 0) {
device_printf(bus, "could not setup workq irq");
return;
}
#ifdef SMP
{
cvmx_ciu_intx0_t en;
int core;
CPU_FOREACH(core) {
if (core == PCPU_GET(cpuid))
continue;
en.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(core*2));
en.s.workq |= (1<<pow_receive_group);
cvmx_write_csr(CVMX_CIU_INTX_EN0(core*2), en.u64);
}
}
#endif
}
static int
ichsmb_pci_attach(device_t dev)
{
const sc_p sc = device_get_softc(dev);
u_int32_t cmd;
int error;
/* Initialize private state */
bzero(sc, sizeof(*sc));
sc->ich_cmd = -1;
sc->dev = dev;
/* Allocate an I/O range */
sc->io_rid = ICH_SMB_BASE;
sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT,
&sc->io_rid, 0, ~0, 16, RF_ACTIVE);
if (sc->io_res == NULL) {
log(LOG_ERR, "%s: can't map I/O\n", device_get_nameunit(dev));
error = ENXIO;
goto fail;
}
sc->io_bst = rman_get_bustag(sc->io_res);
sc->io_bsh = rman_get_bushandle(sc->io_res);
/* Allocate interrupt */
sc->irq_rid = 0;
sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ,
&sc->irq_rid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
if (sc->irq_res == NULL) {
log(LOG_ERR, "%s: can't get IRQ\n", device_get_nameunit(dev));
error = ENXIO;
goto fail;
}
/* Set up interrupt handler */
error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC,
ichsmb_device_intr, sc, &sc->irq_handle);
if (error != 0) {
log(LOG_ERR, "%s: can't setup irq\n", device_get_nameunit(dev));
goto fail;
}
/* Enable I/O mapping */
cmd = pci_read_config(dev, PCIR_COMMAND, 4);
cmd |= PCIM_CMD_PORTEN;
pci_write_config(dev, PCIR_COMMAND, cmd, 4);
cmd = pci_read_config(dev, PCIR_COMMAND, 4);
if ((cmd & PCIM_CMD_PORTEN) == 0) {
log(LOG_ERR, "%s: can't enable memory map\n",
device_get_nameunit(dev));
error = ENXIO;
goto fail;
}
/* Enable device */
pci_write_config(dev, ICH_HOSTC, ICH_HOSTC_HST_EN, 1);
/* Done */
return (ichsmb_attach(dev));
fail:
/* Attach failed, release resources */
ichsmb_release_resources(sc);
return (error);
}
static int
le_pci_attach(device_t dev)
{
struct le_pci_softc *lesc;
struct lance_softc *sc;
int error, i;
lesc = device_get_softc(dev);
sc = &lesc->sc_am79900.lsc;
pci_enable_busmaster(dev);
pci_enable_io(dev, PCIM_CMD_PORTEN);
lesc->sc_rrid = PCIR_BAR(0);
lesc->sc_rres = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
&lesc->sc_rrid, RF_ACTIVE);
if (lesc->sc_rres == NULL) {
device_printf(dev, "cannot allocate registers\n");
error = ENXIO;
goto fail_mtx;
}
lesc->sc_regt = rman_get_bustag(lesc->sc_rres);
lesc->sc_regh = rman_get_bushandle(lesc->sc_rres);
lesc->sc_irid = 0;
if ((lesc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&lesc->sc_irid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
device_printf(dev, "cannot allocate interrupt\n");
error = ENXIO;
goto fail_rres;
}
error = bus_dma_tag_create(
NULL, /* parent */
1, 0, /* alignment, boundary */
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
0, /* nsegments */
BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
BUS_DMA_WAITOK, /* flags */
&lesc->sc_pdmat);
if (error != 0) {
device_printf(dev, "cannot allocate parent DMA tag\n");
goto fail_ires;
}
sc->sc_memsize = PCNET_MEMSIZE;
/*
* For Am79C970A, Am79C971 and Am79C978 the init block must be 2-byte
* aligned and the ring descriptors must be 16-byte aligned when using
* a 32-bit software style.
*/
error = bus_dma_tag_create(
lesc->sc_pdmat, /* parent */
16, 0, /* alignment, boundary */
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
sc->sc_memsize, /* maxsize */
1, /* nsegments */
sc->sc_memsize, /* maxsegsize */
BUS_DMA_WAITOK, /* flags */
&lesc->sc_dmat);
if (error != 0) {
device_printf(dev, "cannot allocate buffer DMA tag\n");
goto fail_pdtag;
}
error = bus_dmamem_alloc(lesc->sc_dmat, (void **)&sc->sc_mem,
BUS_DMA_WAITOK | BUS_DMA_COHERENT, &lesc->sc_dmam);
if (error != 0) {
device_printf(dev, "cannot allocate DMA buffer memory\n");
goto fail_dtag;
}
sc->sc_addr = 0;
error = bus_dmamap_load(lesc->sc_dmat, lesc->sc_dmam, sc->sc_mem,
sc->sc_memsize, le_pci_dma_callback, sc, 0);
if (error != 0 || sc->sc_addr == 0) {
device_printf(dev, "cannot load DMA buffer map\n");
goto fail_dmem;
}
sc->sc_flags = LE_BSWAP;
sc->sc_conf3 = 0;
sc->sc_mediastatus = NULL;
switch (pci_get_device(dev)) {
case AMD_PCNET_HOME:
sc->sc_mediachange = le_pci_mediachange;
sc->sc_supmedia = le_home_supmedia;
sc->sc_nsupmedia = sizeof(le_home_supmedia) / sizeof(int);
sc->sc_defaultmedia = le_home_supmedia[0];
break;
default:
sc->sc_mediachange = le_pci_mediachange;
sc->sc_supmedia = le_pci_supmedia;
sc->sc_nsupmedia = sizeof(le_pci_supmedia) / sizeof(int);
sc->sc_defaultmedia = le_pci_supmedia[0];
}
/*
* Extract the physical MAC address from the ROM.
*/
for (i = 0; i < sizeof(sc->sc_enaddr); i++)
sc->sc_enaddr[i] =
bus_space_read_1(lesc->sc_regt, lesc->sc_regh, i);
sc->sc_copytodesc = lance_copytobuf_contig;
sc->sc_copyfromdesc = lance_copyfrombuf_contig;
sc->sc_copytobuf = lance_copytobuf_contig;
sc->sc_copyfrombuf = lance_copyfrombuf_contig;
sc->sc_zerobuf = lance_zerobuf_contig;
sc->sc_rdcsr = le_pci_rdcsr;
sc->sc_wrcsr = le_pci_wrcsr;
sc->sc_hwreset = le_pci_hwreset;
sc->sc_hwinit = NULL;
sc->sc_hwintr = NULL;
sc->sc_nocarrier = NULL;
error = am79900_config(&lesc->sc_am79900, device_get_name(dev),
device_get_unit(dev));
if (error != 0) {
device_printf(dev, "cannot attach Am79900\n");
goto fail_dmap;
}
error = bus_setup_intr(dev, lesc->sc_ires, INTR_MPSAFE,
am79900_intr, sc, &lesc->sc_ih, sc->ifp->if_serializer);
if (error != 0) {
device_printf(dev, "cannot set up interrupt\n");
goto fail_am79900;
}
sc->ifp->if_cpuid = rman_get_cpuid(lesc->sc_ires);
KKASSERT(sc->ifp->if_cpuid >= 0 && sc->ifp->if_cpuid < ncpus);
return (0);
fail_am79900:
am79900_detach(&lesc->sc_am79900);
fail_dmap:
bus_dmamap_unload(lesc->sc_dmat, lesc->sc_dmam);
fail_dmem:
bus_dmamem_free(lesc->sc_dmat, sc->sc_mem, lesc->sc_dmam);
fail_dtag:
bus_dma_tag_destroy(lesc->sc_dmat);
fail_pdtag:
bus_dma_tag_destroy(lesc->sc_pdmat);
fail_ires:
bus_release_resource(dev, SYS_RES_IRQ, lesc->sc_irid, lesc->sc_ires);
fail_rres:
bus_release_resource(dev, SYS_RES_IOPORT, lesc->sc_rrid, lesc->sc_rres);
fail_mtx:
return (error);
}
int
altera_jtag_uart_attach(struct altera_jtag_uart_softc *sc)
{
struct tty *tp;
int error;
AJU_LOCK_INIT(sc);
/*
* XXXRW: Currently, we detect the console solely based on it using a
* reserved address, and borrow console-level locks and buffer if so.
* Is there a better way?
*/
if (rman_get_start(sc->ajus_mem_res) == BERI_UART_BASE) {
sc->ajus_lockp = &aju_cons_lock;
sc->ajus_buffer_validp = &aju_cons_buffer_valid;
sc->ajus_buffer_datap = &aju_cons_buffer_data;
sc->ajus_jtag_presentp = &aju_cons_jtag_present;
sc->ajus_jtag_missedp = &aju_cons_jtag_missed;
sc->ajus_flags |= ALTERA_JTAG_UART_FLAG_CONSOLE;
} else {
sc->ajus_lockp = &sc->ajus_lock;
sc->ajus_buffer_validp = &sc->ajus_buffer_valid;
sc->ajus_buffer_datap = &sc->ajus_buffer_data;
sc->ajus_jtag_presentp = &sc->ajus_jtag_present;
sc->ajus_jtag_missedp = &sc->ajus_jtag_missed;
}
/*
* Disable interrupts regardless of whether or not we plan to use
* them. We will register an interrupt handler now if they will be
* used, but not re-enable intil later once the remainder of the tty
* layer is properly initialised, as we're not ready for input yet.
*/
AJU_LOCK(sc);
aju_intr_disable(sc);
AJU_UNLOCK(sc);
if (sc->ajus_irq_res != NULL) {
error = bus_setup_intr(sc->ajus_dev, sc->ajus_irq_res,
INTR_ENTROPY | INTR_TYPE_TTY | INTR_MPSAFE, NULL,
aju_intr, sc, &sc->ajus_irq_cookie);
if (error) {
device_printf(sc->ajus_dev,
"could not activate interrupt\n");
AJU_LOCK_DESTROY(sc);
return (error);
}
}
tp = sc->ajus_ttyp = tty_alloc(&aju_ttydevsw, sc);
if (sc->ajus_flags & ALTERA_JTAG_UART_FLAG_CONSOLE) {
aju_cons_sc = sc;
tty_init_console(tp, 0);
}
tty_makedev(tp, NULL, "%s%d", AJU_TTYNAME, sc->ajus_unit);
/*
* If we will be using interrupts, enable them now; otherwise, start
* polling. From this point onwards, input can arrive.
*/
if (sc->ajus_irq_res != NULL) {
AJU_LOCK(sc);
aju_intr_readable_enable(sc);
AJU_UNLOCK(sc);
} else {
callout_init(&sc->ajus_io_callout, 1);
callout_reset(&sc->ajus_io_callout, AJU_IO_POLLINTERVAL,
aju_io_callout, sc);
}
callout_init(&sc->ajus_ac_callout, 1);
callout_reset(&sc->ajus_ac_callout, AJU_AC_POLLINTERVAL,
aju_ac_callout, sc);
return (0);
}
static int
tegra_xhci_attach(device_t dev)
{
struct tegra_xhci_softc *sc;
struct xhci_softc *xsc;
int rv, rid;
phandle_t node;
sc = device_get_softc(dev);
sc->dev = dev;
sc->fw_name = "tegra124_xusb_fw";
node = ofw_bus_get_node(dev);
xsc = &sc->xhci_softc;
LOCK_INIT(sc);
rv = get_fdt_resources(sc, node);
if (rv != 0) {
rv = ENXIO;
goto error;
}
rv = enable_fdt_resources(sc);
if (rv != 0) {
rv = ENXIO;
goto error;
}
/* Allocate resources. */
rid = 0;
xsc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (xsc->sc_io_res == NULL) {
device_printf(dev,
"Could not allocate HCD memory resources\n");
rv = ENXIO;
goto error;
}
rid = 1;
sc->mem_res_fpci = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (sc->mem_res_fpci == NULL) {
device_printf(dev,
"Could not allocate FPCI memory resources\n");
rv = ENXIO;
goto error;
}
rid = 2;
sc->mem_res_ipfs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (sc->mem_res_ipfs == NULL) {
device_printf(dev,
"Could not allocate IPFS memory resources\n");
rv = ENXIO;
goto error;
}
rid = 0;
xsc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_ACTIVE);
if (xsc->sc_irq_res == NULL) {
device_printf(dev, "Could not allocate HCD IRQ resources\n");
rv = ENXIO;
goto error;
}
rid = 1;
sc->irq_res_mbox = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_ACTIVE);
if (sc->irq_res_mbox == NULL) {
device_printf(dev, "Could not allocate MBOX IRQ resources\n");
rv = ENXIO;
goto error;
}
rv = init_hw(sc);
if (rv != 0) {
device_printf(dev, "Could not initialize XUSB hardware\n");
goto error;
}
/* Wakeup and enable firmaware */
rv = mbox_send_cmd(sc, MBOX_CMD_MSG_ENABLED, 0);
if (rv != 0) {
device_printf(sc->dev, "Could not enable XUSB firmware\n");
goto error;
}
/* Fill data for XHCI driver. */
xsc->sc_bus.parent = dev;
xsc->sc_bus.devices = xsc->sc_devices;
xsc->sc_bus.devices_max = XHCI_MAX_DEVICES;
xsc->sc_io_tag = rman_get_bustag(xsc->sc_io_res);
xsc->sc_io_hdl = rman_get_bushandle(xsc->sc_io_res);
xsc->sc_io_size = rman_get_size(xsc->sc_io_res);
strlcpy(xsc->sc_vendor, "Nvidia", sizeof(xsc->sc_vendor));
/* Add USB bus device. */
xsc->sc_bus.bdev = device_add_child(sc->dev, "usbus", -1);
if (xsc->sc_bus.bdev == NULL) {
device_printf(sc->dev, "Could not add USB device\n");
rv = ENXIO;
goto error;
}
device_set_ivars(xsc->sc_bus.bdev, &xsc->sc_bus);
device_set_desc(xsc->sc_bus.bdev, "Nvidia USB 3.0 controller");
rv = xhci_init(xsc, sc->dev, 1);
if (rv != 0) {
device_printf(sc->dev, "USB init failed: %d\n", rv);
goto error;
}
sc->xhci_inited = true;
rv = xhci_start_controller(xsc);
if (rv != 0) {
device_printf(sc->dev,
"Could not start XHCI controller: %d\n", rv);
goto error;
}
rv = bus_setup_intr(dev, sc->irq_res_mbox, INTR_TYPE_MISC | INTR_MPSAFE,
NULL, intr_mbox, sc, &sc->irq_hdl_mbox);
if (rv != 0) {
device_printf(dev, "Could not setup error IRQ: %d\n",rv);
xsc->sc_intr_hdl = NULL;
goto error;
}
rv = bus_setup_intr(dev, xsc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
NULL, (driver_intr_t *)xhci_interrupt, xsc, &xsc->sc_intr_hdl);
if (rv != 0) {
device_printf(dev, "Could not setup error IRQ: %d\n",rv);
xsc->sc_intr_hdl = NULL;
goto error;
}
/* Probe the bus. */
rv = device_probe_and_attach(xsc->sc_bus.bdev);
if (rv != 0) {
device_printf(sc->dev, "Could not initialize USB: %d\n", rv);
goto error;
}
return (0);
error:
panic("XXXXX");
tegra_xhci_detach(dev);
return (rv);
}
static int
cbb_pci_attach(device_t brdev)
{
#if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */
uint32_t pribus;
#endif
struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev);
struct sysctl_ctx_list *sctx;
struct sysctl_oid *soid;
int rid;
device_t parent;
parent = device_get_parent(brdev);
mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF);
sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL);
sc->dev = brdev;
sc->cbdev = NULL;
sc->exca[0].pccarddev = NULL;
sc->domain = pci_get_domain(brdev);
sc->pribus = pcib_get_bus(parent);
#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1);
pcib_setup_secbus(brdev, &sc->bus, 1);
#else
sc->bus.sec = pci_read_config(brdev, PCIR_SECBUS_2, 1);
sc->bus.sub = pci_read_config(brdev, PCIR_SUBBUS_2, 1);
#endif
SLIST_INIT(&sc->rl);
rid = CBBR_SOCKBASE;
sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->base_res) {
device_printf(brdev, "Could not map register memory\n");
mtx_destroy(&sc->mtx);
return (ENOMEM);
} else {
DEVPRINTF((brdev, "Found memory at %08lx\n",
rman_get_start(sc->base_res)));
}
sc->bst = rman_get_bustag(sc->base_res);
sc->bsh = rman_get_bushandle(sc->base_res);
exca_init(&sc->exca[0], brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET);
sc->exca[0].flags |= EXCA_HAS_MEMREG_WIN;
sc->exca[0].chipset = EXCA_CARDBUS;
sc->chipinit = cbb_chipinit;
sc->chipinit(sc);
/*Sysctls*/
sctx = device_get_sysctl_ctx(brdev);
soid = device_get_sysctl_tree(brdev);
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
CTLFLAG_RD, &sc->domain, 0, "Domain number");
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number");
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number");
#if 0
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "memory",
CTLFLAG_RD, &sc->subbus, 0, "Memory window open");
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "premem",
CTLFLAG_RD, &sc->subbus, 0, "Prefetch memroy window open");
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io1",
CTLFLAG_RD, &sc->subbus, 0, "io range 1 open");
SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io2",
CTLFLAG_RD, &sc->subbus, 0, "io range 2 open");
#endif
#if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
/*
* This is a gross hack. We should be scanning the entire pci
* tree, assigning bus numbers in a way such that we (1) can
* reserve 1 extra bus just in case and (2) all sub busses
* are in an appropriate range.
*/
DEVPRINTF((brdev, "Secondary bus is %d\n", sc->bus.sec));
pribus = pci_read_config(brdev, PCIR_PRIBUS_2, 1);
if (sc->bus.sec == 0 || sc->pribus != pribus) {
if (curr_bus_number <= sc->pribus)
curr_bus_number = sc->pribus + 1;
if (pribus != sc->pribus) {
DEVPRINTF((brdev, "Setting primary bus to %d\n",
sc->pribus));
pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1);
}
sc->bus.sec = curr_bus_number++;
sc->bus.sub = curr_bus_number++;
DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n",
sc->bus.sec, sc->bus.sub));
pci_write_config(brdev, PCIR_SECBUS_2, sc->bus.sec, 1);
pci_write_config(brdev, PCIR_SUBBUS_2, sc->bus.sub, 1);
}
#endif
/* attach children */
sc->cbdev = device_add_child(brdev, "cardbus", -1);
if (sc->cbdev == NULL)
DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n"));
else if (device_probe_and_attach(sc->cbdev) != 0)
DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n"));
sc->exca[0].pccarddev = device_add_child(brdev, "pccard", -1);
if (sc->exca[0].pccarddev == NULL)
DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n"));
else if (device_probe_and_attach(sc->exca[0].pccarddev) != 0)
DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n"));
/* Map and establish the interrupt. */
rid = 0;
sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->irq_res == NULL) {
device_printf(brdev, "Unable to map IRQ...\n");
goto err;
}
if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE,
cbb_pci_filt, NULL, sc, &sc->intrhand)) {
device_printf(brdev, "couldn't establish interrupt\n");
goto err;
}
/* reset 16-bit pcmcia bus */
exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET);
/* turn off power */
cbb_power(brdev, CARD_OFF);
/* CSC Interrupt: Card detect interrupt on */
cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD);
/* reset interrupt */
cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT));
if (bootverbose)
cbb_print_config(brdev);
/* Start the thread */
if (kproc_create(cbb_event_thread, sc, &sc->event_thread, 0, 0,
"%s event thread", device_get_nameunit(brdev))) {
device_printf(brdev, "unable to create event thread.\n");
panic("cbb_create_event_thread");
}
sc->sc_root_token = root_mount_hold(device_get_nameunit(sc->dev));
return (0);
err:
if (sc->irq_res)
bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res);
if (sc->base_res) {
bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE,
sc->base_res);
}
mtx_destroy(&sc->mtx);
return (ENOMEM);
}
static int
intsmb_attach(device_t dev)
{
struct intsmb_softc *sc = device_get_softc(dev);
int error, rid, value;
int intr;
char *str;
sc->dev = dev;
mtx_init(&sc->lock, device_get_nameunit(dev), "intsmb", MTX_DEF);
sc->cfg_irq9 = 0;
switch (pci_get_devid(dev)) {
#ifndef NO_CHANGE_PCICONF
case 0x71138086: /* Intel 82371AB */
case 0x719b8086: /* Intel 82443MX */
/* Changing configuration is allowed. */
sc->cfg_irq9 = 1;
break;
#endif
case AMDSB_SMBUS_DEVID:
if (pci_get_revid(dev) >= AMDSB8_SMBUS_REVID)
sc->sb8xx = 1;
break;
case AMDFCH_SMBUS_DEVID:
case AMDCZ_SMBUS_DEVID:
sc->sb8xx = 1;
break;
}
if (sc->sb8xx) {
error = sb8xx_attach(dev);
if (error != 0)
goto fail;
else
goto no_intr;
}
sc->io_rid = PCI_BASE_ADDR_SMB;
sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->io_rid,
RF_ACTIVE);
if (sc->io_res == NULL) {
device_printf(dev, "Could not allocate I/O space\n");
error = ENXIO;
goto fail;
}
if (sc->cfg_irq9) {
pci_write_config(dev, PCIR_INTLINE, 0x9, 1);
pci_write_config(dev, PCI_HST_CFG_SMB,
PCI_INTR_SMB_IRQ9 | PCI_INTR_SMB_ENABLE, 1);
}
value = pci_read_config(dev, PCI_HST_CFG_SMB, 1);
sc->poll = (value & PCI_INTR_SMB_ENABLE) == 0;
intr = value & PCI_INTR_SMB_MASK;
switch (intr) {
case PCI_INTR_SMB_SMI:
str = "SMI";
break;
case PCI_INTR_SMB_IRQ9:
str = "IRQ 9";
break;
case PCI_INTR_SMB_IRQ_PCI:
str = "PCI IRQ";
break;
default:
str = "BOGUS";
}
device_printf(dev, "intr %s %s ", str,
sc->poll == 0 ? "enabled" : "disabled");
printf("revision %d\n", pci_read_config(dev, PCI_REVID_SMB, 1));
if (!sc->poll && intr == PCI_INTR_SMB_SMI) {
device_printf(dev,
"using polling mode when configured interrupt is SMI\n");
sc->poll = 1;
}
if (sc->poll)
goto no_intr;
if (intr != PCI_INTR_SMB_IRQ9 && intr != PCI_INTR_SMB_IRQ_PCI) {
device_printf(dev, "Unsupported interrupt mode\n");
error = ENXIO;
goto fail;
}
/* Force IRQ 9. */
rid = 0;
if (sc->cfg_irq9)
bus_set_resource(dev, SYS_RES_IRQ, rid, 9, 1);
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->irq_res == NULL) {
device_printf(dev, "Could not allocate irq\n");
error = ENXIO;
goto fail;
}
error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
NULL, intsmb_rawintr, sc, &sc->irq_hand);
if (error) {
device_printf(dev, "Failed to map intr\n");
goto fail;
}
no_intr:
sc->isbusy = 0;
sc->smbus = device_add_child(dev, "smbus", -1);
if (sc->smbus == NULL) {
device_printf(dev, "failed to add smbus child\n");
error = ENXIO;
goto fail;
}
error = device_probe_and_attach(sc->smbus);
if (error) {
device_printf(dev, "failed to probe+attach smbus child\n");
goto fail;
}
#ifdef ENABLE_ALART
/* Enable Arart */
bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
#endif
return (0);
fail:
intsmb_release_resources(dev);
return (error);
}
static int
ar71xx_ehci_attach(device_t self)
{
struct ar71xx_ehci_softc *isc = device_get_softc(self);
ehci_softc_t *sc = &isc->base;
int err;
int rid;
/* initialise some bus fields */
sc->sc_bus.parent = self;
sc->sc_bus.devices = sc->sc_devices;
sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
sc->sc_bus.dma_bits = 32;
/* get all DMA memory */
if (usb_bus_mem_alloc_all(&sc->sc_bus,
USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) {
return (ENOMEM);
}
sc->sc_bus.usbrev = USB_REV_2_0;
/* NB: hints fix the memory location and irq */
rid = 0;
sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
if (!sc->sc_io_res) {
device_printf(self, "Could not map memory\n");
goto error;
}
/*
* Craft special resource for bus space ops that handle
* byte-alignment of non-word addresses.
*/
sc->sc_io_tag = ar71xx_bus_space_reversed;
sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
sc->sc_io_size = rman_get_size(sc->sc_io_res);
rid = 0;
sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
RF_ACTIVE | RF_SHAREABLE);
if (sc->sc_irq_res == NULL) {
device_printf(self, "Could not allocate irq\n");
goto error;
}
sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
if (!sc->sc_bus.bdev) {
device_printf(self, "Could not add USB device\n");
goto error;
}
device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR);
sprintf(sc->sc_vendor, "Atheros");
err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
NULL, ar71xx_ehci_intr, sc, &sc->sc_intr_hdl);
if (err) {
device_printf(self, "Could not setup irq, %d\n", err);
sc->sc_intr_hdl = NULL;
goto error;
}
/*
* Arrange to force Host mode, select big-endian byte alignment,
* and arrange to not terminate reset operations (the adapter
* will ignore it if we do but might as well save a reg write).
* Also, the controller has an embedded Transaction Translator
* which means port speed must be read from the Port Status
* register following a port enable.
*/
sc->sc_flags = 0;
sc->sc_vendor_post_reset = ar71xx_ehci_post_reset;
switch (ar71xx_soc) {
case AR71XX_SOC_AR7241:
case AR71XX_SOC_AR7242:
case AR71XX_SOC_AR9130:
case AR71XX_SOC_AR9132:
case AR71XX_SOC_AR9330:
case AR71XX_SOC_AR9331:
case AR71XX_SOC_AR9341:
case AR71XX_SOC_AR9342:
case AR71XX_SOC_AR9344:
case AR71XX_SOC_QCA9533:
case AR71XX_SOC_QCA9533_V2:
case AR71XX_SOC_QCA9556:
case AR71XX_SOC_QCA9558:
sc->sc_flags |= EHCI_SCFLG_TT | EHCI_SCFLG_NORESTERM;
sc->sc_vendor_get_port_speed =
ehci_get_port_speed_portsc;
break;
default:
/* fallthrough */
break;
}
/*
* ehci_reset() needs the correct offset to access the host controller
* registers. The AR724x/AR913x offsets aren't 0.
*/
sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
(void) ehci_reset(sc);
err = ehci_init(sc);
if (!err) {
err = device_probe_and_attach(sc->sc_bus.bdev);
}
if (err) {
device_printf(self, "USB init failed err=%d\n", err);
goto error;
}
return (0);
error:
ar71xx_ehci_detach(self);
return (ENXIO);
}
static int
smu_attach(device_t dev)
{
struct smu_softc *sc;
phandle_t node, child;
uint8_t data[12];
sc = device_get_softc(dev);
mtx_init(&sc->sc_mtx, "smu", NULL, MTX_DEF);
sc->sc_cur_cmd = NULL;
sc->sc_doorbellirqid = -1;
sc->sc_u3 = 0;
if (OF_finddevice("/u3") != -1)
sc->sc_u3 = 1;
/*
* Map the mailbox area. This should be determined from firmware,
* but I have not found a simple way to do that.
*/
bus_dma_tag_create(NULL, 16, 0, BUS_SPACE_MAXADDR_32BIT,
BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE, 1, PAGE_SIZE, 0, NULL,
NULL, &(sc->sc_dmatag));
sc->sc_bt = &bs_le_tag;
bus_space_map(sc->sc_bt, SMU_MAILBOX, 4, 0, &sc->sc_mailbox);
/*
* Allocate the command buffer. This can be anywhere in the low 4 GB
* of memory.
*/
bus_dmamem_alloc(sc->sc_dmatag, (void **)&sc->sc_cmd, BUS_DMA_WAITOK |
BUS_DMA_ZERO, &sc->sc_cmd_dmamap);
bus_dmamap_load(sc->sc_dmatag, sc->sc_cmd_dmamap,
sc->sc_cmd, PAGE_SIZE, smu_phys_callback, sc, 0);
STAILQ_INIT(&sc->sc_cmdq);
/*
* Set up handlers to change CPU voltage when CPU frequency is changed.
*/
EVENTHANDLER_REGISTER(cpufreq_pre_change, smu_cpufreq_pre_change, dev,
EVENTHANDLER_PRI_ANY);
EVENTHANDLER_REGISTER(cpufreq_post_change, smu_cpufreq_post_change, dev,
EVENTHANDLER_PRI_ANY);
/*
* Detect and attach child devices.
*/
node = ofw_bus_get_node(dev);
for (child = OF_child(node); child != 0; child = OF_peer(child)) {
char name[32];
memset(name, 0, sizeof(name));
OF_getprop(child, "name", name, sizeof(name));
if (strncmp(name, "rpm-fans", 9) == 0 ||
strncmp(name, "fans", 5) == 0)
smu_attach_fans(dev, child);
if (strncmp(name, "sensors", 8) == 0)
smu_attach_sensors(dev, child);
if (strncmp(name, "smu-i2c-control", 15) == 0)
smu_attach_i2c(dev, child);
}
/* Some SMUs have the I2C children directly under the bus. */
smu_attach_i2c(dev, node);
/*
* Collect calibration constants.
*/
smu_get_datablock(dev, SMU_CPUTEMP_CAL, data, sizeof(data));
sc->sc_cpu_diode_scale = (data[4] << 8) + data[5];
sc->sc_cpu_diode_offset = (data[6] << 8) + data[7];
smu_get_datablock(dev, SMU_CPUVOLT_CAL, data, sizeof(data));
sc->sc_cpu_volt_scale = (data[4] << 8) + data[5];
sc->sc_cpu_volt_offset = (data[6] << 8) + data[7];
sc->sc_cpu_curr_scale = (data[8] << 8) + data[9];
sc->sc_cpu_curr_offset = (data[10] << 8) + data[11];
smu_get_datablock(dev, SMU_SLOTPW_CAL, data, sizeof(data));
sc->sc_slots_pow_scale = (data[4] << 8) + data[5];
sc->sc_slots_pow_offset = (data[6] << 8) + data[7];
/*
* Set up LED interface
*/
sc->sc_leddev = led_create(smu_set_sleepled, dev, "sleepled");
/*
* Reset on power loss behavior
*/
SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
"server_mode", CTLTYPE_INT | CTLFLAG_RW, dev, 0,
smu_server_mode, "I", "Enable reboot after power failure");
/*
* Set up doorbell interrupt.
*/
sc->sc_doorbellirqid = 0;
sc->sc_doorbellirq = bus_alloc_resource_any(smu_doorbell, SYS_RES_IRQ,
&sc->sc_doorbellirqid, RF_ACTIVE);
bus_setup_intr(smu_doorbell, sc->sc_doorbellirq,
INTR_TYPE_MISC | INTR_MPSAFE, NULL, smu_doorbell_intr, dev,
&sc->sc_doorbellirqcookie);
powerpc_config_intr(rman_get_start(sc->sc_doorbellirq),
INTR_TRIGGER_EDGE, INTR_POLARITY_LOW);
/*
* Connect RTC interface.
*/
clock_register(dev, 1000);
/*
* Learn about shutdown events
*/
EVENTHANDLER_REGISTER(shutdown_final, smu_shutdown, dev,
SHUTDOWN_PRI_LAST);
return (bus_generic_attach(dev));
}
/*
* Attach this instance, and then all the sub-devices
*/
static int
esp_pci_attach(device_t dev)
{
struct esp_pci_softc *esc;
struct ncr53c9x_softc *sc;
int error;
esc = device_get_softc(dev);
sc = &esc->sc_ncr53c9x;
NCR_LOCK_INIT(sc);
esc->sc_dev = dev;
sc->sc_glue = &esp_pci_glue;
pci_enable_busmaster(dev);
error = bus_alloc_resources(dev, esp_pci_res_spec, esc->sc_res);
if (error != 0) {
device_printf(dev, "failed to allocate resources\n");
bus_release_resources(dev, esp_pci_res_spec, esc->sc_res);
return (error);
}
error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
BUS_SPACE_MAXSIZE_32BIT, BUS_SPACE_UNRESTRICTED,
BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &esc->sc_pdmat);
if (error != 0) {
device_printf(dev, "cannot create parent DMA tag\n");
goto fail_res;
}
/*
* XXX More of this should be in ncr53c9x_attach(), but
* XXX should we really poke around the chip that much in
* XXX the MI code? Think about this more...
*/
/*
* Set up static configuration info.
*
* XXX we should read the configuration from the EEPROM.
*/
sc->sc_id = 7;
sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK;
sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE;
sc->sc_rev = NCR_VARIANT_AM53C974;
sc->sc_features = NCR_F_FASTSCSI | NCR_F_DMASELECT;
sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI;
sc->sc_freq = 40; /* MHz */
/*
* This is the value used to start sync negotiations
* Note that the NCR register "SYNCTP" is programmed
* in "clocks per byte", and has a minimum value of 4.
* The SCSI period used in negotiation is one-fourth
* of the time (in nanoseconds) needed to transfer one byte.
* Since the chip's clock is given in MHz, we have the following
* formula: 4 * period = (1000 / freq) * 4
*/
sc->sc_minsync = 1000 / sc->sc_freq;
sc->sc_maxxfer = DFLTPHYS; /* see below */
sc->sc_maxoffset = 15;
sc->sc_extended_geom = 1;
#define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */
/*
* Create the DMA tag and map for the data transfers.
*
* Note: given that bus_dma(9) only adheres to the requested alignment
* for the first segment (and that also only for bus_dmamem_alloc()ed
* DMA maps) we can't use the Memory Descriptor List. However, also
* when not using the MDL, the maximum transfer size apparently is
* limited to 4k so we have to split transfers up, which plain sucks.
*/
error = bus_dma_tag_create(esc->sc_pdmat, PAGE_SIZE, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
MDL_SEG_SIZE, 1, MDL_SEG_SIZE, BUS_DMA_ALLOCNOW,
busdma_lock_mutex, &sc->sc_lock, &esc->sc_xferdmat);
if (error != 0) {
device_printf(dev, "cannot create transfer DMA tag\n");
goto fail_pdmat;
}
error = bus_dmamap_create(esc->sc_xferdmat, 0, &esc->sc_xferdmam);
if (error != 0) {
device_printf(dev, "cannnot create transfer DMA map\n");
goto fail_xferdmat;
}
error = bus_setup_intr(dev, esc->sc_res[ESP_PCI_RES_INTR],
INTR_MPSAFE | INTR_TYPE_CAM, NULL, ncr53c9x_intr, sc,
&esc->sc_ih);
if (error != 0) {
device_printf(dev, "cannot set up interrupt\n");
goto fail_xferdmam;
}
/* Do the common parts of attachment. */
sc->sc_dev = esc->sc_dev;
error = ncr53c9x_attach(sc);
if (error != 0) {
device_printf(esc->sc_dev, "ncr53c9x_attach failed\n");
goto fail_intr;
}
return (0);
fail_intr:
bus_teardown_intr(esc->sc_dev, esc->sc_res[ESP_PCI_RES_INTR],
esc->sc_ih);
fail_xferdmam:
bus_dmamap_destroy(esc->sc_xferdmat, esc->sc_xferdmam);
fail_xferdmat:
bus_dma_tag_destroy(esc->sc_xferdmat);
fail_pdmat:
bus_dma_tag_destroy(esc->sc_pdmat);
fail_res:
bus_release_resources(dev, esp_pci_res_spec, esc->sc_res);
NCR_LOCK_DESTROY(sc);
return (error);
}
static int
ehci_ps3_attach(device_t dev)
{
ehci_softc_t *sc = device_get_softc(dev);
int rid, err;
sc->sc_bus.parent = dev;
sc->sc_bus.devices = sc->sc_devices;
sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
sc->sc_bus.dma_bits = 32;
/* get all DMA memory */
if (usb_bus_mem_alloc_all(&sc->sc_bus,
USB_GET_DMA_TAG(dev), &ehci_iterate_hw_softc))
return (ENOMEM);
rid = 1;
sc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&rid, RF_ACTIVE);
if (!sc->sc_io_res) {
device_printf(dev, "Could not map memory\n");
goto error;
}
sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
sc->sc_io_size = rman_get_size(sc->sc_io_res);
rid = 1;
sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->sc_irq_res == NULL) {
device_printf(dev, "Could not allocate irq\n");
return (ENXIO);
}
sc->sc_bus.bdev = device_add_child(dev, "usbus", -1);
if (!sc->sc_bus.bdev) {
device_printf(dev, "Could not add USB device\n");
return (ENXIO);
}
device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
sprintf(sc->sc_vendor, "Sony");
err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl);
if (err) {
device_printf(dev, "Could not setup error irq, %d\n", err);
goto error;
}
sc->sc_flags |= EHCI_SCFLG_BIGEMMIO;
err = ehci_init(sc);
if (err) {
device_printf(dev, "USB init failed err=%d\n", err);
goto error;
}
err = device_probe_and_attach(sc->sc_bus.bdev);
if (err == 0)
return (0);
error:
return (ENXIO);
}