/*******************************************************************************
* @fn rxFifoAboveThresholdISR
*
* @brief Function running every time the RX FIFO is filled above
* threshold (FIFO_THR = 120)
*
* @param none
*
* @return none
*/
static void rxFifoAboveThresholdISR(void) {
uint8 writeByte;
if (!packetReceived) {
// Change to fixed packet length mode when there is less than 256
// bytes left to receive
if (((bytesLeft - BYTES_IN_RX_FIFO) < (MAX_VARIABLE_LENGTH + 1)) && (pktFormat == INFINITE)) {
writeByte = FIXED_PACKET_LENGTH_MODE;
cc112xSpiWriteReg(CC112X_PKT_CFG0, &writeByte, 1);
pktFormat = FIXED;
}
// Read BYTS_IN_RX_FIFO bytes from the RX FIFO and update the variables
// keeping track of how many more bytes need to be read and where in
// rxBuffer they should be storeds
cc112xSpiReadRxFifo(pBufferIndex, BYTES_IN_RX_FIFO);
bytesLeft -= BYTES_IN_RX_FIFO;
pBufferIndex += BYTES_IN_RX_FIFO;
// Clear ISR flag
ioPinIntClear(IO_PIN_PORT_1, GPIO0);
}
}
/*******************************************************************************
* @fn packetReceivedISR
*
* @brief Function running every time a packet has been received
*
* @param none
*
* @return none
*/
static void packetReceivedISR(void) {
cc112xSpiReadRxFifo(pBufferIndex, bytesLeft);
packetReceived = TRUE;
cc112xSpiReadReg(CC112X_RSSI1,&rssi_readout,1);
// Convert to decimal value from 2's complement rssi_readout.
rssi = (int16)((int8)rssi_readout) - cc112xRssiOffset;
// Clear ISR flag
ioPinIntClear(IO_PIN_PORT_1, GPIO3);
}
/*******************************************************************************
* @fn syncReceivedISR
*
* @brief Function running every time a sync word has been received
*
* @param none
*
* @return none
*/
static void syncReceivedISR(void) {
uint8 numRxBytes;
uint8 writeByte;
// After the sync word is received one needs to wait for the two
// length bytes to be put in the RX FIFO
do {
cc112xSpiReadReg(CC112X_NUM_RXBYTES, &numRxBytes, 1);
} while (numRxBytes < 2);
// Read the length byte and store it in the packetLength variable
cc112xSpiReadRxFifo(rxBuffer, 2);
pBufferIndex += 2;
packetLength = (uint16)(((uint16)(rxBuffer[0] << 8)) | rxBuffer[1]);
// Make sure that the packet length is in the correct range, update
// variables and enable interrupt on falling edge of GPIO3 (PKT_SYNC_RXTX)
if ((packetLength > MAX_VARIABLE_LENGTH)
&& (packetLength <= PACKET_LENGTH)) {
bytesLeft = packetLength + 2;
fixedPacketLength = bytesLeft % (MAX_VARIABLE_LENGTH + 1);
writeByte = fixedPacketLength;
cc112xSpiWriteReg(CC112X_PKT_LEN, &writeByte, 1);
// Clear interrupt flag and enable GPIO3
ioPinIntClear(IO_PIN_PORT_1, GPIO3);
ioPinIntEnable(IO_PIN_PORT_1, GPIO3);
} else { // Exit RX and flush RX FIFO due to length byte being out of range
trxSpiCmdStrobe(CC112X_SIDLE);
trxSpiCmdStrobe(CC112X_SFRX);
state = RX_START;
}
// Clear ISR flag
ioPinIntClear(IO_PIN_PORT_1, GPIO2);
}
/******************************************************************************
* @fn perCC1120CC1190RxTxISR
*
* @brief ISR that's called when sync signal goes low.
* In RX State: Filters incoming data. The global rxData pointer
* always points to this functions static rxData_tmp(struct of
* same kind). The validnes of rxData fields is indicated by the
* the global flag packetSemaphore.
* In TX State: Nothing is done except it facilitates power
* consumption reduction when TX since the program doesn't need
* to wait until TX is done before re-enabling sync pin interrupt.
* cc1120cc1190RadioTxRx is also set to CC112X_STATE_IDLE to be consistent
* with program.
*
* input parameters
*
* @param none
*
* output parameters
*
* @return void
*/
void perCC1120CC1190RxTxISR(void)
{
uint8 rxBytes,rxLength,rssiIndex,lqiIndex;
/* This variable stores the data locally. Access is given to per_test by
* assigning this instance to the global rxData pointer
*/
static rxData_t rxData_tmp;
rxData = &rxData_tmp;
/* Checking if the chip is in RX state: */
if(cc1120cc1190RadioTxRx != CC112X_STATE_RX)
{
/* Transmission finished */
if((perSettings.deviceMode == MASTER_DEVICE) && (perSettings.linkTopology == LINK_2_WAY) && (perSettings.masterSlaveLinked ==PER_DEVICE_LINKED))
{
/* Only applicable when master in 2-way test */
cc1120cc1190RadioTxRx=CC112X_STATE_RX;
}
else
{
cc1120cc1190RadioTxRx = CC112X_STATE_IDLE;
}
return;
}
packetSemaphore |= SYNC_FOUND;
if(((perSettings.masterSlaveLinked == PER_DEVICE_LINKED)||(perSettings.masterSlaveLinked == PER_DEVICE_LINK_BYPASS)) && (perSettings.deviceMode == MASTER_DEVICE) && (perSettings.testRunning == PER_TRUE))
{
if(perSettings.linkTopology == LINK_1_WAY)
{
/* Read timer value and set the perSettings.packetRate valu(adjustment for temperature drift */
halTimer32kSetIntFrequency(perSettings.packetRate);
halTimer32kIntEnable();
}
else
{
/* LINK_2_WAY */
/* Timeout interrupt configuring is handled by the 2-way Per test */
timer32kValue = halTimer32kReadTimerValue();
halTimer32kAbort();
}
}
cc112xSpiReadReg(CC112X_NUM_RXBYTES,&rxBytes,1);
/* Checking if the FIFO is empty */
if(rxBytes == PER_FALSE)
{
/* The packet was removed by HW due to addr or length filtering -> Do nothing */
/* Report that a sync was detected */
rxData_tmp.rssi = perCC1120CC1190Read8BitRssi();
return;
}
else
{
/* The RX FIFO is not empty, process contents */
cc112xSpiReadRxFifo(&rxLength, 1);
/* Check that the packet length just read + FCS(2B) + length byte match the RXBYTES */
/* If these are not equal:
* - RXFIFO overflow: Received packets not processed while beeing in RX.
*/
if(rxBytes != (rxLength+3))
{
/* This is a fault FIFO condition -> clean FIFO and register a sync detection */
/* IDLE -> FLUSH RX FIFO -> RX */
cc1120cc1190RxIdle();
perCC1120CC1190EnterRx();
/* Report that a sync was detected */
rxData_tmp.rssi = perCC1120CC1190Read8BitRssi();
return;
}
else
{
/* We don't have a FIFO error condition -> get packet */
/* Length Field */
rxData_tmp.data[0] = rxLength;
rssiIndex = rxLength+1;
lqiIndex = rssiIndex +1;
/* Payload(ADDR + DATA + FCS) */
cc112xSpiReadRxFifo(&rxData_tmp.data[1], lqiIndex);
/* The whole packet has been read from the FIFO.
* Check if the CRC is correct and that the packet length is as expected.
* If not correct: report sync found and do not update RSSI or LQI.
*/
if((!(rxData_tmp.data[lqiIndex] & CC112X_LQI_CRC_OK_BM)) || (perSettings.payloadLength != rxLength ))
{
rxData_tmp.rssi = perCC1120CC1190Read8BitRssi();
return;
}
/* A complete error-free packet has arrived */
/* Measured data */
rxData_tmp.length = rxLength;
rxData_tmp.lqi = rxData_tmp.data[lqiIndex] & CC112X_LQI_EST_BM;
rxData_tmp.addr = rxData_tmp.data[1];
/* Convert RSSI value from 2's complement to decimal value accounting for offset value */
rxBytes = rxData_tmp.data[rssiIndex];
rxData_tmp.rssi = (int8)((int8)rxBytes) - cc1120cc1190RssiOffset;
/* Signal a good packet is received */
packetSemaphore |= PACKET_RECEIVED;
return;
}
}
}
