/*------------------------------------------------------------------------------------*/
static void switch_to_rx(transceiver_type_t t)
{
switch (t) {
#if (defined(MODULE_CC110X) || defined(MODULE_CC110X_LEGACY))
case TRANSCEIVER_CC1100:
cc110x_switch_to_rx();
break;
#endif
#ifdef MODULE_CC2420
case TRANSCEIVER_CC2420:
cc2420_switch_to_rx();
break;
#endif
#ifdef MODULE_NATIVENET
case TRANSCEIVER_NATIVE:
nativenet_switch_to_rx();
break;
#endif
#ifdef MODULE_AT86RF231
case TRANSCEIVER_AT86RF231:
at86rf231_switch_to_rx();
#endif
default:
break;
}
}
void cc2420_init(int tpid)
{
uint16_t reg;
transceiver_pid = tpid;
cc2420_spi_init();
hwtimer_wait(CC2420_WAIT_TIME);
cc2420_reset();
cc2420_strobe(CC2420_STROBE_XOSCON); //enable crystal
while((cc2420_strobe(NOBYTE) & 0x40) == 0); //wait for crystal to be stable
hwtimer_wait(CC2420_WAIT_TIME);
reg = cc2420_read_reg(CC2420_REG_MDMCTRL0);
reg |= CC2420_ADR_DECODE; //enable adr decode
reg |= CC2420_AUTOACK; //enable auto ack
reg |= CC2420_AUTOCRC; //enable auto crc
reg &= ~(CC2420_RES_FRM_MODE); //disable reserved frames
cc2420_write_reg(CC2420_REG_MDMCTRL0, reg);
/* Change default values as recomended in the data sheet, */
/* RX bandpass filter = 1.3uA. */
reg = cc2420_read_reg(CC2420_REG_RXCTRL1);
reg |= CC2420_RXBPF_LOCUR;
cc2420_write_reg(CC2420_REG_RXCTRL1, reg);
/* Set the FIFOP threshold to maximum. */
cc2420_write_reg(CC2420_REG_IOCFG0, 127);
/* Turn off "Security enable" (page 32). */
reg = cc2420_read_reg(CC2420_REG_SECCTRL0);
reg &= ~CC2420_RXFIFO_PROTECTION;
cc2420_write_reg(CC2420_REG_SECCTRL0, reg);
/* set output power to 0dbm */
cc2420_write_reg(CC2420_REG_TXCTRL, 0xA0FF);
cc2420_set_channel(CC2420_DEFAULT_CHANNR);
cc2420_set_pan(0x1111);
DEBUG("CC2420 initialized and set to channel %i and pan %i\n", radio_channel, radio_pan);
cc2420_init_interrupts();
cc2420_switch_to_rx();
}
