/** * @brief Start the CSI receiver * @param dev dev pointer to structure of cdsi_dev device data * @return 0 on success of a negative error value on error * * Starting the CSI receiver enables sending of UniPro packets encapsulating * CSI-2 data. Before starting the CSI receiver it must be initialized with a * call to csi_rx_init(). * * The CSI receiver can only be started when all lanes of the CSI input are in * the stopped state (LP-11). The caller must thus start the CSI input after the * CSI receiver. * * This function is stateless and must only be called when the CSI receiver is * initialized and not started. * * To stop the CSI receiver call csi_rx_stop(). */ int csi_rx_start(struct cdsi_dev *dev) { unsigned int timeout; /* Clear the line initialization done status. */ cdsi_write(dev, CDSI0_CDSIRX_LPRX_STATE_INT_STAT_OFFS, CDSI0_CDSIRX_LPRX_STATE_INT_STAT_LINEINITDONE_MASK); /* Start CDSIRX */ cdsi_write(dev, CDSI0_CDSIRX_START_OFFS, CDSI0_CDSIRX_START_CDSIRXSTART_MASK); /* Wait for line initialization to complete. */ for (timeout = 50; timeout != 0; --timeout) { uint32_t val; val = cdsi_read(dev, CDSI0_CDSIRX_LPRX_STATE_INT_STAT_OFFS); if (val & CDSI0_CDSIRX_LPRX_STATE_INT_STAT_LINEINITDONE_MASK) break; usleep(10); } if (timeout == 0) { printf("cdsi: line initialization timeout\n"); return -ETIMEDOUT; } printf("cdsi: line initialization complete (%u us)\n", (50 - timeout) * 10); return 0; }
uint32_t csi_rx_get_error(struct cdsi_dev *dev) { uint32_t val; val = cdsi_read(dev, CDSI0_CDSIRX_ERR_STATUS_OFFS); printf("cdsi: RX_ERR_STATUS 0x%08x\n", val); return val; }
/** * @brief Uninitialize the CSI receiver * @param dev dev pointer to structure of cdsi_dev device data * @return 0 on success of a negative error value on error * * Uninitializing the CSI receiver disables the clock to the CSIRX block, * lowering its power consumption. The receiver should be kept uninitialized for * as long as possible. * * This function is stateless and must only be called when the CSI receiver is * stopped and initialized. */ int csi_rx_uninit(struct cdsi_dev *dev) { uint32_t val; /* * Disable CDSIRX and the RX bridge and verify that the bridge became * idle. */ cdsi_write(dev, CDSI0_CDSIRX_CLKEN_OFFS, 0); cdsi_write(dev, CDSI0_AL_RX_BRG_MODE_OFFS, 0); usleep(10); val = cdsi_read(dev, CDSI0_AL_RX_BRG_MODE_OFFS); if (val & CDSI0_AL_RX_BRG_MODE_BUSY_MASK) printf("cdsi: RX bridge failed to become idle (0x%08x)\n", val); return 0; }
static int lg4892_init_lcd(struct cdsi_dev *dev) { uint32_t rdata; int ret = 0; int i, j; for (i = 0; i < (sizeof(LG4892) / sizeof(LG4892[0])); i++) { lowsyslog("count - %d\n", i); while (1) { if (!(cdsi_read(dev, CDSI0_CDSITX_SIDEBAND_STATUS_05_OFFS) & CDSI0_CDSITX_SIDEBAND_STATUS_05_SBO_APF_VHIF_BUSY_MASK)) { break; } } while (1) { if (!(cdsi_read(dev, CDSI0_CDSITX_SIDEBAND_STATUS_05_OFFS) & CDSI0_CDSITX_SIDEBAND_STATUS_05_APF_CMD_BUSY_MASK)) { break; } } while (1) { if (!(cdsi_read(dev, CDSI0_CDSITX_SIDEBAND_STATUS_06_OFFS) & CDSI0_CDSITX_INTERRUPT_STATUS_06_INT_APF_CMD_DONE_MASK)) { break; } } cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CMDIF_01_OFFS, 0x4); rdata = cdsi_read(dev, CDSI0_CDSITX_SIDEBAND_CMDIF_02_OFFS); rdata &= ~CDSI0_CDSITX_SIDEBAND_CMDIF_02_APF_CMD_PKT_DI_MASK; cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CMDIF_02_OFFS, rdata); rdata |= 0x39 << CDSI0_CDSITX_SIDEBAND_CMDIF_02_APF_CMD_PKT_DI_SHIFT; cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CMDIF_02_OFFS, rdata); rdata &= ~CDSI0_CDSITX_SIDEBAND_CMDIF_02_APF_CMD_PKT_WC_MASK; cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CMDIF_02_OFFS, rdata); rdata |= LG4892[i].size << CDSI0_CDSITX_SIDEBAND_CMDIF_02_APF_CMD_PKT_WC_SHIFT; cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CMDIF_02_OFFS, rdata); rdata = cdsi_read(dev, CDSI0_CDSITX_SIDEBAND_CMDIF_00_OFFS); rdata |= CDSI0_CDSITX_SIDEBAND_CMDIF_00_APF_CMD_REQ_MASK; cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CMDIF_00_OFFS, rdata); if (LG4892[i].size % 4) { for (j = 0; j < ((LG4892[i].size / 4) + 1); j++) { cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CMDIF_03_OFFS, LG4892[i].packet[j]); } } else { for (j = 0; j < (LG4892[i].size / 4); j++) { cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CMDIF_03_OFFS, LG4892[i].packet[j]); } } while (!(cdsi_read(dev, CDSI0_CDSITX_INTERRUPT_STATUS_06_OFFS) & CDSI0_CDSITX_INTERRUPT_STATUS_06_INT_APF_CMD_DONE_MASK)) ; rdata = cdsi_read(dev, CDSI0_CDSITX_INTERRUPT_STATUS_06_OFFS); rdata |= CDSI0_CDSITX_INTERRUPT_STATUS_06_INT_APF_CMD_DONE_MASK; cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_06_OFFS, rdata); if (i == 1) { for (j = 0; j < 0x170A390; j++) { __asm("nop"); } } } return ret; }
static void lg4892_cdsi_init_video(struct cdsi_dev *dev) { unsigned int rdata; cdsi_write(dev, CDSI0_AL_TX_BRG_CDSITX_MODE_OFFS, AL_TX_BRG_CDSITX_MODE_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_MODE_OFFS, AL_TX_BRG_MODE_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_TYPE_SEL1_SET_OFFS, AL_TX_BRG_TYPE_SEL1_SET_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_TYPE_SEL2_SET_OFFS, AL_TX_BRG_TYPE_SEL2_SET_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_TYPE_MASK1_SET_OFFS, AL_TX_BRG_TYPE_MASK1_SET_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_TYPE_MASK2_SET_OFFS, AL_TX_BRG_TYPE_MASK2_SET_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_COM_SET_OFFS, AL_TX_BRG_PIC_COM_SET_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_COM_VDELAYSTRCOUNT_OFFS, 0x00000874); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_COM_VDELAYENDCOUNT_OFFS, 0x00000000); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_COM_MAXFCNT_OFFS, AL_TX_BRG_PIC_COM_MAXFCNT_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_COM_3DCM_PLDT_OFFS, AL_TX_BRG_PIC_COM_3DCM_PLDT_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_COM_3DCM_LINE_OFFS, AL_TX_BRG_PIC_COM_3DCM_LINE_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_SYN_SET_OFFS, AL_TX_BRG_PIC_SYN_SET_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_SYN_LINE_OFFS, AL_TX_BRG_PIC_SYN_LINE_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_WAIT_CYCLE_SET_OFFS, AL_TX_BRG_WAIT_CYCLE_SET_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_VSYNC_LINE_SET_OFFS, AL_TX_BRG_VSYNC_LINE_SET_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_STATUS_ENABLE_OFFS, AL_TX_BRG_STATUS_ENABLE_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_CDSITX_MODE_OFFS, AL_TX_BRG_CDSITX_MODE_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_UNIPRO_BYTESWAP_OFFS, AL_TX_BRG_UNIPRO_BYTESWAP_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_MODE_OFFS, 0x00000091); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_FUNC_ENABLE_00_OFFS, CDSITX_INTERRUPT_FUNC_ENABLE_00_VAL); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_FUNC_ENABLE_01_OFFS, CDSITX_INTERRUPT_FUNC_ENABLE_01_VAL); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_FUNC_ENABLE_02_OFFS, CDSITX_INTERRUPT_FUNC_ENABLE_02_VAL); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_FUNC_ENABLE_03_OFFS, CDSITX_INTERRUPT_FUNC_ENABLE_03_VAL); cdsi_write(dev, CDSI0_CDSITX_POWER_SW_OFFS, CDSITX_POWER_SW_VAL); cdsi_write(dev, CDSI0_CDSITX_DPHY_RESET_OFFS, CDSITX_DPHY_RESET_VAL); cdsi_write(dev, CDSI0_CDSITX_PLL_CONFIG_00_OFFS, 0x0120105C); cdsi_write(dev, CDSI0_CDSITX_PLL_CONFIG_02_OFFS, CDSITX_PLL_CONFIG_02_VAL); cdsi_write(dev, CDSI0_CDSITX_PLL_CONTROL_00_OFFS, CDSITX_PLL_CONTROL_00_VAL); cdsi_write(dev, CDSI0_CDSITX_PLL_CONTROL_01_OFFS, CDSITX_PLL_CONTROL_01_VAL); cdsi_write(dev, CDSI0_CDSITX_LANE_ENABLE_00_OFFS, CDSITX_LANE_ENABLE_00_VAL); cdsi_write(dev, CDSI0_CDSITX_LANE_ENABLE_01_OFFS, CDSITX_LANE_ENABLE_01_VAL); cdsi_write(dev, CDSI0_CDSITX_LANE_ENABLE_02_OFFS, CDSITX_LANE_ENABLE_02_VAL); cdsi_write(dev, CDSI0_CDSITX_VREG_CONFIG_OFFS, CDSITX_VREG_CONFIG_VAL); cdsi_write(dev, CDSI0_CDSITX_VREG_CONTROL_OFFS, CDSITX_VREG_CONTROL_VAL); cdsi_write(dev, CDSI0_CDSITX_CSI2DSI_SELECT_OFFS, CDSITX_CSI2DSI_SELECT_VAL); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_00_OFFS, CDSITX_GLOBAL_TIMING_PARAM_00_VAL); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_01_OFFS, CDSITX_GLOBAL_TIMING_PARAM_01_VAL); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_02_OFFS, CDSITX_GLOBAL_TIMING_PARAM_02_VAL); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_03_OFFS, 0x0000000C); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_04_OFFS, 0x00210008); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_05_OFFS, 0x00100005); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_06_OFFS, 0x000C0009); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_07_OFFS, 0x00100008); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_08_OFFS, 0x0000131F); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_09_OFFS, 0x00000007); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_10_OFFS, 0x000C000E); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_00_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_00_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_01_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_01_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_02_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_02_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_03_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_03_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_04_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_04_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_05_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_05_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_06_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_06_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_07_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_07_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_08_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_08_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_09_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_09_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_10_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_10_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_11_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_11_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_00_OFFS, CDSITX_SIDEBAND_CONFIG_00_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_01_OFFS, CDSITX_SIDEBAND_CONFIG_01_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_02_OFFS, CDSITX_SIDEBAND_CONFIG_02_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_03_OFFS, CDSITX_SIDEBAND_CONFIG_03_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_04_OFFS, CDSITX_SIDEBAND_CONFIG_04_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_05_OFFS, CDSITX_SIDEBAND_CONFIG_05_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_06_OFFS, CDSITX_SIDEBAND_CONFIG_06_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_07_OFFS, CDSITX_SIDEBAND_CONFIG_07_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_08_OFFS, CDSITX_SIDEBAND_CONFIG_08_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_09_OFFS, CDSITX_SIDEBAND_CONFIG_09_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_10_OFFS, CDSITX_SIDEBAND_CONFIG_10_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_11_OFFS, 0x00000162); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_12_OFFS, 0x0000028A); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_13_OFFS, CDSITX_SIDEBAND_CONFIG_13_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_14_OFFS, CDSITX_SIDEBAND_CONFIG_14_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_15_OFFS, CDSITX_SIDEBAND_CONFIG_15_VAL); rdata = cdsi_read(dev, CDSI0_CDSITX_INTERRUPT_MASK_00_OFFS); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_MASK_00_OFFS, rdata & 0xFFFFFFF7); rdata = cdsi_read(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS); while ((rdata & 0x8) != 0x8) { rdata = cdsi_read(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS); } while ((rdata & 0x4) != 0x4) { rdata = cdsi_read(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS); } while ((rdata & 0x2) != 0x2) { rdata = cdsi_read(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS); } cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS, 0x0000000E); cdsi_write(dev, CDSI0_CDSITX_PISO_ENABLE_OFFS, CDSITX_PISO_ENABLE_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_INIT_CONTROL_00_OFFS, CDSITX_SIDEBAND_INIT_CONTROL_00_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_INIT_CONTROL_01_OFFS, CDSITX_SIDEBAND_INIT_CONTROL_01_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_INIT_CONTROL_02_OFFS, CDSITX_SIDEBAND_INIT_CONTROL_02_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_INIT_CONTROL_03_OFFS, CDSITX_SIDEBAND_INIT_CONTROL_03_VAL); rdata = cdsi_read(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS); while ((rdata & 0x1) != 0x1) { rdata = cdsi_read(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS); } cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS, 0x0000000E); cdsi_write(dev, CDSI0_AL_RX_BRG_MODE_OFFS, 0x00000001); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_10_OFFS, 0x000F0001); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS, 0xFFFFFFFF); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_01_OFFS, 0xFFFFFFFF); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_02_OFFS, 0xFFFFFFFF); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_03_OFFS, 0xFFFFFFFF); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_04_OFFS, 0xFFFFFFFF); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_05_OFFS, 0xFFFFFFFF); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_06_OFFS, 0xFFFFFFFF); cdsi_write(dev, CDSI0_CDSITX_LINK_RESET_OFFS, CDSITX_LINK_RESET_VAL); cdsi_write(dev, CDSI0_CDSITX_APF_RESET_OFFS, CDSITX_APF_RESET_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_INIT_CONTROL_04_OFFS, CDSITX_SIDEBAND_INIT_CONTROL_04_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_SYN_SET_OFFS, 0x00000001); cdsi_write(dev, CDSI0_AL_TX_BRG_VPARAM_UPDATE_OFFS, 0x00000003); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_COM_START_OFFS, 0x00000001); lowsyslog("--- CDSITX : Initialization completed ---\n"); }
/** * @brief Initialize the CSI receiver * @param dev dev pointer to structure of cdsi_dev device data * @return 0 on success of a negative error value on error * * Initialization of the CSI receiver configures and enables the CSIRX block * and performs LPRX calibration. This results in the CSI receiver being clocked * and ready to be started. * * The receiver shouldn't be left initialized when unused as it consumes power * in that state, even if not started yet. To uninitialize the CSI receiver and * put it back to sleep call csi_rx_uninit(). * * This function is stateless and must only be called when the CSI receiver is * unintialized. */ int csi_rx_init(struct cdsi_dev *dev, const struct csi_rx_config *cfg) { unsigned int timeout; /* Enable the Rx bridge and set to CSI mode */ cdsi_write(dev, CDSI0_AL_RX_BRG_MODE_OFFS, CDSI0_AL_RX_BRG_MODE_CSI2_MODE_MASK | CDSI0_AL_RX_BRG_MODE_BRG_EN_MASK); cdsi_write(dev, CDSI0_AL_RX_BRG_CSI_INFO_OFFS, 0); cdsi_write(dev, CDSI0_AL_RX_BRG_CSI_DT0_OFFS, 0); cdsi_write(dev, CDSI0_AL_RX_BRG_CSI_DT1_OFFS, 0); cdsi_write(dev, CDSI0_AL_RX_BRG_CSI_DT2_OFFS, 0); cdsi_write(dev, CDSI0_AL_RX_BRG_CSI_DT3_OFFS, 0); /* Enable CDSIRX */ cdsi_write(dev, CDSI0_CDSIRX_CLKEN_OFFS, CDSI0_CDSIRX_CLKEN_CDSIRXEN_MASK); /* Set CDSIRX functions enable */ cdsi_write(dev, CDSI0_CDSIRX_FUNC_ENABLE_OFFS, CDSI0_CDSIRX_FUNC_ENABLE_RXERRINTEN_MASK | CDSI0_CDSIRX_FUNC_ENABLE_DSIRXTRGINTEN_MASK | CDSI0_CDSIRX_FUNC_ENABLE_LPRXSTATEEN_MASK | CDSI0_CDSIRX_FUNC_ENABLE_RXERRINTSTATEEN_MASK | CDSI0_CDSIRX_FUNC_ENABLE_DSIRXTRIGINTSTATEN_MASK | CDSI0_CDSIRX_FUNC_ENABLE_LPRXSTATEINTSTATEEN_MASK | CDSI0_CDSIRX_FUNC_ENABLE_HSTOCNTEN_MASK); cdsi_write(dev, CDSI0_CDSIRX_ADDRESS_CONFIG_OFFS, 0); /* Set LPRX calibration */ cdsi_write(dev, CDSI0_CDSIRX_PPI_DPHY_LPRXCALCNTRL_OFFS, (25 << CDSI0_CDSIRX_PPI_DPHY_LPRXCALCNTRL_AUTOCALCNT_SHIFT) | (4 << CDSI0_CDSIRX_PPI_DPHY_LPRXCALCNTRL_LPRXCALTRIM_SHIFT)); cdsi_write(dev, CDSI0_CDSIRX_PPI_DPHY_LPRX_THSLD_OFFS, CDSI0_CDSIRX_PPI_DPHY_LPRX_THSLD_CLS_CUTRSEL_MASK | CDSI0_CDSIRX_PPI_DPHY_LPRX_THSLD_D3S_CUTRSEL_MASK | CDSI0_CDSIRX_PPI_DPHY_LPRX_THSLD_D2S_CUTRSEL_MASK | CDSI0_CDSIRX_PPI_DPHY_LPRX_THSLD_D1S_CUTRSEL_MASK | CDSI0_CDSIRX_PPI_DPHY_LPRX_THSLD_D0S_CUTRSEL_MASK); /* Clear the LPRX calibration status and start LPRX calibration. */ cdsi_write(dev, CDSI0_CDSIRX_LPRX_STATE_INT_STAT_OFFS, CDSI0_CDSIRX_LPRX_STATE_INT_STAT_AUTOCALDONE_MASK); cdsi_write(dev, CDSI0_CDSIRX_PPI_DPHY_LPRXAUTOCALST_OFFS, CDSI0_CDSIRX_PPI_DPHY_LPRXAUTOCALST_AUTOCALSTRT_MASK); /* CDSIRX configuration */ cdsi_write(dev, CDSI0_CDSIRX_CLKSEL_OFFS, (1 << CDSI0_CDSIRX_CLKSEL_PPIHSRXCLKSEL_SHIFT) | CDSI0_CDSIRX_CLKSEL_PPIHSRXCLKEN_MASK); cdsi_write(dev, CDSI0_CDSIRX_MODE_CONFIG_OFFS, CDSI0_CDSIRX_MODE_CONFIG_CSI2MODE_MASK); cdsi_write(dev, CDSI0_CDSIRX_LANE_ENABLE_OFFS, CDSI0_CDSIRX_LANE_ENABLE_CLANEEN_MASK | (cfg->num_lanes << CDSI0_CDSIRX_LANE_ENABLE_DTLANEEN_SHIFT)); cdsi_write(dev, CDSI0_CDSIRX_VC_ENABLE_OFFS, CDSI0_CDSIRX_VC_ENABLE_VC3EN_MASK | CDSI0_CDSIRX_VC_ENABLE_VC2EN_MASK | CDSI0_CDSIRX_VC_ENABLE_VC1EN_MASK | CDSI0_CDSIRX_VC_ENABLE_VC0EN_MASK); cdsi_write(dev, CDSI0_CDSIRX_LINE_INIT_COUNT_OFFS, 4800); cdsi_write(dev, CDSI0_CDSIRX_HSRXTO_COUNT_OFFS, 0xffffffff); cdsi_write(dev, CDSI0_CDSIRX_FUNC_MODE_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_PPI_DPHY_LPTXTIMECNT_OFFS, 0xfff); cdsi_write(dev, CDSI0_CDSIRX_DSI_LPTX_MODE_OFFS, CDSI0_CDSIRX_DSI_LPTX_MODE_TURNDISABLE_MASK); cdsi_write(dev, CDSI0_CDSIRX_PPI_DSI_BTA_COUNT_OFFS, (4 << CDSI0_CDSIRX_PPI_DSI_BTA_COUNT_TXTAGO_SHIFT) | (2047 << CDSI0_CDSIRX_PPI_DSI_BTA_COUNT_RXTASURECNT_SHIFT)); cdsi_write(dev, CDSI0_CDSIRX_PPI_HSRX_CNTRL_OFFS, CDSI0_CDSIRX_PPI_HSRX_CNTRL_CLHSRXENFCTRL_MASK); cdsi_write(dev, CDSI0_CDSIRX_PPI_HSRX_COUNT_OFFS, (4 << CDSI0_CDSIRX_PPI_HSRX_COUNT_CLSETTLECNT_SHIFT) | (10 << CDSI0_CDSIRX_PPI_HSRX_COUNT_DTCLRSIPOCNT_SHIFT)); cdsi_write(dev, CDSI0_CDSIRX_PPI_DPHY_POWERCNTRL_OFFS, CDSI0_CDSIRX_PPI_DPHY_POWERCNTRL_EN_ZEMIPIV12_MASK | CDSI0_CDSIRX_PPI_DPHY_POWERCNTRL_V12EN_MASK); cdsi_write(dev, CDSI0_CDSIRX_PPI_DSI_DPHYTX_ADJUST_OFFS, 2 << CDSI0_CDSIRX_PPI_DSI_DPHYTX_ADJUST_D0S_LPTXCURREN_SHIFT); cdsi_write(dev, CDSI0_CDSIRX_PPI_DPHY_HSRX_ADJUST_OFFS, (2 << CDSI0_CDSIRX_PPI_DPHY_HSRX_ADJUST_CLS_HSRXTUNE_SHIFT) | (2 << CDSI0_CDSIRX_PPI_DPHY_HSRX_ADJUST_D3S_HSRXTUNE_SHIFT) | (2 << CDSI0_CDSIRX_PPI_DPHY_HSRX_ADJUST_D2S_HSRXTUNE_SHIFT) | (2 << CDSI0_CDSIRX_PPI_DPHY_HSRX_ADJUST_D1S_HSRXTUNE_SHIFT) | (2 << CDSI0_CDSIRX_PPI_DPHY_HSRX_ADJUST_D0S_HSRXTUNE_SHIFT)); cdsi_write(dev, CDSI0_CDSIRX_PPI_DPHY_DLYCNTRL_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_LPRX_STATE_INT_MASK_OFFS, CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKCLULPSEXIT_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKD3ULPSEXIT_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKD2ULPSEXIT_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKD1ULPSEXIT_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKD0ULPSEXIT_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKCLULPSENTER_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKD3ULPSENTER_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKD2ULPSENTER_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKD1ULPSENTER_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKD0ULPSENTER_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKCLSTOPRISE_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKD3STOPRISE_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKD2STOPRISE_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKD1STOPRISE_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKD0STOPRISE_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKAUTOCALDONE_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKDIRECTIONFALL_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKDIRECTIONRISE_MASK | CDSI0_CDSIRX_LPRX_STATE_INT_MASK_MASKLINEINITDONE_MASK); cdsi_write(dev, CDSI0_CDSIRX_DSI_RXTRIG_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_RXERR_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_TXERR_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_DSI_VC0_SH_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_DSI_VC1_SH_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_DSI_VC2_SH_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_DSI_VC3_SH_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_DSI_VC0_LN_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_DSI_VC1_LN_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_DSI_VC2_LN_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_DSI_VC3_LN_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_CSI2_VC0_SH_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_CSI2_VC1_SH_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_CSI2_VC2_SH_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_CSI2_VC3_SH_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_CSI2_VC0_LN0_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_CSI2_VC0_LN1_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_CSI2_VC1_LN0_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_CSI2_VC1_LN1_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_CSI2_VC2_LN0_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_CSI2_VC2_LN1_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_CSI2_VC3_LN0_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_CSI2_VC3_LN1_INT_MASK_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_DSI_LPTXTO_COUNT_OFFS, 0xffffffff); cdsi_write(dev, CDSI0_CDSIRX_DSI_TATO_COUNT_OFFS, 0xffffffff); cdsi_write(dev, CDSI0_CDSIRX_DSI_WAITBTA_COUNT_OFFS, 0x10000010); /* Wait for LPRX calibration to complete. */ for (timeout = 50; timeout != 0; --timeout) { uint32_t val; val = cdsi_read(dev, CDSI0_CDSIRX_LPRX_STATE_INT_STAT_OFFS); if (val & CDSI0_CDSIRX_LPRX_STATE_INT_STAT_AUTOCALDONE_MASK) break; usleep(10); } if (timeout == 0) { printf("cdsi: LPRX calibration timeout\n"); return -ETIMEDOUT; } printf("cdsi: LPRX calibration complete (%u us)\n", (50 - timeout) * 10); return 0; }
/** * @brief Stop the CSI receiver * @param dev dev pointer to structure of cdsi_dev device data * @return 0 on success of a negative error value on error * * Stopping the CSI receiver disables sending of UniPro packets. Once stopped * the CSI receiver can be put to power down mode with a call to * csi_rx_uninit(). * * The CSI receiver can only be stopped when all lanes of the CSI input are in * the stopped state (LP-11). The caller must thus stop the CSI input before the * CSI receiver. * * This function is stateless and must only be called when the CSI receiver is * started. */ int csi_rx_stop(struct cdsi_dev *dev) { const uint32_t hs_mask = CDSI0_CDSIRX_LANE_STATUS_HS_CLRXACTIVEHS_MASK | CDSI0_CDSIRX_LANE_STATUS_HS_D3RXACTIVEHS_MASK | CDSI0_CDSIRX_LANE_STATUS_HS_D2RXACTIVEHS_MASK | CDSI0_CDSIRX_LANE_STATUS_HS_D1RXACTIVEHS_MASK | CDSI0_CDSIRX_LANE_STATUS_HS_D0RXACTIVEHS_MASK; const uint32_t lp_mask = CDSI0_CDSIRX_LANE_STATUS_LP_CLSTOPSTATE_MASK | CDSI0_CDSIRX_LANE_STATUS_LP_L3STOPSTATE_MASK | CDSI0_CDSIRX_LANE_STATUS_LP_L2STOPSTATE_MASK | CDSI0_CDSIRX_LANE_STATUS_LP_L1STOPSTATE_MASK | CDSI0_CDSIRX_LANE_STATUS_LP_L0STOPSTATE_MASK; unsigned int timeout; uint32_t val; /* * Wait for the CSI receiver to become idle. Lanes should first switch to * Low Power mode, then to the stop state (LP-11) and finally the CSI * receiver should become idle. */ for (timeout = 0; timeout < CSI_RX_STOP_TIMEOUT; ++timeout) { val = cdsi_read(dev, CDSI0_CDSIRX_LANE_STATUS_HS_OFFS); if (!(val & hs_mask)) break; usleep(10); } if (val & hs_mask) printf("cdsi: lanes failed to switch to LP (0x%08x)\n", val); else printf("cdsi: lanes switched to LP (%u us)\n", timeout * 10); for (timeout = 0; timeout < CSI_RX_STOP_TIMEOUT; ++timeout) { val = cdsi_read(dev, CDSI0_CDSIRX_LANE_STATUS_LP_OFFS); if ((val & lp_mask) == lp_mask) break; usleep(10); } if ((val & lp_mask) != lp_mask) printf("cdsi: lanes failed to switch to LP-11 (0x%08x)\n", val); else printf("cdsi: lanes switched to LP-11 (%u us)\n", timeout * 10); for (timeout = 0; timeout < CSI_RX_STOP_TIMEOUT; ++timeout) { val = cdsi_read(dev, CDSI0_CDSIRX_INTERNAL_STAT_OFFS); if (!val) break; usleep(10); } if (val) printf("cdsi: CDSIRX failed to become idle (0x%08x)\n", val); else printf("cdsi: CDSIRX became idle (%u us)\n", timeout * 10); /* Stop CDSIRX and clear its internal state. */ cdsi_write(dev, CDSI0_CDSIRX_START_OFFS, 0); cdsi_write(dev, CDSI0_CDSIRX_SYSTEM_INIT_OFFS, CDSI0_CDSIRX_SYSTEM_INIT_SYSINIT_MASK); return 0; }
/** * @brief Set the registers in CSI controller to start transfer. * @param dev Pointer to the CDSI device * @param cfg Pointer to CSI transmitter configuration structure * * @return 0 on success or a negative error code on failure. */ int csi_tx_start(struct cdsi_dev *dev, struct csi_tx_config *cfg) { uint32_t rdata; /* Set to Tx mode for CDSI */ cdsi_write(dev, CDSI0_AL_TX_BRG_CDSITX_MODE_OFFS, AL_TX_BRG_CDSITX_MODE_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_SOFT_RESET_OFFS, CDSI0_AL_TX_BRG_ENABLE_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_SYSCLK_ENABLE_OFFS, CDSI0_AL_TX_BRG_ENABLE_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_ENABLE_OFFS, CDSI0_AL_TX_BRG_ENABLE_VAL); /* Tx bridge setting */ cdsi_write(dev, CDSI0_AL_TX_BRG_MODE_OFFS, AL_TX_BRG_MODE_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_COM_SET_OFFS, AL_TX_BRG_PIC_COM_SET_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_COM_VDELAYSTRCOUNT_OFFS, AL_TX_BRG_PIC_COM_VDELAYSTRCOUNT_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_COM_VDELAYENDCOUNT_OFFS, AL_TX_BRG_PIC_COM_VDELAYENDCOUNT_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_COM_MAXFCNT_OFFS, AL_TX_BRG_PIC_COM_MAXFCNT_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_SYN_SET_OFFS, AL_TX_BRG_PIC_SYN_SET_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_SYN_LINE_OFFS, AL_TX_BRG_PIC_SYN_LINE_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_COM_3DCM_PLDT_OFFS, AL_TX_BRG_PIC_COM_3DCM_PLDT_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_COM_3DCM_LINE_OFFS, AL_TX_BRG_PIC_COM_3DCM_LINE_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_WAIT_CYCLE_SET_OFFS, AL_TX_BRG_WAIT_CYCLE_SET_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_VSYNC_LINE_SET_OFFS, AL_TX_BRG_VSYNC_LINE_SET_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_TYPE_SEL1_SET_OFFS, AL_TX_BRG_TYPE_SEL1_SET_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_TYPE_SEL2_SET_OFFS, AL_TX_BRG_TYPE_SEL2_SET_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_TYPE_MASK1_SET_OFFS, AL_TX_BRG_TYPE_MASK1_SET_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_TYPE_MASK2_SET_OFFS, AL_TX_BRG_TYPE_MASK2_SET_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_STATUS_ENABLE_OFFS, AL_TX_BRG_STATUS_ENABLE_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_UNIPRO_BYTESWAP_OFFS, AL_TX_BRG_UNIPRO_BYTESWAP_VAL); /* Tx bridge enable */ cdsi_write(dev, CDSI0_AL_TX_BRG_MODE_OFFS, 0x00000093); /* CDSITX setting */ cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_FUNC_ENABLE_00_OFFS, CDSITX_INTERRUPT_FUNC_ENABLE_00_VAL); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_FUNC_ENABLE_01_OFFS, CDSITX_INTERRUPT_FUNC_ENABLE_01_VAL); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_FUNC_ENABLE_02_OFFS, CDSITX_INTERRUPT_FUNC_ENABLE_02_VAL); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_FUNC_ENABLE_03_OFFS, CDSITX_INTERRUPT_FUNC_ENABLE_03_VAL); cdsi_write(dev, CDSI0_CDSITX_POWER_SW_OFFS, CDSITX_POWER_SW_VAL); /* D-PHY reset deassertion */ cdsi_write(dev, CDSI0_CDSITX_DPHY_RESET_OFFS, CDSITX_DPHY_RESET_VAL); /* D-PHY PLL setting */ cdsi_write(dev, CDSI0_CDSITX_PLL_CONFIG_00_OFFS, CDSITX_PLL_CONFIG_00_VAL); cdsi_write(dev, CDSI0_CDSITX_PLL_CONFIG_02_OFFS, CDSITX_PLL_CONFIG_02_VAL); /* D-PHY PLL enable */ cdsi_write(dev, CDSI0_CDSITX_PLL_CONTROL_00_OFFS, CDSITX_PLL_CONTROL_00_VAL); cdsi_write(dev, CDSI0_CDSITX_PLL_CONTROL_01_OFFS, CDSITX_PLL_CONTROL_01_VAL); /* CDSITX setting */ cdsi_write(dev, CDSI0_CDSITX_LANE_ENABLE_00_OFFS, CDSITX_LANE_ENABLE_00_VAL); cdsi_write(dev, CDSI0_CDSITX_LANE_ENABLE_01_OFFS, CDSITX_LANE_ENABLE_01_VAL); cdsi_write(dev, CDSI0_CDSITX_LANE_ENABLE_02_OFFS, CDSITX_LANE_ENABLE_02_VAL); /* D-PHY Vreg setting */ cdsi_write(dev, CDSI0_CDSITX_VREG_CONFIG_OFFS, CDSITX_VREG_CONFIG_VAL); /* D-PHY Vreg enable */ cdsi_write(dev, CDSI0_CDSITX_VREG_CONTROL_OFFS, CDSITX_VREG_CONTROL_VAL); cdsi_write(dev, CDSI0_CDSITX_LPRX_CALIB_CONFIG_OFFS, CDSI0_CDSITX_LPRX_CALIB_CONFIG_VAL); cdsi_write(dev, CDSI0_CDSITX_LPRX_CALIB_CONTROL_OFFS, CDSI0_CDSITX_LPRX_CALIB_CONTROL_VAL); /* CDSITX setting */ cdsi_write(dev, CDSI0_CDSITX_CSI2DSI_SELECT_OFFS, CDSITX_CSI2DSI_SELECT_VAL); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_00_OFFS, CDSITX_GLOBAL_TIMING_PARAM_00_VAL); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_01_OFFS, CDSITX_GLOBAL_TIMING_PARAM_01_VAL); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_02_OFFS, CDSITX_GLOBAL_TIMING_PARAM_02_VAL); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_03_OFFS, CDSITX_GLOBAL_TIMING_PARAM_03_VAL); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_04_OFFS, CDSITX_GLOBAL_TIMING_PARAM_04_VAL); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_05_OFFS, CDSITX_GLOBAL_TIMING_PARAM_05_VAL); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_06_OFFS, CDSITX_GLOBAL_TIMING_PARAM_06_VAL); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_07_OFFS, CDSITX_GLOBAL_TIMING_PARAM_07_VAL); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_08_OFFS, CDSITX_GLOBAL_TIMING_PARAM_08_VAL); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_09_OFFS, CDSITX_GLOBAL_TIMING_PARAM_09_VAL); cdsi_write(dev, CDSI0_CDSITX_GLOBAL_TIMING_PARAM_10_OFFS, CDSITX_GLOBAL_TIMING_PARAM_10_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_00_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_00_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_01_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_01_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_02_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_02_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_03_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_03_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_04_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_04_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_05_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_05_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_06_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_06_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_07_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_07_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_08_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_08_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_09_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_09_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_10_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_10_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_COUNT_CONFIG_11_OFFS, CDSITX_SIDEBAND_COUNT_CONFIG_11_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_00_OFFS, CDSITX_SIDEBAND_CONFIG_00_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_01_OFFS, CDSITX_SIDEBAND_CONFIG_01_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_02_OFFS, CDSITX_SIDEBAND_CONFIG_02_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_03_OFFS, CDSITX_SIDEBAND_CONFIG_03_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_04_OFFS, CDSITX_SIDEBAND_CONFIG_04_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_05_OFFS, CDSITX_SIDEBAND_CONFIG_05_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_06_OFFS, CDSITX_SIDEBAND_CONFIG_06_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_07_OFFS, CDSITX_SIDEBAND_CONFIG_07_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_08_OFFS, CDSITX_SIDEBAND_CONFIG_08_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_09_OFFS, CDSITX_SIDEBAND_CONFIG_09_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_10_OFFS, CDSITX_SIDEBAND_CONFIG_10_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_11_OFFS, CDSITX_SIDEBAND_CONFIG_11_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_12_OFFS, CDSITX_SIDEBAND_CONFIG_12_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_13_OFFS, CDSITX_SIDEBAND_CONFIG_13_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_14_OFFS, CDSITX_SIDEBAND_CONFIG_14_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_CONFIG_15_OFFS, CDSITX_SIDEBAND_CONFIG_15_VAL); rdata = cdsi_read(dev, CDSI0_CDSITX_INTERRUPT_MASK_00_OFFS); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_MASK_00_OFFS, rdata & 0xFFFFFFF7); /* Wait PLL lockup time */ rdata = cdsi_read(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS); while((rdata & CDSI0_CDSITX_INTERRUPT_STATUS_00_INT_DPHY_LOCKUPDONE_MASK) == 0x0) { rdata = cdsi_read(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS); } /* Wait D-PHY Vreg startup */ while((rdata & CDSI0_CDSITX_INTERRUPT_STATUS_00_INT_DPHY_HSTXVREGRDY_MASK) == 0x0) { rdata = cdsi_read(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS); } cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS, 0x0000000A); cdsi_write(dev, CDSI0_CDSITX_PISO_ENABLE_OFFS, CDSITX_PISO_ENABLE_VAL); /* CDSITX setting */ cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_INIT_CONTROL_00_OFFS, CDSITX_SIDEBAND_INIT_CONTROL_00_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_INIT_CONTROL_01_OFFS, CDSITX_SIDEBAND_INIT_CONTROL_01_VAL); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_INIT_CONTROL_02_OFFS, CDSITX_SIDEBAND_INIT_CONTROL_02_VAL); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS, 0x00000001); rdata = cdsi_read(dev, CDSI0_CDSITX_INTERRUPT_MASK_00_OFFS); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_MASK_00_OFFS, rdata & 0xFFFFFFFE); rdata = cdsi_read(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS); cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_INIT_CONTROL_03_OFFS, CDSITX_SIDEBAND_INIT_CONTROL_03_VAL); /* Wait D-PHY line initialization */ while ((rdata & CDSI0_CDSITX_INTERRUPT_STATUS_00_INT_DPHY_LINEINITDONE_MASK) == 0x0) { rdata = cdsi_read(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS); } cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS, 0x00000001); cdsi_write(dev, CDSI0_AL_RX_BRG_MODE_OFFS, 0x00000003); /* Clear all interrupt statuses */ cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_00_OFFS, 0xFFFFFFFF); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_01_OFFS, 0xFFFFFFFF); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_02_OFFS, 0xFFFFFFFF); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_03_OFFS, 0xFFFFFFFF); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_04_OFFS, 0xFFFFFFFF); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_05_OFFS, 0xFFFFFFFF); cdsi_write(dev, CDSI0_CDSITX_INTERRUPT_STATUS_06_OFFS, 0xFFFFFFFF); /* Reset deassertion for LINK */ cdsi_write(dev, CDSI0_CDSITX_LINK_RESET_OFFS, CDSITX_LINK_RESET_VAL); /* Reset deassertion for APF */ cdsi_write(dev, CDSI0_CDSITX_APF_RESET_OFFS, CDSITX_APF_RESET_VAL); /* APF start */ cdsi_write(dev, CDSI0_CDSITX_SIDEBAND_INIT_CONTROL_04_OFFS, CDSITX_SIDEBAND_INIT_CONTROL_04_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_COM_SET_OFFS, 0X0000000B); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_SYN_SET_OFFS, 0X00000001); cdsi_write(dev, CDSI0_AL_TX_BRG_VPARAM_UPDATE_OFFS, CDSI0_AL_TX_BRG_VPARAM_UPDATE_VAL); cdsi_write(dev, CDSI0_AL_TX_BRG_PIC_COM_START_OFFS, CDSI0_AL_TX_BRG_PIC_COM_START_VAL); cdsi_write(dev, CDSI0_AL_RX_BRG_CSI_INFO_OFFS, CDSI0_AL_RX_BRG_CSI_INFO_VAL); cdsi_write(dev, CDSI0_AL_RX_BRG_CSI_DT0_OFFS, CDSI0_AL_RX_BRG_CSI_DT0_VAL); return 0; }