static int msm_hsl_loopback_enable_set(void *data, u64 val)
{
struct msm_hsl_port *msm_hsl_port = data;
struct uart_port *port = &(msm_hsl_port->uart);
unsigned long flags;
int ret = 0;
ret = clk_set_rate(msm_hsl_port->clk, 7372800);
if (!ret)
clk_en(port, 1);
else {
pr_err("%s(): Error: Setting the clock rate\n", __func__);
return -EINVAL;
}
if (val) {
spin_lock_irqsave(&port->lock, flags);
ret = msm_hsl_read(port, UARTDM_MR2_ADDR);
ret |= UARTDM_MR2_LOOP_MODE_BMSK;
msm_hsl_write(port, ret, UARTDM_MR2_ADDR);
spin_unlock_irqrestore(&port->lock, flags);
} else {
spin_lock_irqsave(&port->lock, flags);
ret = msm_hsl_read(port, UARTDM_MR2_ADDR);
ret &= ~UARTDM_MR2_LOOP_MODE_BMSK;
msm_hsl_write(port, ret, UARTDM_MR2_ADDR);
spin_unlock_irqrestore(&port->lock, flags);
}
clk_en(port, 0);
return 0;
}
static int msm_hsl_loopback_enable_set(void *data, u64 val)
{
struct msm_hsl_port *msm_hsl_port = data;
struct uart_port *port = &(msm_hsl_port->uart);
unsigned int vid;
unsigned long flags;
int ret = 0;
ret = clk_set_rate(msm_hsl_port->clk, 7372800);
if (!ret)
clk_en(port, 1);
else {
E("%s(): Error: Setting the clock rate\n", __func__);
return -EINVAL;
}
vid = msm_hsl_port->ver_id;
if (val) {
spin_lock_irqsave(&port->lock, flags);
ret = msm_hsl_read(port, regmap[vid][UARTDM_MR2]);
ret |= UARTDM_MR2_LOOP_MODE_BMSK;
msm_hsl_write(port, ret, regmap[vid][UARTDM_MR2]);
spin_unlock_irqrestore(&port->lock, flags);
E("%s(): irda loopback enabled for line(%d)\n", __func__, port->line);
} else {
spin_lock_irqsave(&port->lock, flags);
ret = msm_hsl_read(port, regmap[vid][UARTDM_MR2]);
ret &= ~UARTDM_MR2_LOOP_MODE_BMSK;
msm_hsl_write(port, ret, regmap[vid][UARTDM_MR2]);
spin_unlock_irqrestore(&port->lock, flags);
}
clk_en(port, 0);
return 0;
}
static irqreturn_t msm_hsl_irq(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
unsigned int misr;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
clk_en(port, 1);
misr = msm_hsl_read(port, UARTDM_MISR_ADDR);
msm_hsl_write(port, 0, UARTDM_IMR_ADDR); /* disable interrupt */
if (misr & (UARTDM_ISR_RXSTALE_BMSK | UARTDM_ISR_RXLEV_BMSK)) {
handle_rx(port, misr);
if (misr & (UARTDM_ISR_RXSTALE_BMSK))
msm_hsl_write(port, RESET_STALE_INT, UARTDM_CR_ADDR);
msm_hsl_write(port, 6500, UARTDM_DMRX_ADDR);
msm_hsl_write(port, STALE_EVENT_ENABLE, UARTDM_CR_ADDR);
}
if (misr & UARTDM_ISR_TXLEV_BMSK)
handle_tx(port);
if (misr & UARTDM_ISR_DELTA_CTS_BMSK)
handle_delta_cts(port);
/* restore interrupt */
msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
clk_en(port, 0);
spin_unlock_irqrestore(&port->lock, flags);
return IRQ_HANDLED;
}
static void msm_hsl_power_irda(struct uart_port *port, unsigned int state,
unsigned int oldstate)
{
int ret;
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
D("%s (): ir, state %d\n", __func__, state);
switch (state) {
case 0:
irda_enable_flg = 1;
enable_irda(3);
ret = clk_set_rate(msm_hsl_port->clk, 7372800);
if (ret)
E("%s(): Error setting UART clock rate\n",
__func__);
clk_en(port, 1);
break;
case 3:
irda_enable_flg = 0;
enable_irda(0);
clk_en(port, 0);
break;
default:
E("%s(): msm_serial_hsl: Unknown PM state %d\n",
__func__, state);
}
}
static void msm_hsl_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
unsigned int mr;
unsigned int loop_mode;
clk_en(port, 1);
mr = msm_hsl_read(port, UARTDM_MR1_ADDR);
if (!(mctrl & TIOCM_RTS)) {
mr &= ~UARTDM_MR1_RX_RDY_CTL_BMSK;
msm_hsl_write(port, mr, UARTDM_MR1_ADDR);
msm_hsl_write(port, RFR_HIGH, UARTDM_CR_ADDR);
} else {
mr |= UARTDM_MR1_RX_RDY_CTL_BMSK;
msm_hsl_write(port, mr, UARTDM_MR1_ADDR);
}
loop_mode = TIOCM_LOOP & mctrl;
if (loop_mode) {
mr = msm_hsl_read(port, UARTDM_MR2_ADDR);
mr |= UARTDM_MR2_LOOP_MODE_BMSK;
msm_hsl_write(port, mr, UARTDM_MR2_ADDR);
/* Reset TX */
msm_hsl_reset(port);
/* Turn on Uart Receiver & Transmitter*/
msm_hsl_write(port, UARTDM_CR_RX_EN_BMSK
| UARTDM_CR_TX_EN_BMSK, UARTDM_CR_ADDR);
}
clk_en(port, 0);
}
static void msm_hsl_power(struct uart_port *port, unsigned int state,
unsigned int oldstate)
{
int ret;
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
switch (state) {
case 0:
ret = clk_set_rate(msm_hsl_port->clk, 7372800);
if (ret)
pr_err("%s(): Error setting UART clock rate\n",
__func__);
clk_en(port, 1);
break;
case 3:
clk_en(port, 0);
ret = clk_set_rate(msm_hsl_port->clk, 0);
if (ret)
pr_err("%s(): Error setting UART clock rate to zero.\n",
__func__);
break;
default:
pr_err("%s(): msm_serial_hsl: Unknown PM state %d\n",
__func__, state);
}
}
static void msm_hsl_shutdown(struct uart_port *port)
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
struct platform_device *pdev = to_platform_device(port->dev);
const struct msm_serial_hslite_platform_data *pdata =
pdev->dev.platform_data;
clk_en(port, 1);
msm_hsl_port->imr = 0;
msm_hsl_write(port, 0, UARTDM_IMR_ADDR); /* disable interrupts */
clk_en(port, 0);
free_irq(port->irq, port);
#ifndef CONFIG_PM_RUNTIME
msm_hsl_deinit_clock(port);
#endif
pm_runtime_put_sync(port->dev);
if (!(is_console(port)) || (!port->cons) ||
(port->cons && (!(port->cons->flags & CON_ENABLED)))) {
if (pdata && pdata->config_gpio) {
gpio_free(pdata->uart_tx_gpio);
gpio_free(pdata->uart_rx_gpio);
}
}
}
static void msm_hsl_start_tx(struct uart_port *port)
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
clk_en(port, 1);
msm_hsl_port->imr |= UARTDM_ISR_TXLEV_BMSK;
msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
clk_en(port, 0);
}
static void msm_hsl_enable_ms(struct uart_port *port)
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
clk_en(port, 1);
msm_hsl_port->imr |= UARTDM_ISR_DELTA_CTS_BMSK;
msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
clk_en(port, 0);
}
static unsigned int msm_hsl_tx_empty(struct uart_port *port)
{
unsigned int ret;
clk_en(port, 1);
ret = (msm_hsl_read(port, UARTDM_SR_ADDR) &
UARTDM_SR_TXEMT_BMSK) ? TIOCSER_TEMT : 0;
clk_en(port, 0);
return ret;
}
static void msm_hsl_break_ctl(struct uart_port *port, int break_ctl)
{
clk_en(port, 1);
if (break_ctl)
msm_hsl_write(port, START_BREAK, UARTDM_CR_ADDR);
else
msm_hsl_write(port, STOP_BREAK, UARTDM_CR_ADDR);
clk_en(port, 0);
}
static unsigned int msm_hsl_tx_empty_cir(struct uart_port *port)
{
unsigned int vid = UART_TO_MSM(port)->ver_id;
unsigned int ret;
pr_info("%s ():port->line %d, ir\n", __func__, port->line);
clk_en(port, 1);
ret = (msm_hsl_read(port, regmap[vid][UARTDM_SR]) &
UARTDM_SR_TXEMT_BMSK) ? TIOCSER_TEMT : 0;
clk_en(port, 0);
return ret;
}
static void msm_hsl_enable_ms_cir(struct uart_port *port)
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
clk_en(port, 1);
pr_info("%s () :port->line %d, ir\n", __func__, port->line);
msm_hsl_port->imr |= UARTDM_ISR_DELTA_CTS_BMSK;
msm_hsl_write(port, msm_hsl_port->imr,
regmap[msm_hsl_port->ver_id][UARTDM_IMR]);
clk_en(port, 0);
}
static void msm_hsl_start_tx_cir(struct uart_port *port)
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
clk_en(port, 1);
msm_hsl_port->imr |= UARTDM_ISR_TXLEV_BMSK;
msm_hsl_write(port, msm_hsl_port->imr,
regmap[msm_hsl_port->ver_id][UARTDM_IMR]);
clk_en(port, 0);
}
static void msm_hsl_stop_rx(struct uart_port *port)
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
clk_en(port, 1);
msm_hsl_port->imr &= ~(UARTDM_ISR_RXLEV_BMSK |
UARTDM_ISR_RXSTALE_BMSK);
msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
clk_en(port, 0);
}
static void msm_hsl_deinit_clock(struct uart_port *port)
{
#ifdef CONFIG_SERIAL_MSM_CLOCK_CONTROL
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
if (msm_hsl_port->clk_state != MSM_HSL_CLK_OFF)
clk_en(port, 0);
msm_hsl_port->clk_state = MSM_HSL_CLK_PORT_OFF;
#else
clk_en(port, 0);
#endif
}
static void msm_hsl_stop_rx_cir(struct uart_port *port)
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
clk_en(port, 1);
pr_info("%s () :port->line %d, ir\n", __func__, port->line);
msm_hsl_port->imr &= ~(UARTDM_ISR_RXLEV_BMSK |
UARTDM_ISR_RXSTALE_BMSK);
msm_hsl_write(port, msm_hsl_port->imr,
regmap[msm_hsl_port->ver_id][UARTDM_IMR]);
clk_en(port, 0);
}
static void msm_hsl_break_ctl_cir(struct uart_port *port, int break_ctl)
{
unsigned int vid = UART_TO_MSM(port)->ver_id;
clk_en(port, 1);
if (break_ctl) {
msm_hsl_write(port, START_BREAK, regmap[vid][UARTDM_CR]);
pr_info("%s ()break_ctl = 1:port->line %d, ir\n", __func__, port->line);
} else {
msm_hsl_write(port, STOP_BREAK, regmap[vid][UARTDM_CR]);
pr_info("%s ()break_ctl = 0:port->line %d, ir\n", __func__, port->line);
}
clk_en(port, 0);
}
void enable_irda(int irda_en)
{
struct msm_hsl_port *msm_irda_port = htc_irda_port;
struct uart_port *port = &(msm_irda_port->uart);
unsigned long flags;
int ret = 0;
D("%s(): irda msm_irda_port->, irda_en %d\n",
__func__, irda_en);
ret = clk_set_rate(msm_irda_port->clk, 7372800);
if (!ret) {
clk_en(port, 1);
D("%s(): irda+ Clock enabled for line(%d)\n", __func__, port->line);
} else {
E("%s():irda Error: Setting the clock rate\n", __func__);
return;
}
if (irda_en) {
D("%s(): irda+ turn on IRDA\n", __func__);
spin_lock_irqsave(&port->lock, flags);
ret = 1;
ret |= (int)irda_en;
msm_hsl_write(port, ret, UARTDM_IRDA_ADDR);
spin_unlock_irqrestore(&port->lock, flags);
if (msm_irda_port->irda_enable)
msm_irda_port->irda_enable(1);
else
E("no irda enable callback function");
} else {
D("%s(): irda+ turn off IRDA \n", __func__);
#if 0
spin_lock_irqsave(&port->lock, flags);
ret = 0;
msm_hsl_write(port, ret, UARTDM_IRDA_ADDR);
spin_unlock_irqrestore(&port->lock, flags);
#endif
if (msm_irda_port->irda_enable)
msm_irda_port->irda_enable(0);
else
E("no irda enable callback function");
}
clk_en(port, 0);
D("%s(): irda+ Clock enabled for line(%d)\n", __func__, port->line);
}
static void msm_hsl_power(struct uart_port *port, unsigned int state,
unsigned int oldstate)
{
#ifndef CONFIG_SERIAL_MSM_HSL_CLOCK_CONTROL
switch (state) {
case 0:
clk_en(port, 1);
break;
case 3:
clk_en(port, 0);
break;
default:
printk(KERN_ERR "msm_serial_hsl: Unknown PM state %d\n", state);
}
#endif
}
static void msm_hsl_init_clock(struct uart_port *port)
{
clk_en(port, 1);
#ifdef CONFIG_SERIAL_MSM_CLOCK_CONTROL
msm_hsl_port->clk_state = MSM_HSL_CLK_ON;
#endif
}
static void msm_hsl_start_tx(struct uart_port *port)
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
struct circ_buf *xmit = &port->state->xmit;
if(b_terminal_onoff == 0 && console_uart_port && (port == console_uart_port)){
uart_circ_clear(xmit);
return;
}
clk_en(port, 1);
msm_hsl_port->imr |= UARTDM_ISR_TXLEV_BMSK;
msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
clk_en(port, 0);
}
static void msm_hsl_shutdown(struct uart_port *port)
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
clk_en(port, 1);
msm_hsl_port->imr = 0;
msm_hsl_write(port, 0, UARTDM_IMR_ADDR); /* disable interrupts */
clk_en(port, 0);
free_irq(port->irq, port);
#ifndef CONFIG_PM_RUNTIME
msm_hsl_deinit_clock(port);
#endif
pm_runtime_put_sync(port->dev);
}
static void msm_hsl_init_clock(struct uart_port *port)
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port); // [email protected] (GS1 Team)
clk_en(port, 1);
#ifdef CONFIG_SERIAL_MSM_CLOCK_CONTROL
msm_hsl_port->clk_state = MSM_HSL_CLK_ON;
#endif
}
static ssize_t enable_cir_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct msm_hsl_port *msm_cir_port = htc_cir_port;
struct uart_port *port = &(msm_cir_port->uart);
unsigned long flags;
int cir_en, ret = 0;
sscanf(buf, "%d", &cir_en);
if (cir_en != 1 && cir_en != 3 && cir_en != 0)
D("%s: parameter invalid. cir_en = %d", __func__, cir_en);
D("%s: (cir_enable_flg, cir_en) = (%d, %d)\n",
__func__, cir_enable_flg, cir_en);
ret = clk_set_rate(msm_cir_port->clk, 7372800);
if (!ret) {
clk_en(port, 1);
D("%s(): irda Clock enabled for line(%d)\n", __func__, port->line);
} else {
D("%s(): Error: Setting the clock rate\n", __func__);
return -EINVAL;
}
if (cir_en > 1) {
D("%s(): Set IRDA mode\n", __func__);
spin_lock_irqsave(&port->lock, flags);
ret = 1;
ret |= (int)cir_en;
msm_hsl_write(port, ret, UARTDM_IRDA_ADDR);
spin_unlock_irqrestore(&port->lock, flags);
cir_enable_flg = PATH_IRDA;
if (msm_cir_port->cir_set_path)
msm_cir_port->cir_set_path(PATH_IRDA);
}
clk_en(port, 0);
return count;
}
static irqreturn_t msm_hsl_irq(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
unsigned int vid;
unsigned int misr;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
clk_en(port, 1);
vid = msm_hsl_port->ver_id;
misr = msm_hsl_read(port, regmap[vid][UARTDM_MISR]);
msm_hsl_write(port, 0, regmap[vid][UARTDM_IMR]);
if (misr & (UARTDM_ISR_RXSTALE_BMSK | UARTDM_ISR_RXLEV_BMSK)) {
handle_rx(port, misr);
if (misr & (UARTDM_ISR_RXSTALE_BMSK)) {
msm_hsl_write(port, RESET_STALE_INT,
regmap[vid][UARTDM_CR]);
}
msm_hsl_write(port, 6500, regmap[vid][UARTDM_DMRX]);
msm_hsl_write(port, STALE_EVENT_ENABLE, regmap[vid][UARTDM_CR]);
}
if (misr & UARTDM_ISR_TXLEV_BMSK)
handle_tx(port);
if (misr & UARTDM_ISR_DELTA_CTS_BMSK)
handle_delta_cts(port);
msm_hsl_write(port, msm_hsl_port->imr, regmap[vid][UARTDM_IMR]);
clk_en(port, 0);
spin_unlock_irqrestore(&port->lock, flags);
return IRQ_HANDLED;
}
static void msm_hsl_set_mctrl_cir(struct uart_port *port, unsigned int mctrl)
{
unsigned int vid = UART_TO_MSM(port)->ver_id;
unsigned int mr;
unsigned int loop_mode;
clk_en(port, 1);
mr = msm_hsl_read(port, regmap[vid][UARTDM_MR1]);
if (!(mctrl & TIOCM_RTS)) {
pr_info("%s ()mctrl & TIOCM_RTS:port->line %d, ir\n", __func__, port->line);
mr &= ~UARTDM_MR1_RX_RDY_CTL_BMSK;
msm_hsl_write(port, mr, regmap[vid][UARTDM_MR1]);
msm_hsl_write(port, RFR_HIGH, regmap[vid][UARTDM_CR]);
} else {
mr |= UARTDM_MR1_RX_RDY_CTL_BMSK;
msm_hsl_write(port, mr, regmap[vid][UARTDM_MR1]);
pr_info("%s () TIOCM_RTS:port->line %d, ir\n", __func__, port->line);
}
loop_mode = TIOCM_LOOP & mctrl;
if (loop_mode) {
pr_info("%s ()loop_mode:port->line %d, ir\n", __func__, port->line);
mr = msm_hsl_read(port, regmap[vid][UARTDM_MR2]);
mr |= UARTDM_MR2_LOOP_MODE_BMSK;
msm_hsl_write(port, mr, regmap[vid][UARTDM_MR2]);
msm_hsl_reset(port);
msm_hsl_write(port, UARTDM_CR_RX_EN_BMSK
| UARTDM_CR_TX_EN_BMSK, regmap[vid][UARTDM_CR]);
}
clk_en(port, 0);
}
static void msm_hsl_shutdown_cir(struct uart_port *port)
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
clk_en(port, 1);
pr_info("%s () :port->line %d, ir\n", __func__, port->line);
msm_hsl_port->imr = 0;
msm_hsl_write(port, 0, regmap[msm_hsl_port->ver_id][UARTDM_IMR]);
clk_en(port, 0);
free_irq(port->irq, port);
#ifndef CONFIG_PM_RUNTIME
msm_hsl_deinit_clock(port);
#endif
pm_runtime_put_sync(port->dev);
if (!(is_console(port)) || (!port->cons) ||
(port->cons && (!(port->cons->flags & CON_ENABLED)))) {
pr_info("%s () is_console:port->line %d, ir\n", __func__, port->line);
}
}
static int msm_hsl_loopback_enable_get(void *data, u64 *val)
{
struct msm_hsl_port *msm_hsl_port = data;
struct uart_port *port = &(msm_hsl_port->uart);
unsigned long flags;
int ret = 0;
ret = clk_set_rate(msm_hsl_port->clk, 7372800);
if (!ret)
clk_en(port, 1);
else {
pr_err("%s(): Error setting clk rate\n", __func__);
return -EINVAL;
}
spin_lock_irqsave(&port->lock, flags);
ret = msm_hsl_read(port, UARTDM_MR2_ADDR);
spin_unlock_irqrestore(&port->lock, flags);
clk_en(port, 0);
*val = (ret & UARTDM_MR2_LOOP_MODE_BMSK) ? 1 : 0;
return 0;
}
static void msm_hsl_power_cir(struct uart_port *port, unsigned int state,
unsigned int oldstate)
{
int ret;
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
unsigned long flags;
D("%s (): ir, state %d\n", __func__, state);
switch (state) {
case 0:
ret = clk_set_rate(msm_hsl_port->clk, 7372800);
if (ret)
E("%s(): Error setting UART clock rate\n",
__func__);
clk_en(port, 1);
break;
case 3:
if (cir_enable_flg != PATH_CIR) {
D("%s path is not CIR. flg = %d\n",
__func__, cir_enable_flg);
D("%s(): Clear IRDA mode \n", __func__);
spin_lock_irqsave(&port->lock, flags);
ret = 0;
msm_hsl_write(port, ret, UARTDM_IRDA_ADDR);
spin_unlock_irqrestore(&port->lock, flags);
cir_enable_flg = PATH_CIR;
if (msm_hsl_port->cir_set_path)
msm_hsl_port->cir_set_path(PATH_CIR);
}
clk_en(port, 0);
break;
default:
E("%s(): msm_serial_hsl: Unknown PM state %d\n",
__func__, state);
}
}
