void __init tegra2_init_timer(u32 *offset, int *irq) { unsigned long rate = clk_measure_input_freq(); int ret; switch (rate) { case 12000000: timer_writel(0x000b, TIMERUS_USEC_CFG); break; case 13000000: timer_writel(0x000c, TIMERUS_USEC_CFG); break; case 19200000: timer_writel(0x045f, TIMERUS_USEC_CFG); break; case 26000000: timer_writel(0x0019, TIMERUS_USEC_CFG); break; default: WARN(1, "Unknown clock rate"); } #ifdef CONFIG_PM_SLEEP ret = setup_irq(tegra_lp2wake_irq.irq, &tegra_lp2wake_irq); if (ret) { pr_err("Failed to register LP2 timer IRQ: %d\n", ret); BUG(); } #endif *offset = TIMER3_OFFSET; *irq = INT_TMR3; }
/* clk_m functions */ static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c) { u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK; c->rate = clk_measure_input_freq(); switch (c->rate) { case 12000000: auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; break; case 13000000: auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ; break; case 19200000: auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ; break; case 26000000: auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ; break; default: pr_err("%s: Unexpected clock rate %ld", __func__, c->rate); BUG(); } clk_writel(auto_clock_control, OSC_CTRL); return c->rate; }
static void __init tegra_init_timer(void) { unsigned long rate = clk_measure_input_freq(); int ret; #ifdef CONFIG_HAVE_ARM_TWD twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600); #endif switch (rate) { case 12000000: timer_writel(0x000b, TIMERUS_USEC_CFG); break; case 13000000: timer_writel(0x000c, TIMERUS_USEC_CFG); break; case 19200000: timer_writel(0x045f, TIMERUS_USEC_CFG); break; case 26000000: timer_writel(0x0019, TIMERUS_USEC_CFG); break; default: WARN(1, "Unknown clock rate"); } if (clocksource_register_hz(&tegra_clocksource, 1000000)) { printk(KERN_ERR "Failed to register clocksource\n"); BUG(); } ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq); if (ret) { printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret); BUG(); } clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5); tegra_clockevent.max_delta_ns = clockevent_delta2ns(0x1fffffff, &tegra_clockevent); tegra_clockevent.min_delta_ns = clockevent_delta2ns(0x1, &tegra_clockevent); tegra_clockevent.cpumask = cpu_all_mask; tegra_clockevent.irq = tegra_timer_irq.irq; clockevents_register_device(&tegra_clockevent); return; }
void __init tegra3_init_timer(u32 *offset, int *irq) { unsigned long rate = clk_measure_input_freq(); switch (rate) { case 12000000: timer_writel(0x000b, TIMERUS_USEC_CFG); break; case 13000000: timer_writel(0x000c, TIMERUS_USEC_CFG); break; case 19200000: timer_writel(0x045f, TIMERUS_USEC_CFG); break; case 26000000: timer_writel(0x0019, TIMERUS_USEC_CFG); break; case 16800000: timer_writel(0x0453, TIMERUS_USEC_CFG); break; case 38400000: timer_writel(0x04BF, TIMERUS_USEC_CFG); break; case 48000000: timer_writel(0x002F, TIMERUS_USEC_CFG); break; default: WARN(1, "Unknown clock rate"); } #ifdef CONFIG_PM_SLEEP #ifdef CONFIG_SMP /* For T30.A01 use INT_TMR_SHARED instead of INT_TMR6 for CPU3. */ if ((tegra_get_chipid() == TEGRA_CHIPID_TEGRA3) && (tegra_get_revision() == TEGRA_REVISION_A01)) tegra_lp2wake_irq[3].irq = INT_TMR_SHARED; #endif tegra3_register_wake_timer(0); #endif *offset = TIMER1_OFFSET; *irq = INT_TMR1; }
static void __init tegra_init_timer(void) { struct clk *clk; unsigned long rate = clk_measure_input_freq(); int ret; clk = clk_get_sys("timer", NULL); BUG_ON(IS_ERR(clk)); clk_enable(clk); /* * rtc registers are used by read_persistent_clock, keep the rtc clock * enabled */ clk = clk_get_sys("rtc-tegra", NULL); BUG_ON(IS_ERR(clk)); clk_enable(clk); #ifdef CONFIG_HAVE_ARM_TWD twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600); #endif switch (rate) { case 12000000: timer_writel(0x000b, TIMERUS_USEC_CFG); break; case 13000000: timer_writel(0x000c, TIMERUS_USEC_CFG); break; case 19200000: timer_writel(0x045f, TIMERUS_USEC_CFG); break; case 26000000: timer_writel(0x0019, TIMERUS_USEC_CFG); break; default: WARN(1, "Unknown clock rate"); } init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32, 1000000, SC_MULT, SC_SHIFT); if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) { printk(KERN_ERR "Failed to register clocksource\n"); BUG(); } ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq); if (ret) { printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret); BUG(); } clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5); tegra_clockevent.max_delta_ns = clockevent_delta2ns(0x1fffffff, &tegra_clockevent); tegra_clockevent.min_delta_ns = clockevent_delta2ns(0x1, &tegra_clockevent); tegra_clockevent.cpumask = cpu_all_mask; tegra_clockevent.irq = tegra_timer_irq.irq; clockevents_register_device(&tegra_clockevent); }