static int mddi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
#ifdef ENABLE_FWD_LINK_SKEW_CALIBRATION
mddi_host_type host_idx = MDDI_HOST_PRIM;
u32 stat_reg;
#endif
mfd = platform_get_drvdata(pdev);
pmdh_clk_enable();
pm_runtime_get(&pdev->dev);
if (mddi_pdata && mddi_pdata->mddi_power_save)
mddi_pdata->mddi_power_save(1);
pmdh_clk_enable();
#ifdef ENABLE_FWD_LINK_SKEW_CALIBRATION
if (mddi_client_type < 2) {
/* For skew calibration, clock should be less than 50MHz */
if (!clk_set_min_rate(mddi_clk, 49000000)) {
stat_reg = mddi_host_reg_in(STAT);
printk(KERN_DEBUG "\n stat_reg = 0x%x", stat_reg);
mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE);
if (stat_reg & (0x1 << 4))
mddi_host_reg_out(CMD, MDDI_CMD_LINK_ACTIVE);
mddi_host_reg_out(CMD, MDDI_CMD_SEND_RTD);
mddi_send_fw_link_skew_cal(host_idx);
mddi_host_reg_out(CMD, MDDI_CMD_SEND_RTD);
mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE | 1);
} else {
printk(KERN_ERR "%s: clk_set_min_rate failed\n",
__func__);
}
}
#endif
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
if (mddi_pdata &&
mddi_pdata->mddi_sel_clk &&
mddi_pdata->mddi_sel_clk(&clk_rate))
printk(KERN_ERR
"%s: can't select mddi io clk targate rate = %d\n",
__func__, clk_rate);
if (clk_set_min_rate(mddi_clk, clk_rate) < 0)
printk(KERN_ERR "%s: clk_set_min_rate failed\n",
__func__);
ret = panel_next_on(pdev);
return ret;
}
void mddi_disable(int lock)
{
mddi_host_type host_idx = MDDI_HOST_PRIM;
if (mddi_power_locked)
return;
if (lock)
mddi_power_locked = 1;
if (mddi_host_timer.function)
del_timer_sync(&mddi_host_timer);
mddi_pad_ctrl = mddi_host_reg_in(PAD_CTL);
mddi_host_reg_out(PAD_CTL, 0x0);
if (clk_set_min_rate(mddi_clk, 0) < 0)
printk(KERN_ERR "%s: clk_set_min_rate failed\n", __func__);
clk_disable(mddi_clk);
if (mddi_pclk)
clk_disable(mddi_pclk);
disable_irq(INT_MDDI_PRI);
if (mddi_pdata && mddi_pdata->mddi_power_save)
mddi_pdata->mddi_power_save(0);
}
static int lcdc_on(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
unsigned long panel_pixclock_freq = 0;
#ifndef CONFIG_MSM_BUS_SCALING
unsigned long pm_qos_rate;
#endif
mfd = platform_get_drvdata(pdev);
if (lcdc_pdata && lcdc_pdata->lcdc_get_clk)
panel_pixclock_freq = lcdc_pdata->lcdc_get_clk();
if (!panel_pixclock_freq)
panel_pixclock_freq = mfd->fbi->var.pixclock;
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(2);
#else
if (panel_pixclock_freq > 65000000)
/* pm_qos_rate should be in Khz */
pm_qos_rate = panel_pixclock_freq / 1000 ;
else
pm_qos_rate = 65000;
if (mfd->ebi1_clk) {
if (mdp_rev == MDP_REV_303) {
if (clk_set_min_rate(mfd->ebi1_clk, 65000000))
pr_err("%s: ebi1_lcdc_clk set rate failed\n",
__func__);
} else {
clk_set_rate(mfd->ebi1_clk, pm_qos_rate * 1000);
}
clk_enable(mfd->ebi1_clk);
}
#endif
mfd = platform_get_drvdata(pdev);
mfd->fbi->var.pixclock = clk_round_rate(pixel_mdp_clk,
mfd->fbi->var.pixclock);
ret = clk_set_rate(pixel_mdp_clk, mfd->fbi->var.pixclock);
if (ret) {
pr_err("%s: Can't set MDP LCDC pixel clock to rate %u\n",
__func__, mfd->fbi->var.pixclock);
goto out;
}
clk_enable(pixel_mdp_clk);
clk_enable(pixel_lcdc_clk);
if (lcdc_pdata && lcdc_pdata->lcdc_power_save)
lcdc_pdata->lcdc_power_save(1);
if (lcdc_pdata && lcdc_pdata->lcdc_gpio_config)
ret = lcdc_pdata->lcdc_gpio_config(1);
ret = panel_next_on(pdev);
out:
return ret;
}
void mipi_dsi_clk_enable(void)
{
unsigned data = 0;
if (mipi_dsi_clk_on) {
pr_err("%s: mipi_dsi_clk already ON\n", __func__);
return;
}
mipi_dsi_clk_on = 1;
if (clk_set_min_rate(ebi1_dsi_clk, 65000000)) /* 65 MHz */
pr_err("%s: ebi1_dsi_clk set rate failed\n", __func__);
clk_enable(ebi1_dsi_clk);
clk_enable(dsi_ref_clk);
clk_set_rate(dsi_byte_div_clk, data);
clk_set_rate(dsi_esc_clk, data);
clk_enable(mdp_dsi_pclk);
clk_enable(ahb_m_clk);
clk_enable(ahb_s_clk);
clk_enable(dsi_byte_div_clk);
clk_enable(dsi_esc_clk);
mipi_dsi_pclk_ctrl(&dsi_pclk, 1);
mipi_dsi_clk_ctrl(&dsicore_clk, 1);
}
static int mddi_ext_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
mfd = platform_get_drvdata(pdev);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
if (mddi_ext_pdata &&
mddi_ext_pdata->mddi_sel_clk &&
mddi_ext_pdata->mddi_sel_clk(&clk_rate))
printk(KERN_ERR
"%s: can't select mddi io clk targate rate = %d\n",
__func__, clk_rate);
if (clk_set_min_rate(mddi_ext_clk, clk_rate) < 0)
printk(KERN_ERR "%s: clk_set_min_rate failed\n",
__func__);
mddi_host_start_ext_display();
ret = panel_next_on(pdev);
return ret;
}
static int mddi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
mfd = platform_get_drvdata(pdev);
pm_runtime_get(&pdev->dev);
if (mddi_pdata && mddi_pdata->mddi_power_save)
mddi_pdata->mddi_power_save(1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
if (mddi_pdata &&
mddi_pdata->mddi_sel_clk &&
mddi_pdata->mddi_sel_clk(&clk_rate))
printk(KERN_ERR
"%s: can't select mddi io clk targate rate = %d\n",
__func__, clk_rate);
if (clk_set_min_rate(mddi_clk, clk_rate) < 0)
printk(KERN_ERR "%s: clk_set_min_rate failed\n",
__func__);
pm_qos_update_request(mfd->pm_qos_req, 65000);
ret = panel_next_on(pdev);
return ret;
}
static int mddi_on(struct platform_device *pdev)
{
int ret = 0;
u32 clk_rate;
struct msm_fb_data_type *mfd;
mfd = platform_get_drvdata(pdev);
if (machine_is_msm7201a_ffa())
gpio_direction_output(88, 1);
clk_rate = mfd->fbi->var.pixclock;
clk_rate = min(clk_rate, mfd->panel_info.clk_max);
if (mddi_pdata &&
mddi_pdata->mddi_sel_clk &&
mddi_pdata->mddi_sel_clk(&clk_rate))
printk(KERN_ERR
"%s: can't select mddi io clk targate rate = %d\n",
__func__, clk_rate);
if (clk_set_min_rate(mddi_clk, clk_rate) < 0)
printk(KERN_ERR "%s: clk_set_min_rate failed\n",
__func__);
ret = panel_next_on(pdev);
return ret;
}
static int __init mddi_driver_init(void)
{
int ret;
pmdh_clk_status = 0;
mddi_clk = clk_get(NULL, "mddi_clk");
if (IS_ERR(mddi_clk)) {
printk(KERN_ERR "can't find mddi_clk\n");
return PTR_ERR(mddi_clk);
}
ret = clk_set_min_rate(mddi_clk, 49000000);
if (ret)
printk(KERN_ERR "Can't set mddi_clk min rate to 49000000\n");
printk(KERN_INFO "mddi_clk init rate is %lu\n",
clk_get_rate(mddi_clk));
mddi_pclk = clk_get(NULL, "mddi_pclk");
if (IS_ERR(mddi_pclk))
mddi_pclk = NULL;
pmdh_clk_enable();
ret = mddi_register_driver();
if (ret) {
pmdh_clk_disable();
clk_put(mddi_clk);
if (mddi_pclk)
clk_put(mddi_pclk);
printk(KERN_ERR "mddi_register_driver() failed!\n");
return ret;
}
mddi_init();
return ret;
}
static int lcdc_off(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
mfd = platform_get_drvdata(pdev);
ret = panel_next_off(pdev);
clk_disable(pixel_mdp_clk);
clk_disable(pixel_lcdc_clk);
if (lcdc_pdata && lcdc_pdata->lcdc_power_save)
lcdc_pdata->lcdc_power_save(0);
if (lcdc_pdata && lcdc_pdata->lcdc_gpio_config)
ret = lcdc_pdata->lcdc_gpio_config(0);
#ifndef CONFIG_MSM_BUS_SCALING
if (mfd->ebi1_clk) {
if (mdp_rev == MDP_REV_303) {
if (clk_set_min_rate(mfd->ebi1_clk, 0))
pr_err("%s: ebi1_lcdc_clk set rate failed\n",
__func__);
}
clk_disable(mfd->ebi1_clk);
}
#else
mdp_bus_scale_update_request(0);
#endif
return ret;
}
int msm_gemini_platform_clk_enable(void)
{
/* MP*fps*(1 + %blanking)
2MP: 24MHz ------ 2 x 10 x 1.2
3MP: 36MHz ------ 3 x 10 x 1.2
5MP: 60MHz ------ 5 x 10 x 1.2
8MP: 96MHz ------ 8 x 10 x 1.2
12MP: 144MHz ------12 x 10 x 1.2
*/
int rc = -1;
u32 rate = 144000000;
if (jpeg_clk == NULL) {
jpeg_clk = clk_get(NULL, "jpeg_clk");
if (jpeg_clk == NULL) {
GMN_PR_ERR("%s:%d] fail rc = %d\n", __func__, __LINE__,
rc);
goto fail;
}
}
rc = clk_set_min_rate(jpeg_clk, rate);
if (rc) {
GMN_PR_ERR("%s:%d] fail rc = %d\n", __func__, __LINE__, rc);
goto fail;
}
rc = clk_enable(jpeg_clk);
if (rc) {
GMN_PR_ERR("%s:%d] fail rc = %d\n", __func__, __LINE__, rc);
goto fail;
}
if (jpeg_pclk == NULL) {
jpeg_pclk = clk_get(NULL, "jpeg_pclk");
if (jpeg_pclk == NULL) {
GMN_PR_ERR("%s:%d] fail rc = %d\n", __func__, __LINE__,
rc);
goto fail;
}
}
rc = clk_enable(jpeg_pclk);
if (rc) {
GMN_PR_ERR("%s:%d] fail rc = %d\n", __func__, __LINE__, rc);
goto fail;
}
/* Need to add PM QOS bus requirement once updated */
GMN_DBG("%s:%d]\n", __func__, __LINE__);
return rc;
fail:
GMN_PR_ERR("%s:%d] fail rc = %d\n", __func__, __LINE__, rc);
return rc;
}
static int mddi_ext_suspend(struct platform_device *pdev, pm_message_t state)
{
if (mddi_ext_is_in_suspend)
return 0;
mddi_ext_is_in_suspend = 1;
if (clk_set_min_rate(mddi_ext_clk, 0) < 0)
printk(KERN_ERR "%s: clk_set_min_rate failed\n", __func__);
clk_disable(mddi_ext_clk);
disable_irq(INT_MDDI_EXT);
return 0;
}
static int clock_debug_rate_set(void *data, u64 val)
{
struct clk *clock = data;
int ret;
/* Only increases to max rate will succeed, but that's actually good
* for debugging purposes so we don't check for error. */
if (clock->flags & CLK_MAX)
clk_set_max_rate(clock, val);
if (clock->flags & CLK_MIN)
ret = clk_set_min_rate(clock, val);
else
ret = clk_set_rate(clock, val);
if (ret != 0)
printk(KERN_ERR "clk_set%s_rate failed (%d)\n",
(clock->flags & CLK_MIN) ? "_min" : "", ret);
return ret;
}
void mddi_disable(int lock)
{
mddi_host_type host_idx = MDDI_HOST_PRIM;
if (mddi_power_locked)
return;
if (lock)
mddi_power_locked = 1;
pmdh_clk_enable();
mddi_pad_ctrl = mddi_host_reg_in(PAD_CTL);
mddi_host_reg_out(PAD_CTL, 0x0);
if (clk_set_min_rate(mddi_clk, 0) < 0)
printk(KERN_ERR "%s: clk_set_min_rate failed\n", __func__);
pmdh_clk_disable();
if (mddi_pdata && mddi_pdata->mddi_power_save)
mddi_pdata->mddi_power_save(0);
}
void mddi_disable(int lock)
{
mddi_host_type host_idx = MDDI_HOST_PRIM;
if (mddi_power_locked)
return;
if (lock)
mddi_power_locked = 1;
if (mddi_host_timer.function)
del_timer_sync(&mddi_host_timer);
mddi_pad_ctrl = mddi_host_reg_in(PAD_CTL);
mddi_host_reg_out(PAD_CTL, 0x0);
if (clk_set_min_rate(mddi_clk, 0) < 0)
printk(KERN_ERR "%s: clk_set_min_rate failed\n", __func__);
clk_disable(mddi_clk);
if (mddi_pclk)
clk_disable(mddi_pclk);
#ifdef CONFIG_SHLCDC_BOARD
pm_qos_update_requirement(PM_QOS_SYSTEM_BUS_FREQ, "mddi",
PM_QOS_DEFAULT_VALUE);
#endif
disable_irq(INT_MDDI_PRI);
if (mddi_pdata && mddi_pdata->mddi_power_save)
mddi_pdata->mddi_power_save(0);
#ifdef CONFIG_SHLCDC_BOARD
if (no_set_power_flag == FALSE) {
shlcdc_api_set_power_mode(SHLCDC_DEV_TYPE_MDDI, SHLCDC_DEV_PWR_OFF);
}
#endif
}
void mipi_dsi_clk_disable(void)
{
if (mipi_dsi_clk_on == 0) {
pr_err("%s: mipi_dsi_clk already OFF\n", __func__);
return;
}
mipi_dsi_clk_on = 0;
MIPI_OUTP(MIPI_DSI_BASE + 0x0118, 0);
mipi_dsi_pclk_ctrl(&dsi_pclk, 0);
mipi_dsi_clk_ctrl(&dsicore_clk, 0);
clk_disable(dsi_esc_clk);
clk_disable(dsi_byte_div_clk);
clk_disable(mdp_dsi_pclk);
clk_disable(ahb_m_clk);
clk_disable(ahb_s_clk);
clk_disable(dsi_ref_clk);
if (clk_set_min_rate(ebi1_dsi_clk, 0))
pr_err("%s: ebi1_dsi_clk set rate failed\n", __func__);
clk_disable(ebi1_dsi_clk);
}
static int mddi_suspend(struct platform_device *pdev, pm_message_t state)
{
mddi_host_type host_idx = MDDI_HOST_PRIM;
if (mddi_is_in_suspend)
return 0;
mddi_is_in_suspend = 1;
if (mddi_power_locked)
return 0;
pmdh_clk_enable();
mddi_pad_ctrl = mddi_host_reg_in(PAD_CTL);
mddi_host_reg_out(PAD_CTL, 0x0);
if (clk_set_min_rate(mddi_clk, 0) < 0)
printk(KERN_ERR "%s: clk_set_min_rate failed\n", __func__);
pmdh_clk_disable();
return 0;
}
int msm_camio_jpeg_clk_enable(void)
{
/* MP*fps*(1 + %blanking)
2MP: 24MHz ------ 2 x 10 x 1.2
3MP: 36MHz ------ 3 x 10 x 1.2
5MP: 60MHz ------ 5 x 10 x 1.2
8MP: 96MHz ------ 8 x 10 x 1.2
12MP: 144MHz ------12 x 10 x 1.2
*/
int rc = -1;
u32 rate = 144000000;
if (jpeg_clk == NULL) {
jpeg_clk = clk_get(NULL, "jpeg_clk");
if (jpeg_clk == NULL) {
pr_err("[CAM] %s:%d] fail rc = %d\n", __func__, __LINE__,
rc);
goto fail;
}
}
rc = clk_set_min_rate(jpeg_clk, rate);
if (rc) {
pr_err("[CAM] %s:%d] fail rc = %d\n", __func__, __LINE__, rc);
goto fail;
}
rc = clk_enable(jpeg_clk);
if (rc) {
pr_err("[CAM] %s:%d] fail rc = %d\n", __func__, __LINE__, rc);
goto fail;
}
if (jpeg_pclk == NULL) {
jpeg_pclk = clk_get(NULL, "jpeg_pclk");
if (jpeg_pclk == NULL) {
pr_err("[CAM] %s:%d] fail rc = %d\n", __func__, __LINE__,
rc);
goto fail;
}
}
rc = clk_enable(jpeg_pclk);
if (rc) {
pr_err("[CAM] %s:%d] fail rc = %d\n", __func__, __LINE__, rc);
goto fail;
}
/*rc = pm_qos_add_requirement(PM_QOS_SYSTEM_BUS_FREQ,
"msm_gemini", MSM_SYSTEM_BUS_RATE);
if (rc) {
GMN_PR_ERR("request AXI bus QOS fails. rc = %d\n", rc);
goto fail;
}*/
return rc;
fail:
pr_err("[CAM] %s:%d] fail rc = %d\n", __func__, __LINE__, rc);
return rc;
}
int msm_camio_clk_enable(enum msm_camio_clk_type clktype)
{
int rc = 0;
struct clk *clk = NULL;
switch (clktype) {
case CAMIO_VFE_MDC_CLK:
pr_err("CLK Enable: CAMIO_VFE_MDC_CLK");
camio_vfe_mdc_clk =
clk = clk_get(NULL, "vfe_mdc_clk");
break;
case CAMIO_MDC_CLK:
pr_err("CLK Enable: CAMIO_MDC_CLK");
camio_mdc_clk =
clk = clk_get(NULL, "mdc_clk");
break;
case CAMIO_VFE_CLK:
pr_err("CLK Enable: CAMIO_VFE_CLK");
camio_vfe_clk =
clk = clk_get(NULL, "vfe_clk");
msm_camio_clk_rate_set_2(clk, camio_clk.vfe_clk_rate);
break;
case CAMIO_VFE_CAMIF_CLK:
pr_err("CLK Enable: CAMIO_VFE_CAMIF_CLK");
camio_vfe_camif_clk =
clk = clk_get(NULL, "vfe_camif_clk");
break;
case CAMIO_VFE_PBDG_CLK:
pr_err("CLK Enable: CAMIO_VFE_PBDG_CLK");
camio_vfe_pbdg_clk =
clk = clk_get(NULL, "vfe_pclk");
break;
case CAMIO_CAM_MCLK_CLK:
pr_err("CLK Enable: CAMIO_CAM_MCLK_CLK");
camio_cam_m_clk =
clk = clk_get(NULL, "cam_m_clk");
msm_camio_clk_rate_set_2(clk, camio_clk.mclk_clk_rate);
break;
case CAMIO_CAMIF_PAD_PBDG_CLK:
pr_err("CLK Enable: CAMIO_PAD_PBDG_CLK");
camio_camif_pad_pbdg_clk =
clk = clk_get(NULL, "camif_pad_pclk");
break;
case CAMIO_CSI0_CLK:
pr_err("CLK Enable: CAMIO_CSI0_CLK");
camio_csi_clk =
clk = clk_get(NULL, "csi_clk");
msm_camio_clk_rate_set_2(clk, 153600000);
break;
case CAMIO_CSI0_VFE_CLK:
pr_err("CLK Enable: CAMIO_VFE_CLK");
camio_csi_vfe_clk =
clk = clk_get(NULL, "csi_vfe_clk");
break;
case CAMIO_CSI0_PCLK:
pr_err("CLK Enable: CAMIO_CSI0_CLK");
camio_csi_pclk =
clk = clk_get(NULL, "csi_pclk");
break;
case CAMIO_JPEG_CLK:
pr_err("CLK Enable: CAMIO_JPEG_CLK");
camio_jpeg_clk =
clk = clk_get(NULL, "jpeg_clk");
clk_set_min_rate(clk, 144000000);
break;
case CAMIO_JPEG_PCLK:
pr_err("CLK Enable: CAMIO_JPEG_PCLK");
camio_jpeg_pclk =
clk = clk_get(NULL, "jpeg_pclk");
break;
case CAMIO_VPE_CLK:
pr_err("CLK Enable: CAMIO_VPE_CLK");
camio_vpe_clk =
clk = clk_get(NULL, "vpe_clk");
msm_camio_clk_set_min_rate(clk, 150000000);
break;
default:
pr_err("CLK Enable: NO DEFINED CLOCK (CLKTYPE: %d)", clktype);
break;
}
if (!IS_ERR(clk)) {
pr_err("CLK Enabled");
clk_enable(clk);
} else {
pr_err("CLK ERROR on check");
rc = -1;
}
return rc;
}
void msm_camio_clk_set_min_rate(struct clk *clk, int rate)
{
clk_set_min_rate(clk, rate);
}
int msm_camio_clk_enable(enum msm_camio_clk_type clktype)
{
int rc = 0;
struct clk *clk = NULL;
switch (clktype) {
case CAMIO_VFE_MDC_CLK:
camio_vfe_mdc_clk =
clk = clk_get(NULL, "vfe_mdc_clk");
break;
case CAMIO_MDC_CLK:
camio_mdc_clk =
clk = clk_get(NULL, "mdc_clk");
break;
case CAMIO_VFE_CLK:
camio_vfe_clk =
clk = clk_get(NULL, "vfe_clk");
msm_camio_clk_rate_set_2(clk, camio_clk.vfe_clk_rate);
break;
case CAMIO_VFE_CAMIF_CLK:
camio_vfe_camif_clk =
clk = clk_get(NULL, "vfe_camif_clk");
break;
case CAMIO_VFE_PBDG_CLK:
camio_vfe_pbdg_clk =
clk = clk_get(NULL, "vfe_pclk");
break;
case CAMIO_CAM_MCLK_CLK:
camio_cam_m_clk =
clk = clk_get(NULL, "cam_m_clk");
msm_camio_clk_rate_set_2(clk, camio_clk.mclk_clk_rate);
break;
case CAMIO_CAMIF_PAD_PBDG_CLK:
camio_camif_pad_pbdg_clk =
clk = clk_get(NULL, "camif_pad_pclk");
break;
case CAMIO_CSI0_CLK:
camio_csi_clk =
clk = clk_get(NULL, "csi_clk");
msm_camio_clk_rate_set_2(clk, 153600000);
break;
case CAMIO_CSI0_VFE_CLK:
camio_csi_vfe_clk =
clk = clk_get(NULL, "csi_vfe_clk");
break;
case CAMIO_CSI0_PCLK:
camio_csi_pclk =
clk = clk_get(NULL, "csi_pclk");
break;
case CAMIO_JPEG_CLK:
camio_jpeg_clk =
clk = clk_get(NULL, "jpeg_clk");
clk_set_min_rate(clk, 144000000);
break;
case CAMIO_JPEG_PCLK:
camio_jpeg_pclk =
clk = clk_get(NULL, "jpeg_pclk");
break;
case CAMIO_VPE_CLK:
camio_vpe_clk =
clk = clk_get(NULL, "vpe_clk");
msm_camio_clk_set_min_rate(clk, vpe_clk_rate);
break;
default:
break;
}
if (!IS_ERR(clk))
clk_enable(clk);
else
rc = -1;
return rc;
}
static int msm_iommu_probe(struct platform_device *pdev)
{
struct resource *r, *r2;
struct clk *iommu_clk = NULL;
struct clk *iommu_pclk = NULL;
struct msm_iommu_drvdata *drvdata;
struct msm_iommu_dev *iommu_dev = pdev->dev.platform_data;
void __iomem *regs_base;
resource_size_t len;
int ret, irq, par;
if (pdev->id == -1) {
msm_iommu_root_dev = pdev;
return 0;
}
drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
if (!drvdata) {
ret = -ENOMEM;
goto fail;
}
if (!iommu_dev) {
ret = -ENODEV;
goto fail;
}
iommu_pclk = clk_get(NULL, "smmu_pclk");
if (IS_ERR(iommu_pclk)) {
ret = -ENODEV;
goto fail;
}
ret = clk_enable(iommu_pclk);
if (ret)
goto fail_enable;
iommu_clk = clk_get(&pdev->dev, "iommu_clk");
if (!IS_ERR(iommu_clk)) {
if (clk_get_rate(iommu_clk) == 0)
clk_set_min_rate(iommu_clk, 1);
ret = clk_enable(iommu_clk);
if (ret) {
clk_put(iommu_clk);
goto fail_pclk;
}
} else
iommu_clk = NULL;
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "physbase");
if (!r) {
ret = -ENODEV;
goto fail_clk;
}
len = r->end - r->start + 1;
r2 = request_mem_region(r->start, len, r->name);
if (!r2) {
pr_err("Could not request memory region: start=%p, len=%d\n",
(void *) r->start, len);
ret = -EBUSY;
goto fail_clk;
}
regs_base = ioremap(r2->start, len);
if (!regs_base) {
pr_err("Could not ioremap: start=%p, len=%d\n",
(void *) r2->start, len);
ret = -EBUSY;
goto fail_mem;
}
irq = platform_get_irq_byname(pdev, "nonsecure_irq");
if (irq < 0) {
ret = -ENODEV;
goto fail_io;
}
msm_iommu_reset(regs_base, iommu_dev->ncb);
SET_M(regs_base, 0, 1);
SET_PAR(regs_base, 0, 0);
SET_V2PCFG(regs_base, 0, 1);
SET_V2PPR(regs_base, 0, 0);
mb();
par = GET_PAR(regs_base, 0);
SET_V2PCFG(regs_base, 0, 0);
SET_M(regs_base, 0, 0);
mb();
if (!par) {
pr_err("%s: Invalid PAR value detected\n", iommu_dev->name);
ret = -ENODEV;
goto fail_io;
}
ret = request_irq(irq, msm_iommu_fault_handler, 0,
"msm_iommu_secure_irpt_handler", drvdata);
if (ret) {
pr_err("Request IRQ %d failed with ret=%d\n", irq, ret);
goto fail_io;
}
drvdata->pclk = iommu_pclk;
drvdata->clk = iommu_clk;
drvdata->base = regs_base;
drvdata->irq = irq;
drvdata->ncb = iommu_dev->ncb;
drvdata->name = iommu_dev->name;
pr_info("device %s mapped at %p, irq %d with %d ctx banks\n",
iommu_dev->name, regs_base, irq, iommu_dev->ncb);
platform_set_drvdata(pdev, drvdata);
if (iommu_clk)
clk_disable(iommu_clk);
clk_disable(iommu_pclk);
return 0;
fail_io:
iounmap(regs_base);
fail_mem:
release_mem_region(r->start, len);
fail_clk:
if (iommu_clk) {
clk_disable(iommu_clk);
clk_put(iommu_clk);
}
fail_pclk:
clk_disable(iommu_pclk);
fail_enable:
clk_put(iommu_pclk);
fail:
kfree(drvdata);
return ret;
}
int msm_camio_clk_enable(enum msm_camio_clk_type clktype)
{
int rc = 0;
struct clk *clk = NULL;
switch (clktype) {
case CAMIO_CAM_MCLK_CLK:
camio_cam_clk =
clk = clk_get(NULL, "cam_clk");
msm_camio_clk_rate_set_2(clk, camio_clk.mclk_clk_rate);
break;
case CAMIO_VFE_CLK:
camio_vfe_clk =
clk = clk_get(NULL, "vfe_clk");
msm_camio_clk_rate_set_2(clk, camio_clk.vfe_clk_rate);
break;
case CAMIO_CSI0_VFE_CLK:
camio_csi0_vfe_clk =
clk = clk_get(NULL, "csi_vfe_clk");
break;
case CAMIO_CSI1_VFE_CLK:
camio_csi1_vfe_clk =
clk = clk_get(&camio_dev->dev, "csi_vfe_clk");
break;
case CAMIO_CSI_SRC_CLK:
camio_csi_src_clk =
clk = clk_get(NULL, "csi_src_clk");
msm_camio_clk_rate_set_2(clk, 384000000);
break;
case CAMIO_CSI0_CLK:
camio_csi0_clk =
clk = clk_get(NULL, "csi_clk");
break;
case CAMIO_CSI1_CLK:
camio_csi1_clk =
clk = clk_get(&camio_dev->dev, "csi_clk");
break;
case CAMIO_VFE_PCLK:
camio_vfe_pclk =
clk = clk_get(NULL, "vfe_pclk");
break;
case CAMIO_CSI0_PCLK:
camio_csi0_pclk =
clk = clk_get(NULL, "csi_pclk");
break;
case CAMIO_CSI1_PCLK:
camio_csi1_pclk =
clk = clk_get(&camio_dev->dev, "csi_pclk");
break;
case CAMIO_JPEG_CLK:
camio_jpeg_clk =
clk = clk_get(NULL, "ijpeg_clk");
clk_set_min_rate(clk, 144000000);
break;
case CAMIO_JPEG_PCLK:
camio_jpeg_pclk =
clk = clk_get(NULL, "ijpeg_pclk");
break;
case CAMIO_VPE_CLK:
camio_vpe_clk =
clk = clk_get(NULL, "vpe_clk");
msm_camio_clk_set_min_rate(clk, 160000000 ); //200000000);
break;
case CAMIO_VPE_PCLK:
camio_vpe_pclk =
clk = clk_get(NULL, "vpe_pclk");
break;
default:
break;
}
if (!IS_ERR(clk))
clk_enable(clk);
else
rc = -1;
return rc;
}
