void stm32_rcc_set_periph_clk_irq(
Stm32Rcc *s,
stm32_periph_t periph,
qemu_irq periph_irq)
{
Clk clk = s->PERIPHCLK[periph];
assert(clk != NULL);
clktree_adduser(clk, periph_irq);
}
/* Set up the clock tree */
static void stm32_rcc_init_clk(Stm32Rcc *s)
{
int i;
qemu_irq *hclk_upd_irq =
qemu_allocate_irqs(stm32_rcc_hclk_upd_irq_handler, s, 1);
Clk HSI_DIV2, HSE_DIV2;
/* Make sure all the peripheral clocks are null initially.
* This will be used for error checking to make sure
* an invalid clock is not referenced (not all of the
* indexes will be used).
*/
for(i = 0; i < STM32_PERIPH_COUNT; i++) {
s->PERIPHCLK[i] = NULL;
}
/* Initialize clocks */
/* Source clocks are initially disabled, which represents
* a disabled oscillator. Enabling the clock represents
* turning the clock on.
*/
s->HSICLK = clktree_create_src_clk("HSI", HSI_FREQ, false);
s->LSICLK = clktree_create_src_clk("LSI", LSI_FREQ, false);
s->HSECLK = clktree_create_src_clk("HSE", s->osc_freq, false);
s->LSECLK = clktree_create_src_clk("LSE", s->osc32_freq, false);
HSI_DIV2 = clktree_create_clk("HSI/2", 1, 2, true, CLKTREE_NO_MAX_FREQ, 0,
s->HSICLK, NULL);
HSE_DIV2 = clktree_create_clk("HSE/2", 1, 2, true, CLKTREE_NO_MAX_FREQ, 0,
s->HSECLK, NULL);
s->PLLXTPRECLK = clktree_create_clk("PLLXTPRE", 1, 1, true, CLKTREE_NO_MAX_FREQ, CLKTREE_NO_INPUT,
s->HSECLK, HSE_DIV2, NULL);
/* PLLCLK contains both the switch and the multiplier, which are shown as
* two separate components in the clock tree diagram.
*/
s->PLLCLK = clktree_create_clk("PLLCLK", 0, 1, false, 72000000, CLKTREE_NO_INPUT,
HSI_DIV2, s->PLLXTPRECLK, NULL);
s->SYSCLK = clktree_create_clk("SYSCLK", 1, 1, true, 72000000, CLKTREE_NO_INPUT,
s->HSICLK, s->HSECLK, s->PLLCLK, NULL);
s->HCLK = clktree_create_clk("HCLK", 0, 1, true, 72000000, 0,
s->SYSCLK, NULL);
clktree_adduser(s->HCLK, hclk_upd_irq[0]);
s->PCLK1 = clktree_create_clk("PCLK1", 0, 1, true, 36000000, 0,
s->HCLK, NULL);
s->PCLK2 = clktree_create_clk("PCLK2", 0, 1, true, 72000000, 0,
s->HCLK, NULL);
/* Peripheral clocks */
s->PERIPHCLK[STM32_GPIOA] = clktree_create_clk("GPIOA", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK2, NULL);
s->PERIPHCLK[STM32_GPIOB] = clktree_create_clk("GPIOB", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK2, NULL);
s->PERIPHCLK[STM32_GPIOC] = clktree_create_clk("GPIOC", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK2, NULL);
s->PERIPHCLK[STM32_GPIOD] = clktree_create_clk("GPIOD", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK2, NULL);
s->PERIPHCLK[STM32_GPIOE] = clktree_create_clk("GPIOE", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK2, NULL);
s->PERIPHCLK[STM32_GPIOF] = clktree_create_clk("GPIOF", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK2, NULL);
s->PERIPHCLK[STM32_GPIOG] = clktree_create_clk("GPIOG", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK2, NULL);
s->PERIPHCLK[STM32_AFIO] = clktree_create_clk("AFIO", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK2, NULL);
s->PERIPHCLK[STM32_UART1] = clktree_create_clk("UART1", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK2, NULL);
s->PERIPHCLK[STM32_UART2] = clktree_create_clk("UART2", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
s->PERIPHCLK[STM32_UART3] = clktree_create_clk("UART3", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
s->PERIPHCLK[STM32_UART4] = clktree_create_clk("UART4", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
s->PERIPHCLK[STM32_UART5] = clktree_create_clk("UART5", 1, 1, false, CLKTREE_NO_MAX_FREQ, 0, s->PCLK1, NULL);
}