/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
uint32_t reg = 0;
switch (freq) {
case MMC_CLK_400KHZ:
clock_config(SDC_CLK_NS_400KHZ,
SDC_CLK_MD_400KHZ,
SDC_NS(interface), SDC_MD(interface));
break;
case MMC_CLK_48MHZ:
case MMC_CLK_50MHZ: /* Max supported is 48MHZ */
clock_config(SDC_CLK_NS_48MHZ,
SDC_CLK_MD_48MHZ,
SDC_NS(interface), SDC_MD(interface));
break;
default:
ASSERT(0);
}
reg |= MMC_BOOT_MCI_CLK_ENABLE;
reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
writel(reg, MMC_BOOT_MCI_CLK);
}
static unsigned int msm_boot_uart_dm_config_clock(void)
{
unsigned int curr_value = 0;
/* Vote for PLL8 to be enabled */
curr_value = readl(MSM_BOOT_PLL_ENABLE_SC0);
curr_value |= (1 << 8);
writel(curr_value, MSM_BOOT_PLL_ENABLE_SC0);
/* Proceed only after PLL is enabled */
while (!(readl(MSM_BOOT_PLL8_STATUS) & (1<<16)));
/* PLL8 is enabled. Enable gsbi_uart_clk */
/* GSBI clock frequencies for UART protocol
* Operating mode gsbi_uart_clk
* UART up to 115.2 Kbps 1.8432 MHz
* UART up to 460.8 Kbps 7.3728 MHz
* UART up to 4 Mbit/s 64 MHz
*
* Choosing lowest supported value
* Rate (KHz) NS MD
* 3686400 0xFD940043 0x0006FD8E
*/
clock_config(0xFD940043, 0x0006FD8E,
MSM_BOOT_UART_DM_APPS_NS,
MSM_BOOT_UART_DM_APPS_MD);
/* Enable gsbi_pclk */
writel(0x10, MSM_BOOT_UART_DM_GSBI_HCLK_CTL);
return MSM_BOOT_UART_DM_E_SUCCESS;
}
/* Write the M,N,D values and enable the MMSS Clocks */
void config_mmss_clk(uint32_t ns,
uint32_t md,
uint32_t cc,
uint32_t ns_addr, uint32_t md_addr, uint32_t cc_addr)
{
unsigned int val = 0;
clock_config(ns, md, ns_addr, md_addr);
/* Enable MND counter */
val = cc | (1 << 5);
val = val | readl(cc_addr);
writel(val, cc_addr);
/* Enable the root of the clock tree */
val = 1 << 2;
val = val | readl(cc_addr);
writel(val, cc_addr);
/* Enable the Pixel Clock */
val = 1 << 0;
val = val | readl(cc_addr);
writel(val, cc_addr);
/* Force On */
val = 1 << 31;
val = val | readl(cc_addr);
writel(val, cc_addr);
}
int main(){
WDTCTL = WDTPW | WDTHOLD;
clock_config();
serial_config();
serial_print_string("ASCII TABLE:\n");
char strVal[4];
for(char i = ' '; i < 127; i++){
itoa(i, strVal, 10);
serial_print_string(strVal);
serial_print_string(": ");
serial_print_byte((char)i);
serial_print_byte('\n');
}
serial_print_byte('\n');
__enable_interrupt();
__bis_SR_register(LPM4_bits);
return 0;
}
void hsusb_clock_init(void)
{
/* Setup XCVR clock */
clock_config(USB_XCVR_CLK_NS_VAL,
USB_XCVR_CLK_MD_VAL,
USB_HS1_XCVR_FS_CLK_NS,
USB_HS1_XCVR_FS_CLK_MD);
}
/* Configure UART clock - based on the gsbi id */
void clock_config_uart_dm(uint8_t id)
{
/* Enable gsbi_uart_clk */
clock_config(UART_DM_CLK_NS_115200,
UART_DM_CLK_MD_115200,
GSBIn_UART_APPS_NS(id), GSBIn_UART_APPS_MD(id));
/* Enable gsbi_pclk */
writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id));
}
void hsusb_clock_init(void)
{
/* TODO: Enable pll8 here */
/* Setup USB AHB clock */
/* Setup XCVR clock */
clock_config(USB_XCVR_CLK_NS,
USB_XCVR_CLK_MD,
USB_HS1_XCVR_FS_CLK_NS, USB_HS1_XCVR_FS_CLK_MD);
}
// Main entry point
int
main(void)
{
SystemInit();
LL_Init1msTick(SystemCoreClock);
clock_config();
adc_config();
io_config();
spi_config();
sched_main();
return 0;
}
// 初始化系统时钟
void system_config_clk_init(void)
{
//clock_config(16); // 内部时钟16M
clock_config(8); // 内部时钟8M
#if 0
CLK_DeInit();
CLK_FastHaltWakeUpCmd(ENABLE);
CLK_HSECmd(DISABLE);
CLK_HSICmd(ENABLE);
CLK_SYSCLKConfig(CLK_PRESCALER_HSIDIV4);
#endif
}
/*
* main.c
*/
int main(void)
{
lcd_pin_init();
clock_config();
lcd_start();
while (1)
{
write_to_lcd();
delay_ms(1500);
}
return 0;
}
/* Configure UART clock - based on the gsbi id */
void clock_config_uart_dm(uint8_t id)
{
/* Enable gsbi_uart_clk */
clock_config(UART_DM_CLK_NS_115200,
UART_DM_CLK_MD_115200,
GSBIn_QUP_APPS_NS(id),
GSBIn_QUP_APPS_MD(id));
/* Configure clock selection register for tx and rx rates.
* Selecting 115.2k for both RX and TX.
*/
writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(id));
/* Enable gsbi_pclk */
writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id));
}
void system_init()
{
/* Stop the watchdog */
startup_watchdog_disable(); /* Do it right now, before it gets a chance to break in */
/* Note: Brown-Out detection must be powered to operate the ADC. adc_on() will power
* it back on if called after system_init() */
system_brown_out_detection_config(0);
system_set_default_power_state();
clock_config(SELECTED_FREQ);
set_pins(common_pins);
gpio_on();
/* System tick timer MUST be configured and running in order to use the sleeping
* functions */
systick_timer_on(1); /* 1ms */
systick_start();
}
/* Configure i2c clock */
void clock_config_i2c(uint8_t id, uint32_t freq)
{
uint32_t ns;
uint32_t md;
switch (freq) {
case 24000000:
ns = I2C_CLK_NS_24MHz;
md = I2C_CLK_MD_24MHz;
break;
default:
ASSERT(0);
}
clock_config(ns, md, GSBIn_QUP_APPS_NS(id), GSBIn_QUP_APPS_MD(id));
/* Enable the GSBI HCLK */
writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id));
}
/**
* @brief Function for main application entry.
*/
int main(void)
{
ret_code_t err_code;
char config;
APP_ERROR_CHECK(NRF_LOG_INIT(NULL));
bsp_board_leds_init();
err_code = clock_config();
APP_ERROR_CHECK(err_code);
APP_TIMER_INIT(APP_TIMER_PRESCALER, OP_QUEUES_SIZE, NULL);
NRF_LOG_INFO("Capacitive sensing driver example.\r\n");
csense_initialize();
NRF_LOG_INFO("Do you want to enter configuration mode to set thresholds?(y/n)\r\n");
NRF_LOG_FLUSH();
config = NRF_LOG_GETCHAR();
conf_mode = (config == 'y') ? true : false;
if (conf_mode)
{
configure_thresholds();
conf_mode = false;
}
NRF_LOG_INFO("Module ready.\r\n");
start_app_timer();
while (1)
{
NRF_LOG_FLUSH();
__WFI();
}
}
void
hal_bsp_init(void)
{
int rc;
(void)rc;
clock_config();
#if MYNEWT_VAL(UART_0)
rc = os_dev_create((struct os_dev *) &hal_uart0, "uart0",
OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&uart_cfg[0]);
assert(rc == 0);
#endif
#if MYNEWT_VAL(TIMER_0)
hal_timer_init(0, TIM9);
#endif
#if MYNEWT_VAL(TIMER_1)
hal_timer_init(1, TIM10);
#endif
#if MYNEWT_VAL(TIMER_2)
hal_timer_init(2, TIM11);
#endif
#if MYNEWT_VAL(SPI_1_MASTER)
rc = hal_spi_init(1, &spi1_cfg, HAL_SPI_TYPE_MASTER);
assert(rc == 0);
#endif
#if MYNEWT_VAL(SPI_1_SLAVE)
rc = hal_spi_init(1, &spi1_cfg, HAL_SPI_TYPE_SLAVE);
assert(rc == 0);
#endif
#if MYNEWT_VAL(I2C_0)
rc = hal_i2c_init(0, &i2c_cfg0);
assert(rc == 0);
#endif
}
int main(void)
{
clock_config();
gpio_init();
timer_init();
TIM2->CR1 |=(1<<0) ;
while(1)
{
//led on
GPIOD->ODR |= (1<<12)
// wait until UIF flag is set
while(!(TIM2->SR & 1));
//led off
GPIOD->ODR &= ~(1<<12);
// wait until UIF flag is set
while(!(TIM2->SR & 1));
}
}
void set_i2c_clk(struct qup_i2c_dev *dev)
{
uint32_t md = 0;
uint32_t ns = 0;
switch (dev->src_clk_freq) {
case 24000000:
ns = I2C_APPS_CLK_NS_24MHz;
md = I2C_APPS_CLK_MD_24MHz;
break;
default:
return;
}
/* Enable the GSBI8 HCLK */
writel((GSBI8_HCLK_CTL_CLK_ENA << GSBI8_HCLK_CTL_S),
GSBIn_HCLK_CTL(dev->gsbi_number));
clock_config(ns,
md,
GSBIn_QUP_APPS_NS(dev->gsbi_number),
GSBIn_QUP_APPS_MD(dev->gsbi_number));
}
static void
sys_reset(void)
{
unsigned int volatile *d;
d = dummy;
/* turn on the internal oscillator */
RCC->CR |= RCC_CR_HSION;
/* turn off the external oscillator, the clock security system, and the PLL */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* disable and clear any pending interrupts */
RCC->CIR =
RCC_CIR_LSIRDYC |
RCC_CIR_LSERDYC |
RCC_CIR_HSIRDYC |
RCC_CIR_HSERDYC |
RCC_CIR_PLLRDYC |
RCC_CIR_CSSC;
/* turn on the flash pre-fetch buffer and set its wait state to 2 */
FLASH->ACR |= FLASH_ACR_PRFTBE;
FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY) | FLASH_ACR_LATENCY_2;
copy_initialized();
clear_bss();
enable_fault_exceptions();
clock_config();
start_hse_clock();
flash_config();
use_pll();
main();
while(1);
}
/**
* machine_init
*
* Machine-specific initialization.
*/
void machine_init(void)
{
debug_log_init();
clock_config();
return;
}
/*ARGSUSED*/
static void
tmuattach(struct device *parent, struct device *self, void *args)
{
struct pbridge_attach_args *pa = args;
struct tmu_softc *sc;
u_int32_t tcnt;
int i;
tmu_sc = sc = (struct tmu_softc *)self;
sc->sc_bust = pa->pa_bust;
bus_space_map(sc->sc_bust, pa->pa_offset, TMU_REG_SIZE, 0,&sc->sc_bush);
/*
* Disable the timers
*/
bus_space_write_1(sc->sc_bust, sc->sc_bush, TMU_REG_TOCR, 0);
bus_space_write_1(sc->sc_bust, sc->sc_bush, TMU_REG_TSTR, 0);
for (i = 0; i < TMU_NTIMERS; i++)
bus_space_write_2(sc->sc_bust, sc->sc_bush, TMU_REG_TCR(i), 0);
/*
* Hook the timer interrupts.
* Note that passing NULL as the "arg" parameter tells the interrupt
* dispatcher to pass our handlers a pointer to the interrupt frame.
*/
sc->sc_clkih = sh5_intr_establish(pa->pa_intevt, IST_LEVEL,
pa->pa_ipl, tmu_clkint, NULL);
sc->sc_statih = sh5_intr_establish(pa->pa_intevt + 0x20, IST_LEVEL,
pa->pa_ipl, tmu_statint, NULL);
/*
* Calculate the number of timer ticks per millisecond
* This will be used in tmu_microtime() to return the
* number of micro-seconds since the last underflow.
*/
sc->sc_ticksperms = cprc_clocks.cc_peripheral / 4000;
printf(": Timer Unit\n");
printf("%s: Ticks per uS: %d.%03d\n", sc->sc_dev.dv_xname,
sc->sc_ticksperms / 1000, sc->sc_ticksperms % 1000);
/*
* Calculate the delay constant.
*/
_sh5_delay_constant = 1;
bus_space_write_4(sc->sc_bust, sc->sc_bush, TMU_REG_TCNT(0),
0xffffffff);
bus_space_write_2(sc->sc_bust, sc->sc_bush, TMU_REG_TCR(0),
TMU_TCR_TPSC_PDIV4);
bus_space_write_1(sc->sc_bust, sc->sc_bush, TMU_REG_TSTR, TMU_TSTR(0));
delay(100000);
tcnt = 0 - bus_space_read_4(sc->sc_bust, sc->sc_bush, TMU_REG_TCNT(0));
bus_space_write_1(sc->sc_bust, sc->sc_bush, TMU_REG_TSTR, 0);
tcnt = (tcnt * 1000) / sc->sc_ticksperms;
_sh5_delay_constant = (100000 / tcnt) + 1;
printf("%s: Delay constant: %d\n", sc->sc_dev.dv_xname,
_sh5_delay_constant);
/*
* Attach to the common clock back-end
*/
sc->sc_ca.ca_rate = cprc_clocks.cc_peripheral / 4;
sc->sc_ca.ca_has_stat_clock = 0;
sc->sc_ca.ca_arg = sc;
sc->sc_ca.ca_start = tmu_start;
sc->sc_ca.ca_microtime = tmu_microtime;
clock_config(self, &sc->sc_ca, sh5_intr_evcnt(sc->sc_clkih));
}