static void init_utmip_pll(void) { int khz = clock_get_osc_khz(); /* Shut off PLL crystal clock while we mess with it */ clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ udelay(1); write32(80 << 16 | /* (rst) phy_divn */ 1 << 8 | /* (rst) phy_divm */ 0, &clk_rst->utmip_pll_cfg0); /* 960MHz * 1 / 80 == 12 MHz */ write32(CEIL_DIV(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */ 0 << 16 | /* PLLU pwrdn */ 0 << 14 | /* pll_enable pwrdn */ 0 << 12 | /* pll_active pwrdn */ CEIL_DIV(khz, 102) << 0 | /* phy_stbl_cnt / 256 (2.5ms) */ 0, &clk_rst->utmip_pll_cfg1); /* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */ write32(0 << 24 | /* SAMP_D/XDEV pwrdn */ CEIL_DIV(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */ CEIL_DIV(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */ 0 << 4 | /* SAMP_C/USB3 pwrdn */ 0 << 2 | /* SAMP_B/XHOST pwrdn */ 0 << 0 | /* SAMP_A/USBD pwrdn */ 0, &clk_rst->utmip_pll_cfg2); setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ }
void clock_init_arm_generic_timer(void) { uint32_t freq = clock_get_osc_khz() * 1000; // Set the cntfrq register. set_cntfrq(freq); // Record the system timer frequency. write32(&sysctr->cntfid0, freq); // Enable the system counter. uint32_t cntcr = read32(&sysctr->cntcr); cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG; write32(&sysctr->cntcr, cntcr); }
void clock_init_arm_generic_timer(void) { uint32_t freq = clock_get_osc_khz() * 1000; // Set the cntfrq register. __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" :: "r"(freq)); // Record the system timer frequency. write32(freq, &sysctr->cntfid0); // Enable the system counter. uint32_t cntcr = read32(&sysctr->cntcr); cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG; write32(cntcr, &sysctr->cntcr); }