int board_usb_init(const void *blob)
{
struct fdt_usb config;
unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
enum clock_osc_freq freq;
int node_list[USB_PORTS_MAX];
int node, count, i;
/* Set up the USB clocks correctly based on our oscillator frequency */
freq = clock_get_osc_freq();
config_clock(usb_pll[freq]);
/* count may return <0 on error */
count = fdtdec_find_aliases_for_id(blob, "usb",
COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
for (i = 0; i < count; i++) {
debug("USB %d: ", i);
node = node_list[i];
if (!node)
continue;
if (fdt_decode_usb(blob, node, osc_freq, &config)) {
debug("Cannot decode USB node %s\n",
fdt_get_name(blob, node, NULL));
return -1;
}
if (add_port(&config, usb_pll[freq]))
return -1;
set_host_mode(&config);
}
return 0;
}
int tegra_set_emc(const void *blob, unsigned rate)
{
struct emc_ctlr *emc;
const u32 *table;
int err, i;
err = decode_emc(blob, rate, &emc, &table);
if (err) {
debug("Warning: no valid EMC (%d), memory timings unset\n",
err);
return err;
}
debug("%s: Table found, setting EMC values as follows:\n", __func__);
for (i = 0; i < TEGRA_EMC_NUM_REGS; i++) {
u32 value = fdt32_to_cpu(table[i]);
u32 addr = (uintptr_t)emc + emc_reg_addr[i];
debug(" %#x: %#x\n", addr, value);
writel(value, addr);
}
/* trigger emc with new settings */
clock_adjust_periph_pll_div(PERIPH_ID_EMC, CLOCK_ID_MEMORY,
clock_get_rate(CLOCK_ID_MEMORY), NULL);
debug("EMC clock set to %lu\n",
clock_get_periph_rate(PERIPH_ID_EMC, CLOCK_ID_MEMORY));
return 0;
}
int mmc_clock_get_rate(unsigned id)
{
return clock_get_rate(id); //Get mmc clock rate
}
int board_usb_init(const void *blob)
{
#ifdef CONFIG_OF_CONTROL
struct fdt_usb config;
int clk_done = 0;
int node, upto = 0;
unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
#if defined(CONFIG_TEGRA3)
struct usb_ctlr *usb1ctlr;
#endif
do {
node = fdt_decode_next_alias(blob, "usb",
COMPAT_NVIDIA_TEGRA250_USB, &upto);
if (node < 0)
break;
if (fdt_decode_usb(blob, node, osc_freq, &config))
return -1;
if (!config.enabled)
continue;
/* The first port we find gets to set the clocks */
if (!clk_done) {
config_clock(config.params);
clk_done = 1;
}
if (config.host_mode) {
/* Only one host-dev port is supported */
if (host_dev_ctlr)
return -1;
host_dev_ctlr = config.reg;
}
if (add_port(config.periph_id, config.reg, config.params,
config.utmi))
return -1;
#if defined(CONFIG_TEGRA3)
fdt_setup_gpio(&config.vbus_gpio);
fdt_setup_gpio(&config.vbus_pullup_gpio);
usb1ctlr = (struct usb_ctlr *)NV_PA_USB1_BASE;
/*
* BIAS Pad Power Down is common among all 3 USB
* controllers and can be controlled from USB1 only.
*/
bf_writel(UTMIP_BIASPD, 0, &usb1ctlr->utmip_bias_cfg0);
#endif
} while (node);
#else
enum clock_osc_freq freq;
const int *params;
/* Get the Oscillator frequency */
freq = clock_get_osc_freq();
/* Enable PLL U for USB */
params = &usb_pll[freq][0];
config_clock(params);
/* Set up our two ports */
#ifdef CONFIG_TEGRA2_USB1_HOST
host_dev_ctlr = (struct usb_ctlr *)NV_PA_USB1_BASE;
#endif
probe_port((struct usb_ctlr *)CONFIG_TEGRA2_USB0, params);
probe_port((struct usb_ctlr *)CONFIG_TEGRA2_USB1, params);
#endif /* CONFIG_OF_CONTROL */
usb_set_host_mode();
port_current = -1;
return 0;
}
