/******************************************************************************* * The following function provides a compatibility function for SPDs using the * existing cm library routines. This function is expected to be invoked for * initializing the cpu_context for the CPU specified by MPIDR for first use. ******************************************************************************/ void cm_init_context(unsigned long mpidr, const entry_point_info_t *ep) { if ((mpidr & MPIDR_AFFINITY_MASK) == (read_mpidr_el1() & MPIDR_AFFINITY_MASK)) cm_init_my_context(ep); else cm_init_context_by_index(platform_get_core_pos(mpidr), ep); }
/******************************************************************************* * The following function provides a compatibility function for SPDs using the * existing cm library routines. This function is expected to be invoked for * initializing the cpu_context for the CPU specified by MPIDR for first use. ******************************************************************************/ void cm_init_context(uint64_t mpidr, const entry_point_info_t *ep) { if ((mpidr & MPIDR_AFFINITY_MASK) == (read_mpidr_el1() & MPIDR_AFFINITY_MASK)) cm_init_my_context(ep); else { /* * Suppress deprecated declaration warning in compatibility * function */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wdeprecated-declarations" cm_init_context_by_index(platform_get_core_pos(mpidr), ep); #pragma GCC diagnostic pop } }
/******************************************************************************* * Generic handler which is called to physically power on a cpu identified by * its mpidr. It performs the generic, architectural, platform setup and state * management to power on the target cpu e.g. it will ensure that * enough information is stashed for it to resume execution in the non-secure * security state. * * The state of all the relevant power domains are changed after calling the * platform handler as it can return error. ******************************************************************************/ int psci_cpu_on_start(u_register_t target_cpu, entry_point_info_t *ep) { int rc; unsigned int target_idx = plat_core_pos_by_mpidr(target_cpu); aff_info_state_t target_aff_state; /* Calling function must supply valid input arguments */ assert((int) target_idx >= 0); assert(ep != NULL); /* * This function must only be called on platforms where the * CPU_ON platform hooks have been implemented. */ assert(psci_plat_pm_ops->pwr_domain_on && psci_plat_pm_ops->pwr_domain_on_finish); /* Protect against multiple CPUs trying to turn ON the same target CPU */ psci_spin_lock_cpu(target_idx); /* * Generic management: Ensure that the cpu is off to be * turned on. * Perform cache maintanence ahead of reading the target CPU state to * ensure that the data is not stale. * There is a theoretical edge case where the cache may contain stale * data for the target CPU data - this can occur under the following * conditions: * - the target CPU is in another cluster from the current * - the target CPU was the last CPU to shutdown on its cluster * - the cluster was removed from coherency as part of the CPU shutdown * * In this case the cache maintenace that was performed as part of the * target CPUs shutdown was not seen by the current CPU's cluster. And * so the cache may contain stale data for the target CPU. */ flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx)); if (rc != PSCI_E_SUCCESS) goto exit; /* * Call the cpu on handler registered by the Secure Payload Dispatcher * to let it do any bookeeping. If the handler encounters an error, it's * expected to assert within */ if (psci_spd_pm && psci_spd_pm->svc_on) psci_spd_pm->svc_on(target_cpu); /* * Set the Affinity info state of the target cpu to ON_PENDING. * Flush aff_info_state as it will be accessed with caches * turned OFF. */ psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); /* * The cache line invalidation by the target CPU after setting the * state to OFF (see psci_do_cpu_off()), could cause the update to * aff_info_state to be invalidated. Retry the update if the target * CPU aff_info_state is not ON_PENDING. */ target_aff_state = psci_get_aff_info_state_by_idx(target_idx); if (target_aff_state != AFF_STATE_ON_PENDING) { assert(target_aff_state == AFF_STATE_OFF); psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); assert(psci_get_aff_info_state_by_idx(target_idx) == AFF_STATE_ON_PENDING); } /* * Perform generic, architecture and platform specific handling. */ /* * Plat. management: Give the platform the current state * of the target cpu to allow it to perform the necessary * steps to power on. */ rc = psci_plat_pm_ops->pwr_domain_on(target_cpu); assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL); if (rc == PSCI_E_SUCCESS) /* Store the re-entry information for the non-secure world. */ cm_init_context_by_index(target_idx, ep); else { /* Restore the state on error. */ psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF); flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); } exit: psci_spin_unlock_cpu(target_idx); return rc; }