static inline __attribute__((unused)) int do_normal_boot(void)
{
unsigned char byte;
if (cmos_error() || !cmos_chksum_valid()) {
/* Invalid CMOS checksum detected!
* Force fallback boot...
*/
byte = cmos_read(RTC_BOOT_BYTE);
byte &= boot_set_fallback(byte) & 0x0f;
byte |= 0xf << 4;
cmos_write(byte, RTC_BOOT_BYTE);
}
/* The RTC_BOOT_BYTE is now o.k. see where to go. */
byte = cmos_read(RTC_BOOT_BYTE);
/* Are we attempting to boot normally? */
if (boot_use_normal(byte)) {
/* Are we already at the max count? */
if (boot_count(byte) < CONFIG_MAX_REBOOT_CNT)
byte = increment_boot_count(byte);
else
byte = boot_set_fallback(byte);
}
/* Save the boot byte */
cmos_write(byte, RTC_BOOT_BYTE);
/* Return selected code path for this boot attempt */
return boot_use_normal(byte);
}
void bootblock_mainboard_init(void)
{
uint8_t recovery_enabled;
unsigned char addr;
unsigned char byte;
bootblock_northbridge_init();
bootblock_southbridge_init();
/* Recovery jumper is connected to SP5100 GPIO61, and clears the GPIO when placed in the Recovery position */
byte = pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x56);
byte |= 0x1 << 4; /* Set GPIO61 to input mode */
pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte);
recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1));
if (recovery_enabled) {
#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
/* Clear NVRAM checksum */
for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
cmos_write(0x0, addr);
}
/* Set fallback boot */
byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0xfc;
cmos_write(byte, RTC_BOOT_BYTE);
#else
/* FIXME
* Figure out how to recover if the option table is not available
*/
#endif
}
}
static void cmos_post_code(u8 value)
{
spin_lock(&cmos_post_lock);
switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
case CMOS_POST_BANK_0_MAGIC:
cmos_write(value, CMOS_POST_BANK_0_OFFSET);
break;
case CMOS_POST_BANK_1_MAGIC:
cmos_write(value, CMOS_POST_BANK_1_OFFSET);
break;
}
spin_unlock(&cmos_post_lock);
}
void cpu_wakeup_aps(void)
{
int i;
struct cpu_info *cpu;
unsigned cpuid = cpu_number_from_lapic();
cmos_write(0xf, 0xa); // Shutdown causes warm reset.
for (i = 0; i < number_cpus; i++) {
if (i == cpuid)
continue;
cpu = cpuinfo_get(i);
printf("Waking up CPU %02d...", i);
/* Setup AP bootstrap page */
memcpy((void *) (UKERNBASE + UKERN_APBOOT(i)), &_ap_start,
(size_t) & _ap_end - (size_t) & _ap_start);
/* Setup Warm Reset Vector */
*(volatile uint16_t *) (UKERNBASE + 0x467) = UKERN_APBOOT(i) & 0xf;
*(volatile uint16_t *) (UKERNBASE + 0x469) = UKERN_APBOOT(i) >> 4;
/* INIT-SIPI-SIPI sequence. */
lapic_ipi(cpu->phys_id, APIC_DLVR_INIT, 0);
_delay();
lapic_ipi(cpu->phys_id, APIC_DLVR_START,
UKERN_APBOOT(i) >> 12);
_delay();
lapic_ipi(cpu->phys_id, APIC_DLVR_START,
UKERN_APBOOT(i) >> 12);
_delay();
printf(" done\n");
}
}
void save_mrc_data(struct pei_data *pei_data)
{
u16 c1, c2, checksum;
/* Save the MRC S3 restore data to cbmem */
store_current_mrc_cache(pei_data->mrc_output, pei_data->mrc_output_len);
/* Save the MRC seed values to CMOS */
cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
printk(BIOS_DEBUG, "Save scrambler seed 0x%08x to CMOS 0x%02x\n",
pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
cmos_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n",
pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
/* Save a simple checksum of the seed values */
c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed,
sizeof(u32));
c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3,
sizeof(u32));
checksum = add_ip_checksums(sizeof(u32), c1, c2);
cmos_write(checksum & 0xff, CMOS_OFFSET_MRC_SEED_CHK);
cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK+1);
}
void save_vbnv_cmos(const uint8_t *vbnv_copy)
{
int i;
for (i = 0; i < VBOOT_VBNV_BLOCK_SIZE; i++)
cmos_write(vbnv_copy[i], CONFIG_VBOOT_VBNV_OFFSET + 14 + i);
}
void save_mrc_data(struct pei_data *pei_data)
{
u16 c1, c2, checksum;
struct mrc_data_container *mrcdata;
int output_len = ALIGN(pei_data->mrc_output_len, 16);
/* Save the MRC S3 restore data to cbmem */
mrcdata = cbmem_add
(CBMEM_ID_MRCDATA,
output_len + sizeof(struct mrc_data_container));
if (mrcdata != NULL) {
printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n",
pei_data->mrc_output, mrcdata, output_len);
mrcdata->mrc_signature = MRC_DATA_SIGNATURE;
mrcdata->mrc_data_size = output_len;
mrcdata->reserved = 0;
memcpy(mrcdata->mrc_data, pei_data->mrc_output,
pei_data->mrc_output_len);
/* Zero the unused space in aligned buffer. */
if (output_len > pei_data->mrc_output_len)
memset(mrcdata->mrc_data+pei_data->mrc_output_len, 0,
output_len - pei_data->mrc_output_len);
mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data,
mrcdata->mrc_data_size);
}
/* Save the MRC seed values to CMOS */
cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
printk(BIOS_DEBUG, "Save scrambler seed 0x%08x to CMOS 0x%02x\n",
pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
cmos_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n",
pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
/* Save a simple checksum of the seed values */
c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed,
sizeof(u32));
c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3,
sizeof(u32));
checksum = add_ip_checksums(sizeof(u32), c1, c2);
cmos_write(checksum & 0xff, CMOS_OFFSET_MRC_SEED_CHK);
cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK+1);
}
/****************************************************************************
* do_cmos_writes
*
* 'list' is a linked list of pending CMOS write operations that have passed
* all sanity checks. Perform all write operations, destroying the list as
* we go.
****************************************************************************/
void do_cmos_writes(cmos_write_t * list)
{
cmos_write_t *item;
set_iopl(3);
while (list != NULL) {
cmos_entry_t e;
item = list;
e.bit = item->bit;
e.length = item->length;
e.config = item->config;
list = item->next;
cmos_write(&e, item->value);
free(item);
}
cmos_checksum_write(cmos_checksum_compute());
set_iopl(0);
}
int mainboard_should_reset_usb(int s3resume)
{
if (s3resume) {
/*
* For Stumpy the back USB ports are reset on resume
* so default to resetting the controller to make the
* kernel happy. There is a CMOS flag to disable the
* controller reset in case the kernel can tolerate
* the device power loss better in the future.
*/
u8 magic = cmos_read(CMOS_USB_RESET_DISABLE);
if (magic == USB_RESET_DISABLE_MAGIC) {
printk(BIOS_DEBUG, "USB Controller Reset Disabled\n");
return 0;
} else {
printk(BIOS_DEBUG, "USB Controller Reset Enabled\n");
return 1;
}
} else {
/* Ensure USB reset on resume is enabled at boot */
cmos_write(0, CMOS_USB_RESET_DISABLE);
return 1;
}
}
static void cmos_write_bcd ( int port, int data )
{
cmos_write(port,cmos_bcd()?(data/10)<<4|(data%10):data) ;
}
void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
.system_type = 0, // 0 Mobile, 1 Desktop/Server
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00,0xa4,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 0,
// 0 = leave channel enabled
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel
// 3 = disable dimm 0+1 on channel
.dimm_channel0_disabled = 2,
.dimm_channel1_disabled = 2,
.max_ddr3_freq = 1333,
.usb_port_config = {
{ 1, 0, 0x0080 }, /* P0: Front port (OC0) */
{ 1, 1, 0x0040 }, /* P1: Back port (OC1) */
{ 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */
{ 1, 0, 0x0040 }, /* P3: MMC (no OC) */
{ 1, 2, 0x0080 }, /* P4: Front port (OC2) */
{ 0, 0, 0x0000 }, /* P5: Empty */
{ 0, 0, 0x0000 }, /* P6: Empty */
{ 0, 0, 0x0000 }, /* P7: Empty */
{ 1, 4, 0x0040 }, /* P8: Back port (OC4) */
{ 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */
{ 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */
{ 0, 4, 0x0000 }, /* P11: Empty */
{ 1, 6, 0x0040 }, /* P12: Back port (OC6) */
{ 1, 5, 0x0040 }, /* P13: Back port (OC5) */
},
};
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();
pch_enable_lpc();
/* Enable GPIOs */
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&stumpy_gpio_map);
setup_sio_gpios();
/* Early SuperIO setup */
it8772f_ac_resume_southbridge(DUMMY_DEV);
ite_kill_watchdog(GPIO_DEV);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
init_bootmode_straps();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected\n");
boot_mode = 1;
/* System is not happy after keyboard reset... */
printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
outb(0x6, 0xcf9);
halt();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
enable_smbus();
/* Prepare USB controller early in S3 resume */
if (boot_mode == 2) {
/*
* For Stumpy the back USB ports are reset on resume
* so default to resetting the controller to make the
* kernel happy. There is a CMOS flag to disable the
* controller reset in case the kernel can tolerate
* the device power loss better in the future.
*/
u8 magic = cmos_read(CMOS_USB_RESET_DISABLE);
if (magic == USB_RESET_DISABLE_MAGIC) {
printk(BIOS_DEBUG, "USB Controller Reset Disabled\n");
enable_usb_bar();
} else {
printk(BIOS_DEBUG, "USB Controller Reset Enabled\n");
}
} else {
/* Ensure USB reset on resume is enabled at boot */
cmos_write(0, CMOS_USB_RESET_DISABLE);
}
post_code(0x39);
pei_data.boot_mode = boot_mode;
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(&pei_data);
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x3a);
/* Perform some initialization that must run before stage2 */
early_pch_init();
post_code(0x3b);
rcba_config();
post_code(0x3c);
quick_ram_check();
post_code(0x3e);
cbmem_was_initted = !cbmem_recovery(boot_mode==2);
if (boot_mode!=2)
save_mrc_data(&pei_data);
if (boot_mode==2 && !cbmem_was_initted) {
/* Failed S3 resume, reset to come up cleanly */
outb(0x6, 0xcf9);
halt();
}
northbridge_romstage_finalize(boot_mode==2);
post_code(0x3f);
if (CONFIG_LPC_TPM) {
init_tpm(boot_mode == 2);
}
}
/****************************************************************************
* set_one_param
*
* Set the CMOS parameter given by 'name' to 'value'. The 'name' parameter
* is case-sensitive. If we are setting an enum parameter, then 'value' is
* interpreted as a case-sensitive string that must match the option name
* exactly. If we are setting a 'hex' parameter, then 'value' is treated as
* a string representation of an unsigned integer that may be specified in
* decimal, hex, or octal.
****************************************************************************/
static void set_one_param(const char name[], const char value[])
{
const cmos_entry_t *e;
unsigned long long n;
if (is_checksum_name(name) || (e = find_cmos_entry(name)) == NULL) {
fprintf(stderr, "%s: CMOS parameter %s not found.", prog_name,
name);
exit(1);
}
switch (prepare_cmos_write(e, value, &n)) {
case OK:
break;
case CMOS_OP_BAD_ENUM_VALUE:
fprintf(stderr, "%s: Bad value for parameter %s.", prog_name,
name);
goto fail;
case CMOS_OP_NEGATIVE_INT:
fprintf(stderr,
"%s: This program does not support assignment of negative "
"numbers to coreboot parameters.", prog_name);
goto fail;
case CMOS_OP_INVALID_INT:
fprintf(stderr, "%s: %s is not a valid integer.", prog_name,
value);
goto fail;
case CMOS_OP_RESERVED:
fprintf(stderr,
"%s: Can not modify reserved coreboot parameter %s.",
prog_name, name);
goto fail;
case CMOS_OP_VALUE_TOO_WIDE:
fprintf(stderr,
"%s: Can not write value %s to CMOS parameter %s that is "
"only %d bits wide.", prog_name, value, name,
e->length);
goto fail;
case CMOS_OP_NO_MATCHING_ENUM:
fprintf(stderr,
"%s: coreboot parameter %s has no matching enums.",
prog_name, name);
goto fail;
case CMOS_AREA_OUT_OF_RANGE:
fprintf(stderr,
"%s: The CMOS area specified by the layout info for "
"coreboot parameter %s is out of range.", prog_name,
name);
goto fail;
case CMOS_AREA_OVERLAPS_RTC:
fprintf(stderr,
"%s: The CMOS area specified by the layout info for "
"coreboot parameter %s overlaps the realtime clock area.",
prog_name, name);
goto fail;
case CMOS_AREA_TOO_WIDE:
fprintf(stderr,
"%s: The CMOS area specified by the layout info for "
"coreboot parameter %s is too wide.", prog_name, name);
goto fail;
default:
fprintf(stderr,
"%s: Unknown error encountered while attempting to modify "
"coreboot parameter %s.", prog_name, name);
goto fail;
}
/* write the value to nonvolatile RAM */
set_iopl(3);
cmos_write(e, n);
cmos_checksum_write(cmos_checksum_compute());
set_iopl(0);
return;
fail:
fprintf(stderr, " CMOS write not performed.\n");
exit(1);
}
