static void
obiouart_attach(device_t parent, device_t self, void *aux)
{
struct com_obio_softc *osc = device_private(self);
struct com_softc *sc = &osc->sc_sc;
struct obio_attach_args *obio = aux;
bus_space_tag_t bst;
bus_space_handle_t bsh = 0;
bus_addr_t iobase;
sc->sc_dev = self;
bst = obio->obio_bst;
iobase = obio->obio_base + obio->obio_offset;
sc->sc_frequency = ROCKCHIP_UART_FREQ;
sc->sc_type = COM_TYPE_NORMAL;
if (com_is_console(bst, iobase, &bsh) == 0 &&
bus_space_subregion(bst, obio->obio_bsh, obio->obio_size, 0, &bsh)) {
panic(": can't map registers\n");
return;
}
COM_INIT_REGS(sc->sc_regs, bst, bsh, iobase);
com_attach_subr(sc);
aprint_naive("\n");
#if 1
KASSERT(obio->obio_intr != OBIOCF_INTR_DEFAULT);
osc->sc_ih = intr_establish(obio->obio_intr, IPL_SERIAL, IST_EDGE,
comintr, sc);
if (osc->sc_ih == NULL)
panic("%s: failed to establish interrup %d",
device_xname(self), obio->obio_intr);
#endif
}
void
com_mainbus_attach(device_t parent, device_t self, void *aux)
{
struct com_mainbus_softc *msc = device_private(self);
struct com_softc *sc = &msc->sc_com;
struct mainbus_attach_args *maa = aux;
bus_space_handle_t ioh;
sc->sc_dev = self;
if (!com_is_console(maa->ma_iot, maa->ma_addr, &ioh) &&
bus_space_map(maa->ma_iot, maa->ma_addr, COM_NPORTS, 0, &ioh)) {
aprint_error(": can't map i/o space\n");
return;
}
COM_INIT_REGS(sc->sc_regs, maa->ma_iot, ioh, maa->ma_addr);
sc->sc_frequency = COM_MAINBUS_FREQ;
com_attach_subr(sc);
cpu_intr_establish(maa->ma_level, IPL_SERIAL, comintr, sc);
return;
}
static bus_addr_t
pucprobe_doit(struct consdev *cn)
{
struct pci_attach_args pa;
int bus;
static int dev = 0, func = 0;
int maxdev, nfunctions = 0, i; /* XXX */
pcireg_t reg, bhlcr, subsys = 0; /* XXX */
int foundport = 0;
const struct puc_device_description *desc;
pcireg_t base;
/* Fetch our tags */
if (cpu_comcnprobe(cn, &pa) != 0) {
return 0;
}
puctag = pa.pa_iot;
pci_decompose_tag(pa.pa_pc, pa.pa_tag, &bus, &maxdev, NULL);
/* scan through devices */
for (; dev <= maxdev ; dev++) {
pa.pa_tag = pci_make_tag(pa.pa_pc, bus, dev, 0);
reg = pci_conf_read(pa.pa_pc, pa.pa_tag, PCI_ID_REG);
if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID
|| PCI_VENDOR(reg) == 0)
continue;
bhlcr = pci_conf_read(pa.pa_pc, pa.pa_tag, PCI_BHLC_REG);
if (PCI_HDRTYPE_MULTIFN(bhlcr)) {
nfunctions = 8;
} else {
nfunctions = 1;
}
resume_scan:
for (; func < nfunctions; func++) {
pa.pa_tag = pci_make_tag(pa.pa_pc, bus, dev, func);
reg = pci_conf_read(pa.pa_pc, pa.pa_tag, PCI_CLASS_REG);
if (PCI_CLASS(reg) == PCI_CLASS_COMMUNICATIONS
&& PCI_SUBCLASS(reg)
== PCI_SUBCLASS_COMMUNICATIONS_SERIAL) {
pa.pa_id = pci_conf_read(pa.pa_pc, pa.pa_tag, PCI_ID_REG);
subsys = pci_conf_read(pa.pa_pc, pa.pa_tag,
PCI_SUBSYS_ID_REG);
foundport = 1;
break;
}
}
if (foundport)
break;
func = 0;
}
if (!foundport)
return 0;
foundport = 0;
desc = puc_find_description(PCI_VENDOR(pa.pa_id),
PCI_PRODUCT(pa.pa_id), PCI_VENDOR(subsys), PCI_PRODUCT(subsys));
if (desc == NULL) {
func++;
goto resume_scan;
}
for (i = 0; PUC_PORT_VALID(desc, i); i++)
{
if (desc->ports[i].type != PUC_PORT_TYPE_COM)
continue;
base = pci_conf_read(pa.pa_pc, pa.pa_tag, desc->ports[i].bar);
base += desc->ports[i].offset;
if (PCI_MAPREG_TYPE(base) != PCI_MAPREG_TYPE_IO)
continue;
base = PCI_MAPREG_IO_ADDR(base);
if (com_is_console(puctag, base, NULL))
continue;
foundport = 1;
break;
}
if (foundport == 0) {
func++;
goto resume_scan;
}
cn->cn_pri = CN_REMOTE;
return PCI_MAPREG_IO_ADDR(base);
}
int
ioat66probe(device_t parent, cfdata_t self, void *aux)
{
struct isa_attach_args *ia = aux;
bus_space_tag_t iot = ia->ia_iot;
bus_space_handle_t ioh;
int iobase;
int i, rv = 1;
if (ia->ia_niomem < 1)
return (0);
if (ia->ia_nirq < 1)
return (0);
/*
* Do the normal com probe for the first UART and assume
* its presence, and the ability to map the other UARTS,
* means there is a multiport board there.
* XXX Needs more robustness.
*/
/* Disallow wildcarded i/o address. */
if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT)
return 0;
if (ia->ia_irq[0].ir_irq == ISA_UNKNOWN_IRQ)
return (0);
iobase = ia->ia_io[0].ir_addr;
/* if the first port is in use as console, then it. */
if (com_is_console(iot, iobase, 0))
goto checkmappings;
if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) {
rv = 0;
goto out;
}
rv = comprobe1(iot, ioh);
bus_space_unmap(iot, ioh, COM_NPORTS);
if (rv == 0)
goto out;
checkmappings:
for (i = 1; i < NSLAVES; i++) {
iobase = ioatbases[i];
if (com_is_console(iot, iobase, 0))
continue;
if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) {
rv = 0;
goto out;
}
bus_space_unmap(iot, ioh, COM_NPORTS);
}
out:
if (rv) {
ia->ia_nio = 1;
ia->ia_io[0].ir_size = NSLAVES * COM_NPORTS;
ia->ia_nirq = 1;
ia->ia_niomem = 0;
ia->ia_ndrq = 0;
}
return (rv);
}
static int
pxauart_match(device_t parent, cfdata_t cf, void *aux)
{
struct pxaip_attach_args *pxa = aux;
bus_space_tag_t bt = &pxa2x0_a4x_bs_tag; /* XXX: This sucks */
bus_space_handle_t bh;
struct pxa2x0_gpioconf *gpioconf;
u_int gpio;
int rv, i;
switch (pxa->pxa_addr) {
case PXA2X0_FFUART_BASE:
if (pxa->pxa_intr != PXA2X0_INT_FFUART)
return (0);
gpioconf = CPU_IS_PXA250 ? pxa25x_com_ffuart_gpioconf :
pxa27x_com_ffuart_gpioconf;
break;
case PXA2X0_STUART_BASE:
if (pxa->pxa_intr != PXA2X0_INT_STUART)
return (0);
gpioconf = CPU_IS_PXA250 ? pxa25x_com_stuart_gpioconf :
pxa27x_com_stuart_gpioconf;
break;
case PXA2X0_BTUART_BASE: /* XXX: Config file option ... */
if (pxa->pxa_intr != PXA2X0_INT_BTUART)
return (0);
gpioconf = CPU_IS_PXA250 ? pxa25x_com_btuart_gpioconf :
pxa27x_com_btuart_gpioconf;
break;
case PXA2X0_HWUART_BASE:
if (pxa->pxa_intr != PXA2X0_INT_HWUART)
return (0);
if (CPU_IS_PXA270)
return (0);
gpioconf = pxa25x_com_hwuart_gpioconf;
break;
default:
return (0);
}
for (i = 0; gpioconf[i].pin != -1; i++) {
gpio = pxa2x0_gpio_get_function(gpioconf[i].pin);
if (GPIO_FN(gpio) != GPIO_FN(gpioconf[i].value) ||
GPIO_FN_IS_OUT(gpio) != GPIO_FN_IS_OUT(gpioconf[i].value))
return (0);
}
pxa->pxa_size = 0x20;
if (com_is_console(bt, pxa->pxa_addr, NULL))
return (1);
if (bus_space_map(bt, pxa->pxa_addr, pxa->pxa_size, 0, &bh))
return (0);
/* Make sure the UART is enabled */
bus_space_write_1(bt, bh, com_ier, IER_EUART);
rv = comprobe1(bt, bh);
bus_space_unmap(bt, bh, pxa->pxa_size);
return (rv);
}
static void
com_obio_attach(device_t parent, device_t self, void *aux)
{
struct com_obio_softc *osc = device_private(self);
struct com_softc *sc = &osc->osc_com;
union obio_attach_args *uoba = aux;
struct sbus_attach_args *sa = &uoba->uoba_sbus;
bus_space_handle_t ioh;
bus_space_tag_t iot;
bus_addr_t iobase;
sc->sc_dev = self;
if (strcmp("modem", sa->sa_name) == 0) {
osc->osc_tadpole = 1;
}
/*
* We're living on an obio that looks like an sbus slot.
*/
iot = sa->sa_bustag;
iobase = sa->sa_offset;
sc->sc_frequency = COM_FREQ;
/*
* XXX: It would be nice to be able to split console input and
* output to different devices. For now switch to serial
* console if PROM stdin is on serial (so that we can use DDB).
*/
if (prom_instance_to_package(prom_stdin()) == sa->sa_node)
comcnattach(iot, iobase, B9600, sc->sc_frequency,
COM_TYPE_NORMAL, (CLOCAL | CREAD | CS8));
if (!com_is_console(iot, iobase, &ioh) &&
sbus_bus_map(iot, sa->sa_slot, iobase, sa->sa_size,
BUS_SPACE_MAP_LINEAR, &ioh) != 0) {
aprint_error(": can't map registers\n");
return;
}
COM_INIT_REGS(sc->sc_regs, iot, ioh, iobase);
if (osc->osc_tadpole) {
*AUXIO4M_REG |= (AUXIO4M_LED|AUXIO4M_LTE);
do {
DELAY(100);
} while (!com_probe_subr(&sc->sc_regs));
#if 0
printf("modem: attach: lcr=0x%02x iir=0x%02x\n",
bus_space_read_1(sc->sc_regs.iot, sc->sc_regs.ioh, 3),
bus_space_read_1(sc->sc_regs.iot, sc->sc_regs.ioh, 2));
#endif
}
com_attach_subr(sc);
if (sa->sa_nintr != 0) {
(void)bus_intr_establish(sc->sc_regs.cr_iot, sa->sa_pri,
IPL_SERIAL, comintr, sc);
evcnt_attach_dynamic(&osc->osc_intrcnt, EVCNT_TYPE_INTR, NULL,
device_xname(self), "intr");
}
if (!pmf_device_register1(self, com_suspend, com_resume, com_cleanup)) {
aprint_error_dev(self, "could not establish shutdown hook");
}
}
static void
puc_attach(device_t parent, device_t self, void *aux)
{
struct puc_softc *sc = device_private(self);
struct pci_attach_args *pa = aux;
struct puc_attach_args paa;
pci_intr_handle_t intrhandle;
pcireg_t subsys;
int i, barindex;
bus_addr_t base;
bus_space_tag_t tag;
#ifdef PUCCN
bus_space_handle_t ioh;
#endif
int locs[PUCCF_NLOCS];
subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
sc->sc_desc = puc_find_description(PCI_VENDOR(pa->pa_id),
PCI_PRODUCT(pa->pa_id), PCI_VENDOR(subsys), PCI_PRODUCT(subsys));
if (sc->sc_desc == NULL) {
/*
* This was a class/subclass match, so tell people to compile
* kernel with options that cause this driver to spew.
*/
#ifdef PUC_PRINT_REGS
printf(":\n");
pci_conf_print(pa->pa_pc, pa->pa_tag, NULL);
#else
printf(": unknown PCI communications device\n");
printf("%s: compile kernel with PUC_PRINT_REGS and larger\n",
device_xname(self));
printf("%s: mesage buffer (via 'options MSGBUFSIZE=...'),\n",
device_xname(self));
printf("%s: and report the result with send-pr\n",
device_xname(self));
#endif
return;
}
printf(": %s (", sc->sc_desc->name);
for (i = 0; PUC_PORT_VALID(sc->sc_desc, i); i++)
printf("%s%s", i ? ", " : "",
puc_port_type_name(sc->sc_desc->ports[i].type));
printf(")\n");
for (i = 0; i < 6; i++) {
pcireg_t bar, type;
sc->sc_bar_mappings[i].mapped = 0;
bar = pci_conf_read(pa->pa_pc, pa->pa_tag,
PCI_MAPREG_START + 4 * i); /* XXX const */
if (bar == 0) /* BAR not implemented(?) */
continue;
type = (PCI_MAPREG_TYPE(bar) == PCI_MAPREG_TYPE_IO ?
PCI_MAPREG_TYPE_IO : PCI_MAPREG_MEM_TYPE(bar));
if (type == PCI_MAPREG_TYPE_IO) {
tag = pa->pa_iot;
base = PCI_MAPREG_IO_ADDR(bar);
} else {
tag = pa->pa_memt;
base = PCI_MAPREG_MEM_ADDR(bar);
}
#ifdef PUCCN
if (com_is_console(tag, base, &ioh)) {
sc->sc_bar_mappings[i].mapped = 1;
sc->sc_bar_mappings[i].a = base;
sc->sc_bar_mappings[i].s = COM_NPORTS;
sc->sc_bar_mappings[i].t = tag;
sc->sc_bar_mappings[i].h = ioh;
continue;
}
#endif
sc->sc_bar_mappings[i].mapped = (pci_mapreg_map(pa,
PCI_MAPREG_START + 4 * i, type, 0,
&sc->sc_bar_mappings[i].t, &sc->sc_bar_mappings[i].h,
&sc->sc_bar_mappings[i].a, &sc->sc_bar_mappings[i].s)
== 0);
if (sc->sc_bar_mappings[i].mapped)
continue;
aprint_error_dev(self, "couldn't map BAR at offset 0x%lx\n",
(long)(PCI_MAPREG_START + 4 * i));
}
/* Map interrupt. */
if (pci_intr_map(pa, &intrhandle)) {
aprint_error_dev(self, "couldn't map interrupt\n");
return;
}
/*
* XXX the sub-devices establish the interrupts, for the
* XXX following reasons:
* XXX
* XXX * we can't really know what IPLs they'd want
* XXX
* XXX * the MD dispatching code can ("should") dispatch
* XXX chained interrupts better than we can.
* XXX
* XXX It would be nice if we could indicate to the MD interrupt
* XXX handling code that the interrupt line used by the device
* XXX was a PCI (level triggered) interrupt.
* XXX
* XXX It's not pretty, but hey, what is?
*/
/* Configure each port. */
for (i = 0; PUC_PORT_VALID(sc->sc_desc, i); i++) {
bus_space_handle_t subregion_handle;
/* make sure the base address register is mapped */
barindex = PUC_PORT_BAR_INDEX(sc->sc_desc->ports[i].bar);
if (!sc->sc_bar_mappings[barindex].mapped) {
printf("%s: %s port uses unmapped BAR (0x%x)\n",
device_xname(self),
puc_port_type_name(sc->sc_desc->ports[i].type),
sc->sc_desc->ports[i].bar);
continue;
}
/* set up to configure the child device */
paa.port = i;
paa.type = sc->sc_desc->ports[i].type;
paa.flags = sc->sc_desc->ports[i].flags;
paa.pc = pa->pa_pc;
paa.tag = pa->pa_tag;
paa.intrhandle = intrhandle;
paa.a = sc->sc_bar_mappings[barindex].a;
paa.t = sc->sc_bar_mappings[barindex].t;
paa.dmat = pa->pa_dmat;
paa.dmat64 = pa->pa_dmat64;
if (
#ifdef PUCCN
!com_is_console(sc->sc_bar_mappings[barindex].t,
sc->sc_bar_mappings[barindex].a, &subregion_handle)
&&
#endif
bus_space_subregion(sc->sc_bar_mappings[barindex].t,
sc->sc_bar_mappings[barindex].h,
sc->sc_desc->ports[i].offset,
sc->sc_bar_mappings[barindex].s -
sc->sc_desc->ports[i].offset,
&subregion_handle) != 0) {
aprint_error_dev(self, "couldn't get subregion for port %d\n", i);
continue;
}
paa.h = subregion_handle;
#if 0
printf("%s: port %d: %s @ (index %d) 0x%x (0x%lx, 0x%lx)\n",
device_xname(self), paa.port,
puc_port_type_name(paa.type), barindex, (int)paa.a,
(long)paa.t, (long)paa.h);
#endif
locs[PUCCF_PORT] = i;
/* and configure it */
sc->sc_ports[i].dev = config_found_sm_loc(self, "puc", locs,
&paa, puc_print, config_stdsubmatch);
}
}
static bus_addr_t
pucprobe_doit(struct consdev *cn)
{
struct pci_attach_args pa;
int bus;
static int dev = 0, func = 0;
int maxdev, nfunctions = 0, i; /* XXX */
pcireg_t reg, bhlcr, subsys = 0; /* XXX */
int foundport = 0;
const struct puc_device_description *desc;
pcireg_t base;
/* Fetch our tags */
#if defined(amd64) || defined(i386)
if (cpu_puc_cnprobe(cn, &pa) != 0)
#endif
return 0;
pci_decompose_tag(pa.pa_pc, pa.pa_tag, &bus, &maxdev, NULL);
/* Scan through devices and find a communication class device. */
for (; dev <= maxdev ; dev++) {
pa.pa_tag = pci_make_tag(pa.pa_pc, bus, dev, 0);
reg = pci_conf_read(pa.pa_pc, pa.pa_tag, PCI_ID_REG);
if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID
|| PCI_VENDOR(reg) == 0)
continue;
bhlcr = pci_conf_read(pa.pa_pc, pa.pa_tag, PCI_BHLC_REG);
if (PCI_HDRTYPE_MULTIFN(bhlcr)) {
nfunctions = 8;
} else {
nfunctions = 1;
}
resume_scan:
for (; func < nfunctions; func++) {
pa.pa_tag = pci_make_tag(pa.pa_pc, bus, dev, func);
reg = pci_conf_read(pa.pa_pc, pa.pa_tag,
PCI_CLASS_REG);
if (PCI_CLASS(reg) == PCI_CLASS_COMMUNICATIONS
&& PCI_SUBCLASS(reg)
== PCI_SUBCLASS_COMMUNICATIONS_SERIAL) {
pa.pa_id = pci_conf_read(pa.pa_pc, pa.pa_tag,
PCI_ID_REG);
subsys = pci_conf_read(pa.pa_pc, pa.pa_tag,
PCI_SUBSYS_ID_REG);
foundport = 1;
break;
}
}
if (foundport)
break;
func = 0;
}
/*
* If all devices was scanned and couldn't find any communication
* device, return with 0.
*/
if (!foundport)
return 0;
/* Clear foundport flag */
foundport = 0;
/* Check whether the device is in the puc device table or not */
desc = puc_find_description(PCI_VENDOR(pa.pa_id),
PCI_PRODUCT(pa.pa_id), PCI_VENDOR(subsys), PCI_PRODUCT(subsys));
/* If not, check the next communication device */
if (desc == NULL) {
/* Resume from the next function */
func++;
goto resume_scan;
}
/*
* We found a device and it's on the puc table. Set the tag and
* the base address.
*/
for (i = 0; PUC_PORT_VALID(desc, i); i++) {
if (desc->ports[i].type != PUC_PORT_TYPE_COM)
continue;
puccnflags = desc->ports[i].flags;
base = pci_conf_read(pa.pa_pc, pa.pa_tag, desc->ports[i].bar);
base += desc->ports[i].offset;
if (PCI_MAPREG_TYPE(base) == PCI_MAPREG_TYPE_IO) {
puctag = pa.pa_iot;
base = PCI_MAPREG_IO_ADDR(base);
}
#if 0 /* For MMIO device */
else {
puctag = pa.pa_memt;
base = PCI_MAPREG_MEM_ADDR(base);
}
#endif
if (com_is_console(puctag, base, NULL))
continue;
foundport = 1;
break;
}
if (foundport == 0) {
func++;
goto resume_scan;
}
#if 0
cn->cn_pri = CN_REMOTE;
#else
if (cn)
cn->cn_pri = CN_REMOTE;
#endif
return base;
}
