int board_init(void) { char *env_hwconfig; u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; #ifdef CONFIG_FSL_MC_ENET u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; #endif u32 val; init_final_memctl_regs(); val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); env_hwconfig = getenv("hwconfig"); if (hwconfig_f("dspi", env_hwconfig) && DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) config_board_mux(MUX_TYPE_DSPI); else config_board_mux(MUX_TYPE_SDHC); #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); #ifdef CONFIG_FSL_MC_ENET /* invert AQR405 IRQ pins polarity */ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); #endif return 0; }
int config_serdes_mux(void) { struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; u32 cfg; cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; switch (cfg) { case 0x0: config_board_mux(MUX_TYPE_SD_PCI4); break; case 0x30: config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG); break; case 0x60: config_board_mux(MUX_TYPE_SD_PC_SG_SG); break; case 0x70: config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG); break; default: printf("SRDS1 prtcl:0x%x\n", cfg); break; } return 0; }
int misc_init_r(void) { if (hwconfig("gpio")) config_board_mux(MUX_TYPE_GPIO); return 0; }
int misc_init_r(void) { if (hwconfig("sdhc")) config_board_mux(MUX_TYPE_SDHC); return 0; }
int misc_init_r(void) { int conflict_flag; /* some signals can not enable simultaneous*/ conflict_flag = 0; if (hwconfig("sdhc")) conflict_flag++; if (hwconfig("iic2")) conflict_flag++; if (conflict_flag > 1) { printf("WARNING: pin conflict !\n"); return 0; } conflict_flag = 0; if (hwconfig("rgmii")) conflict_flag++; if (hwconfig("can")) conflict_flag++; if (hwconfig("sai")) conflict_flag++; if (conflict_flag > 1) { printf("WARNING: pin conflict !\n"); return 0; } if (hwconfig("can")) config_board_mux(MUX_TYPE_CAN); else if (hwconfig("rgmii")) config_board_mux(MUX_TYPE_RGMII); else if (hwconfig("sai")) config_board_mux(MUX_TYPE_SAI); if (hwconfig("iic2")) config_board_mux(MUX_TYPE_IIC2); else if (hwconfig("sdhc")) config_board_mux(MUX_TYPE_SDHC); #ifdef CONFIG_FSL_DEVICE_DISABLE device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); #endif #ifdef CONFIG_FSL_CAAM return sec_init(); #endif return 0; }
int misc_init_r(void) { if (hwconfig("sdhc")) config_board_mux(MUX_TYPE_SDHC); if (adjust_vdd(0)) printf("Warning: Adjusting core voltage failed.\n"); return 0; }
int misc_init_r(void) { #ifndef CONFIG_QSPI_BOOT config_board_mux(); #endif #ifdef CONFIG_FSL_CAAM return sec_init(); #endif }
int misc_init_r(void) { #ifdef CONFIG_FSL_DEVICE_DISABLE device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); #endif #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) config_board_mux(); #endif #ifdef CONFIG_FSL_CAAM return sec_init(); #endif }
int misc_init_r(void) { config_board_mux(); return 0; }