hand_t::hand_t(eleap::eleap_t::impl_t *root, unsigned id, const piw::cookie_t &output):
root_(root), id_(id), leap_id_(0)
{
connect(output);
palm_wire_t *w = new palm_wire_t(1);
connect_wire(w, w->source());
palm_wire_ = pic::ref(w);
}
/// osc_pad_t::impl_t implementation
osc_pad_t::impl_t::impl_t(piw::clockdomain_ctl_t *cd, const piw::cookie_t &c,
const std::string &send_host, const std::string &send_port, const std::string &recv_port) :
root_t(0), up_(0),
server_( new osc_server_t(recv_port)), client_(new osc_client_t(send_host,send_port)),
view_(new live_model::live_view_t(model_,0,50,0,25))
{
connect(c);
cd->sink(this,"oscinput");
tick_enable(true);
set_clock(this);
light_wire_ = pic::ref(new light_wire_t(this));
connect_wire(light_wire_.ptr(), light_wire_->source());
client_->osc_startup();
server_->osc_startup();
server_->registerHandler(new clip_info_handler_t(light_wire_.ptr()));
server_->registerHandler(new track_info_handler_t(light_wire_.ptr()));
server_->registerHandler(new name_clip_handler_t(view(), client_));
server_->registerHandler(new armed_handler_t(view(), client_));
server_->registerHandler(new startup_handler_t(light_wire_.ptr()));
server_->registerHandler(new shutdown_handler_t(light_wire_.ptr()));
client_->send(new live_name_clip_message_t());
}
bool module::read_module(string buff, map<string, module*> &map_module, map<string, cell*> &map_cell) {
try {
string buff_s = buff;
string input_line, output_line, wire_line, instance_line;
std::regex e;
std::smatch sm;
std::regex_iterator<std::string::iterator> rit;
std::regex_iterator<std::string::iterator> rend;
e = "module ([\\\\\\._a-zA-Z0-9]+)";
std::regex_search(buff, sm, e);
sModuleName = sm[1];
cout << "module_name: " << sModuleName << endl;
e = "input\\s+([^;]+;)";
string buff_input = buff;
while (std::regex_search(buff_input, sm, e)) {
input_line = sm[1];
std::regex e_input_line("([\\\\\\w]+)");
rit = std::regex_iterator<std::string::iterator>(input_line.begin(), input_line.end(), e_input_line);
while (rit != rend) {
add_net(rit->str());
set_input(get_net(rit->str()), true);
rit++;
}
buff_input = sm.suffix().str();
}
e = "output\\s+([^;]+;)";
string buff_output = buff;
while (std::regex_search(buff_output, sm, e)) {
output_line = sm[1];
std::regex e_output_line("([\\\\\\w]+)");
rit = std::regex_iterator<std::string::iterator>(output_line.begin(), output_line.end(), e_output_line);
while (rit != rend) {
add_net(rit->str());
set_output(get_net(rit->str()), true);
rit++;
}
buff_output = sm.suffix().str();
}
e = "wire\\s+([^;]+;)";
string buff_wire = buff;
while (std::regex_search(buff_wire, sm, e)) {
wire_line = sm[1];
std::regex e_wire_line("([\\\\\\w]+)");
rit = std::regex_iterator<std::string::iterator>(wire_line.begin(), wire_line.end(), e_wire_line);
while (rit != rend) {
add_net(rit->str());
rit++;
}
buff_wire = sm.suffix().str();
}
e = "([\\\\\\.\\w]+)\\s+([\\\\\\.\\w]+)\\s*\\((?:.|\\s)*?\\);";
rit = std::regex_iterator<std::string::iterator>(buff_s.begin(), buff_s.end(), e);
while (rit != rend) {
instance_line = rit->str();
std::regex e_instance_line("([\\\\\\.\\w]+)\\s+([\\\\\\.\\w]+)\\s*\\(((?:.|\\s)*?)\\);");
if (std::regex_match(instance_line, sm, e_instance_line)) {
string gate_type = sm[1];
string instance_name = sm[2];
string port_info = sm[3];
if (gate_type != "module") {
node* new_node = add_node(instance_name, gate_type, map_module, map_cell);
vector<string> pin_list;
vector<string> wire_list;
std::regex e_port_info("\\.([\\\\\\[\\]\\w]+)\\(\\s*([\\\\\\[\\]\\w]+)\\s*\\)");
std::regex_iterator<std::string::iterator> it_port_info(port_info.begin(), port_info.end(), e_port_info);
while (it_port_info != rend) {
string single_port = it_port_info->str();
smatch sm_single_port;
if (std::regex_match(single_port, sm_single_port, e_port_info)) {
connect_wire(get_net(sm_single_port[2]), new_node, sm_single_port[1]);
}
it_port_info++;
}
}
}
rit++;
}
commit();
}
catch (std::exception &e) {
cerr << "reading module faild. (read_module)\n";
cerr << "description: " << e.what();
destroy();
return false;
}
return true;
}