int checkboard(void) { static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; u8 cfg_rcw_src1, cfg_rcw_src2; u16 cfg_rcw_src; u8 sd1refclk_sel; puts("Board: LS1046ARDB, boot from "); cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); cpld_rev_bit(&cfg_rcw_src1); cfg_rcw_src = cfg_rcw_src1; cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; if (cfg_rcw_src == 0x44) printf("QSPI vBank %d\n", CPLD_READ(vbank)); else if (cfg_rcw_src == 0x40) puts("SD\n"); else puts("Invalid setting of SW5\n"); printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); puts("SERDES Reference Clocks:\n"); sd1refclk_sel = CPLD_READ(sd1refclk_sel); printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); return 0; }
void cpld_set_sd(void) { u16 reg = CPLD_CFG_RCW_SRC_SD; u8 reg5 = (u8)(reg >> 1); u8 reg6 = (u8)(reg & 1); cpld_rev_bit(®5); CPLD_WRITE(soft_mux_on, 1); CPLD_WRITE(cfg_rcw_src1, reg5); CPLD_WRITE(cfg_rcw_src2, reg6); CPLD_WRITE(system_rst, 1); }
int checkboard(void) { static const char *freq[3] = {"100.00MHZ", "156.25MHZ"}; #ifndef CONFIG_SD_BOOT u8 cfg_rcw_src1, cfg_rcw_src2; u32 cfg_rcw_src; #endif u32 sd1refclk_sel; printf("Board: LS1043ARDB, boot from "); #ifdef CONFIG_SD_BOOT puts("SD\n"); #else cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); cpld_rev_bit(&cfg_rcw_src1); cfg_rcw_src = cfg_rcw_src1; cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; if (cfg_rcw_src == 0x25) printf("vBank %d\n", CPLD_READ(vbank)); else if (cfg_rcw_src == 0x106) puts("NAND\n"); else printf("Invalid setting of SW4\n"); #endif printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); puts("SERDES Reference Clocks:\n"); sd1refclk_sel = CPLD_READ(sd1refclk_sel); printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); return 0; }