void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0) { uintptr_t ra = GETPC(); uint64_t oldv, cmpv, newv; int eflags; eflags = cpu_cc_compute_all(env, CC_OP); cmpv = deposit64(env->regs[R_EAX], 32, 32, env->regs[R_EDX]); newv = deposit64(env->regs[R_EBX], 32, 32, env->regs[R_ECX]); oldv = cpu_ldq_data_ra(env, a0, ra); newv = (cmpv == oldv ? newv : oldv); /* always do the store */ cpu_stq_data_ra(env, a0, newv, ra); if (oldv == cmpv) { eflags |= CC_Z; } else { env->regs[R_EAX] = (uint32_t)oldv; env->regs[R_EDX] = (uint32_t)(oldv >> 32); eflags &= ~CC_Z; } CC_SRC = eflags; }
void helper_cmpxchg16b(CPUX86State *env, target_ulong a0) { uintptr_t ra = GETPC(); if ((a0 & 0xf) != 0) { raise_exception_ra(env, EXCP0D_GPF, ra); } else { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else int eflags = cpu_cc_compute_all(env, CC_OP); Int128 cmpv = int128_make128(env->regs[R_EAX], env->regs[R_EDX]); Int128 newv = int128_make128(env->regs[R_EBX], env->regs[R_ECX]); int mem_idx = cpu_mmu_index(env, false); TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); Int128 oldv = helper_atomic_cmpxchgo_le_mmu(env, a0, cmpv, newv, oi, ra); if (int128_eq(oldv, cmpv)) { eflags |= CC_Z; } else { env->regs[R_EAX] = int128_getlo(oldv); env->regs[R_EDX] = int128_gethi(oldv); eflags &= ~CC_Z; } CC_SRC = eflags; #endif } }
void helper_cmpxchg16b(CPUX86State *env, target_ulong a0) { uint64_t d0, d1; int eflags; if ((a0 & 0xf) != 0) { raise_exception(env, EXCP0D_GPF); } eflags = cpu_cc_compute_all(env, CC_OP); d0 = cpu_ldq_data(env, a0); d1 = cpu_ldq_data(env, a0 + 8); if (d0 == EAX && d1 == EDX) { cpu_stq_data(env, a0, EBX); cpu_stq_data(env, a0 + 8, ECX); eflags |= CC_Z; } else { /* always do the store */ cpu_stq_data(env, a0, d0); cpu_stq_data(env, a0 + 8, d1); EDX = d1; EAX = d0; eflags &= ~CC_Z; } CC_SRC = eflags; }
target_ulong helper_read_eflags(CPUX86State *env) { uint32_t eflags; eflags = cpu_cc_compute_all(env, CC_OP); eflags |= (env->df & DF_MASK); eflags |= env->eflags & ~(VM_MASK | RF_MASK); return eflags; }
void helper_into(CPUX86State *env, int next_eip_addend) { int eflags; eflags = cpu_cc_compute_all(env, CC_OP); if (eflags & CC_O) { raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend); } }
void helper_cmpxchg8b(CPUX86State *env, target_ulong a0) { uint64_t d; int eflags; eflags = cpu_cc_compute_all(env, CC_OP); d = cpu_ldq_data(env, a0); if (d == (((uint64_t)EDX << 32) | (uint32_t)EAX)) { cpu_stq_data(env, a0, ((uint64_t)ECX << 32) | (uint32_t)EBX); eflags |= CC_Z; } else { /* always do the store */ cpu_stq_data(env, a0, d); EDX = (uint32_t)(d >> 32); EAX = (uint32_t)d; eflags &= ~CC_Z; } CC_SRC = eflags; }
void helper_cmpxchg8b(CPUX86State *env, target_ulong a0) { #ifdef CONFIG_ATOMIC64 uint64_t oldv, cmpv, newv; int eflags; eflags = cpu_cc_compute_all(env, CC_OP); cmpv = deposit64(env->regs[R_EAX], 32, 32, env->regs[R_EDX]); newv = deposit64(env->regs[R_EBX], 32, 32, env->regs[R_ECX]); #ifdef CONFIG_USER_ONLY { uint64_t *haddr = g2h(a0); cmpv = cpu_to_le64(cmpv); newv = cpu_to_le64(newv); oldv = atomic_cmpxchg__nocheck(haddr, cmpv, newv); oldv = le64_to_cpu(oldv); } #else { uintptr_t ra = GETPC(); int mem_idx = cpu_mmu_index(env, false); TCGMemOpIdx oi = make_memop_idx(MO_TEQ, mem_idx); oldv = helper_atomic_cmpxchgq_le_mmu(env, a0, cmpv, newv, oi, ra); } #endif if (oldv == cmpv) { eflags |= CC_Z; } else { env->regs[R_EAX] = (uint32_t)oldv; env->regs[R_EDX] = (uint32_t)(oldv >> 32); eflags &= ~CC_Z; } CC_SRC = eflags; #else cpu_loop_exit_atomic(ENV_GET_CPU(env), GETPC()); #endif /* CONFIG_ATOMIC64 */ }
void helper_cmpxchg16b_unlocked(CPUX86State *env, target_ulong a0) { uintptr_t ra = GETPC(); Int128 oldv, cmpv, newv; uint64_t o0, o1; int eflags; bool success; if ((a0 & 0xf) != 0) { raise_exception_ra(env, EXCP0D_GPF, GETPC()); } eflags = cpu_cc_compute_all(env, CC_OP); cmpv = int128_make128(env->regs[R_EAX], env->regs[R_EDX]); newv = int128_make128(env->regs[R_EBX], env->regs[R_ECX]); o0 = cpu_ldq_data_ra(env, a0 + 0, ra); o1 = cpu_ldq_data_ra(env, a0 + 8, ra); oldv = int128_make128(o0, o1); success = int128_eq(oldv, cmpv); if (!success) { newv = oldv; } cpu_stq_data_ra(env, a0 + 0, int128_getlo(newv), ra); cpu_stq_data_ra(env, a0 + 8, int128_gethi(newv), ra); if (success) { eflags |= CC_Z; } else { env->regs[R_EAX] = int128_getlo(oldv); env->regs[R_EDX] = int128_gethi(oldv); eflags &= ~CC_Z; } CC_SRC = eflags; }