uint16 cpu_get_src_reg (sim_cpu* cpu, uint8 reg) { switch (reg) { case 0: return cpu_get_a (cpu); case 1: return cpu_get_b (cpu); case 2: return cpu_get_ccr (cpu); case 3: return cpu_get_tmp3 (cpu); case 4: return cpu_get_d (cpu); case 5: return cpu_get_x (cpu); case 6: return cpu_get_y (cpu); case 7: return cpu_get_sp (cpu); default: return 0; } }
int sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length) { sim_cpu *cpu; uint16 val; int size = 2; cpu = STATE_CPU (sd, 0); switch (rn) { case A_REGNUM: val = cpu_get_a (cpu); size = 1; break; case B_REGNUM: val = cpu_get_b (cpu); size = 1; break; case D_REGNUM: val = cpu_get_d (cpu); break; case X_REGNUM: val = cpu_get_x (cpu); break; case Y_REGNUM: val = cpu_get_y (cpu); break; case SP_REGNUM: val = cpu_get_sp (cpu); break; case PC_REGNUM: val = cpu_get_pc (cpu); break; case PSW_REGNUM: val = cpu_get_ccr (cpu); size = 1; break; case PAGE_REGNUM: val = cpu_get_page (cpu); size = 1; break; default: val = 0; break; } if (size == 1) { memory[0] = val; } else { memory[0] = val >> 8; memory[1] = val & 0x0FF; } return size; }
static int m68hc11_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) { uint16 val; int size = 2; switch (rn) { case A_REGNUM: val = cpu_get_a (cpu); size = 1; break; case B_REGNUM: val = cpu_get_b (cpu); size = 1; break; case D_REGNUM: val = cpu_get_d (cpu); break; case X_REGNUM: val = cpu_get_x (cpu); break; case Y_REGNUM: val = cpu_get_y (cpu); break; case SP_REGNUM: val = cpu_get_sp (cpu); break; case PC_REGNUM: val = cpu_get_pc (cpu); break; case PSW_REGNUM: val = cpu_get_ccr (cpu); size = 1; break; case PAGE_REGNUM: val = cpu_get_page (cpu); size = 1; break; default: val = 0; break; } if (size == 1) { memory[0] = val; } else { memory[0] = val >> 8; memory[1] = val & 0x0FF; } return size; }