static void pic_irq_request(void *opaque, int irq, int level)
{
CPUState *env = first_cpu;
DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
if (env->apic_state) {
while (env) {
if (apic_accept_pic_intr(env->apic_state)) {
apic_deliver_pic_intr(env->apic_state, level);
}
env = env->next_cpu;
}
} else {
if (level)
cpu_interrupt(env, CPU_INTERRUPT_HARD);
else
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
}
}
void cpu_check_irqs(CPUState *env)
{
if (env->pil_in && (env->interrupt_index == 0 ||
(env->interrupt_index & ~15) == TT_EXTINT)) {
unsigned int i;
for (i = 15; i > 0; i--) {
if (env->pil_in & (1 << i)) {
int old_interrupt = env->interrupt_index;
env->interrupt_index = TT_EXTINT | i;
if (old_interrupt != env->interrupt_index)
cpu_interrupt(env, CPU_INTERRUPT_HARD);
break;
}
}
} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
env->interrupt_index = 0;
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
}
}
static void typhoon_set_timer_irq(void *opaque, int irq, int level)
{
TyphoonState *s = opaque;
int i;
/* Thankfully, the mc146818rtc code doesn't track the IRQ state,
and so we don't have to worry about missing interrupts just
because we never actually ACK the interrupt. Just ignore any
case of the interrupt level going low. */
if (level == 0) {
return;
}
/* Deliver the interrupt to each CPU, considering each CPU's IIC. */
for (i = 0; i < 4; ++i) {
AlphaCPU *cpu = s->cchip.cpu[i];
if (cpu != NULL) {
uint32_t iic = s->cchip.iic[i];
/* ??? The verbage in Section 10.2.2.10 isn't 100% clear.
Bit 24 is the OverFlow bit, RO, and set when the count
decrements past 0. When is OF cleared? My guess is that
OF is actually cleared when the IIC is written, and that
the ICNT field always decrements. At least, that's an
interpretation that makes sense, and "allows the CPU to
determine exactly how mant interval timer ticks were
skipped". At least within the next 4M ticks... */
iic = ((iic - 1) & 0x1ffffff) | (iic & 0x1000000);
s->cchip.iic[i] = iic;
if (iic & 0x1000000) {
/* Set the ITI bit for this cpu. */
s->cchip.misc |= 1 << (i + 4);
/* And signal the interrupt. */
cpu_interrupt(CPU(cpu), CPU_INTERRUPT_TIMER);
}
}
}
}
static void s5l8930_iop_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
s5l8930_iop_s *s = (s5l8930_iop_s *)opaque;
//fprintf(stderr, "%s:%s: offset 0x%08x value 0x%08x isARM7_CPU 0x%p\n", __FUNCTION__, s->name, offset, value, get_current_cpu());
//cpu_synchronize_all_states();
switch(offset) {
case 0x18:
case 0x1c:
case 0x24:
return;
case 0x100:
if(value & 0x10) { /* Stop CPU ? */
s->status |= 0x2;
break;
}
if(value & 0x1) {
fprintf(stderr, "switching cpu state to start IOP processing @ address 0x%08x\n", s->startaddr);
cpu_interrupt(s->s5l8930env, CPU_INTERRUPT_HALT);
//pause_all_vcpus();
//switch_iop_mode(s->env, ARM_MODE_IOP);
run_on_cpu(s->iopenv, do_iop_run, s);
//s->iopenv->regs[15] = s->startaddr;
//resume_all_vcpus();
}
s->status = value;
break;
case 0x110:
s->startaddr = value;
break;
default:
fprintf(stderr, "%s:%s: UNKNOWN offset 0x%08x value 0x%08x isARM7_CPU 0x%p\n", __FUNCTION__, s->name, offset, value, get_current_cpu());
break;
}
}
static void cpu_set_ivec_irq(void *opaque, int irq, int level)
{
CPUSPARCState *env = opaque;
if (level) {
if (!(env->ivec_status & 0x20)) {
CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
env->halted = 0;
env->interrupt_index = TT_IVEC;
env->ivec_status |= 0x20;
env->ivec_data[0] = (0x1f << 6) | irq;
env->ivec_data[1] = 0;
env->ivec_data[2] = 0;
cpu_interrupt(env, CPU_INTERRUPT_HARD);
}
} else {
if (env->ivec_status & 0x20) {
CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
env->ivec_status &= ~0x20;
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
}
}
}
void check_interrupts(CPUXtensaState *env)
{
int minlevel = xtensa_get_cintlevel(env);
uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];
int level;
/* If the CPU is halted advance CCOUNT according to the vm_clock time
* elapsed since the moment when it was advanced last time.
*/
if (env->halted) {
int64_t now = qemu_get_clock_ns(vm_clock);
xtensa_advance_ccount(env,
muldiv64(now - env->halt_clock,
env->config->clock_freq_khz, 1000000));
env->halt_clock = now;
}
for (level = env->config->nlevel; level > minlevel; --level) {
if (env->config->level_mask[level] & int_set_enabled) {
env->pending_irq_level = level;
cpu_interrupt(env, CPU_INTERRUPT_HARD);
qemu_log_mask(CPU_LOG_INT,
"%s level = %d, cintlevel = %d, "
"pc = %08x, a0 = %08x, ps = %08x, "
"intset = %08x, intenable = %08x, "
"ccount = %08x\n",
__func__, level, xtensa_get_cintlevel(env),
env->pc, env->regs[0], env->sregs[PS],
env->sregs[INTSET], env->sregs[INTENABLE],
env->sregs[CCOUNT]);
return;
}
}
env->pending_irq_level = 0;
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
}
static void cchip_write(void *opaque, hwaddr addr,
uint64_t v32, unsigned size)
{
TyphoonState *s = opaque;
CPUState *cpu_single_cpu = CPU(alpha_env_get_cpu(cpu_single_env));
uint64_t val, oldval, newval;
if (addr & 4) {
val = v32 << 32 | s->latch_tmp;
addr ^= 4;
} else {
s->latch_tmp = v32;
return;
}
switch (addr) {
case 0x0000:
/* CSC: Cchip System Configuration Register. */
/* All sorts of data here; nothing relevant RW. */
break;
case 0x0040:
/* MTR: Memory Timing Register. */
/* All sorts of stuff related to real DRAM. */
break;
case 0x0080:
/* MISC: Miscellaneous Register. */
newval = oldval = s->cchip.misc;
newval &= ~(val & 0x10000ff0); /* W1C fields */
if (val & 0x100000) {
newval &= ~0xff0000ull; /* ACL clears ABT and ABW */
} else {
newval |= val & 0x00f00000; /* ABT field is W1S */
if ((newval & 0xf0000) == 0) {
newval |= val & 0xf0000; /* ABW field is W1S iff zero */
}
}
newval |= (val & 0xf000) >> 4; /* IPREQ field sets IPINTR. */
newval &= ~0xf0000000000ull; /* WO and RW fields */
newval |= val & 0xf0000000000ull;
s->cchip.misc = newval;
/* Pass on changes to IPI and ITI state. */
if ((newval ^ oldval) & 0xff0) {
int i;
for (i = 0; i < 4; ++i) {
AlphaCPU *cpu = s->cchip.cpu[i];
if (cpu != NULL) {
CPUState *cs = CPU(cpu);
/* IPI can be either cleared or set by the write. */
if (newval & (1 << (i + 8))) {
cpu_interrupt(cs, CPU_INTERRUPT_SMP);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_SMP);
}
/* ITI can only be cleared by the write. */
if ((newval & (1 << (i + 4))) == 0) {
cpu_reset_interrupt(cs, CPU_INTERRUPT_TIMER);
}
}
}
}
break;
case 0x00c0:
/* MPD: Memory Presence Detect Register. */
break;
case 0x0100: /* AAR0 */
case 0x0140: /* AAR1 */
case 0x0180: /* AAR2 */
case 0x01c0: /* AAR3 */
/* AAR: Array Address Register. */
/* All sorts of information about DRAM. */
break;
case 0x0200: /* DIM0 */
/* DIM: Device Interrupt Mask Register, CPU0. */
s->cchip.dim[0] = val;
cpu_irq_change(s->cchip.cpu[0], val & s->cchip.drir);
break;
case 0x0240: /* DIM1 */
/* DIM: Device Interrupt Mask Register, CPU1. */
s->cchip.dim[0] = val;
cpu_irq_change(s->cchip.cpu[1], val & s->cchip.drir);
break;
case 0x0280: /* DIR0 (RO) */
case 0x02c0: /* DIR1 (RO) */
case 0x0300: /* DRIR (RO) */
break;
case 0x0340:
/* PRBEN: Probe Enable Register. */
break;
case 0x0380: /* IIC0 */
s->cchip.iic[0] = val & 0xffffff;
break;
case 0x03c0: /* IIC1 */
s->cchip.iic[1] = val & 0xffffff;
break;
case 0x0400: /* MPR0 */
case 0x0440: /* MPR1 */
case 0x0480: /* MPR2 */
case 0x04c0: /* MPR3 */
/* MPR: Memory Programming Register. */
break;
case 0x0580:
/* TTR: TIGbus Timing Register. */
/* All sorts of stuff related to interrupt delivery timings. */
break;
case 0x05c0:
/* TDR: TIGbug Device Timing Register. */
break;
case 0x0600:
/* DIM2: Device Interrupt Mask Register, CPU2. */
s->cchip.dim[2] = val;
cpu_irq_change(s->cchip.cpu[2], val & s->cchip.drir);
break;
case 0x0640:
/* DIM3: Device Interrupt Mask Register, CPU3. */
s->cchip.dim[3] = val;
cpu_irq_change(s->cchip.cpu[3], val & s->cchip.drir);
break;
case 0x0680: /* DIR2 (RO) */
case 0x06c0: /* DIR3 (RO) */
break;
case 0x0700: /* IIC2 */
s->cchip.iic[2] = val & 0xffffff;
break;
case 0x0740: /* IIC3 */
s->cchip.iic[3] = val & 0xffffff;
break;
case 0x0780:
/* PWR: Power Management Control. */
break;
case 0x0c00: /* CMONCTLA */
case 0x0c40: /* CMONCTLB */
case 0x0c80: /* CMONCNT01 */
case 0x0cc0: /* CMONCNT23 */
break;
default:
cpu_unassigned_access(cpu_single_cpu, addr, true, false, 0, size);
return;
}
}
static void cpu_halt_signal(void *opaque, int irq, int level)
{
if (level && current_cpu) {
cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
}
}
void cpu_check_irqs(CPUSPARCState *env)
{
CPUState *cs;
uint32_t pil = env->pil_in |
(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
/* We should be holding the BQL before we mess with IRQs */
g_assert(qemu_mutex_iothread_locked());
/* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
if (env->ivec_status & 0x20) {
return;
}
cs = CPU(sparc_env_get_cpu(env));
/* check if TM or SM in SOFTINT are set
setting these also causes interrupt 14 */
if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
pil |= 1 << 14;
}
/* The bit corresponding to psrpil is (1<< psrpil), the next bit
is (2 << psrpil). */
if (pil < (2 << env->psrpil)) {
if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
env->interrupt_index = 0;
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
return;
}
if (cpu_interrupts_enabled(env)) {
unsigned int i;
for (i = 15; i > env->psrpil; i--) {
if (pil & (1 << i)) {
int old_interrupt = env->interrupt_index;
int new_interrupt = TT_EXTINT | i;
if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
&& ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
trace_sparc64_cpu_check_irqs_noset_irq(env->tl,
cpu_tsptr(env)->tt,
new_interrupt);
} else if (old_interrupt != new_interrupt) {
env->interrupt_index = new_interrupt;
trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt,
new_interrupt);
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
}
break;
}
}
} else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
env->interrupt_index);
env->interrupt_index = 0;
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
int gb_tick(gb_t *gb)
{
update_joypad(gb);
if (!cpu_tick(gb))
return 0;
if (!lcd_tick(gb))
return 0;
if (++gb->ticks == TICKS_MAX)
{
ERR("Game Over");
return 0;
}
// DMA
if (gb->mem[IO_DMA] != 0xFF)
{
// XXX instant DMA?
memcpy(&gb->mem[0xFE00], &gb->mem[gb->mem[IO_DMA] << 8], 0xA0);
gb->mem[IO_DMA] = 0xFF;
}
if (++gb->ticks_divider == TICKS_DIVIDER)
{
gb->mem[IO_DIV]++;
gb->ticks_divider = 0;
}
if (gb->mem[IO_TAC] & (1 << 2))
{
// timer ON
unsigned int total_ticks;
switch(gb->mem[IO_TAC] & 3)
{
case 0:
total_ticks = 244;
break;
case 1:
total_ticks = 4;
break;
case 2:
total_ticks = 15;
break;
case 3:
total_ticks = 61;
break;
}
if (++gb->ticks_timer >= total_ticks)
{
gb->ticks_timer = 0;
if (gb->mem[IO_TIMA]++ == 0xFF)
{
//overflow
gb->mem[IO_TIMA] = gb->mem[IO_TMA];
cpu_interrupt(gb, 2);
}
}
}
return 1;
}
static void
microblaze_generic_fdt_reset(MicroBlazeCPU *cpu)
{
CPUMBState *env = &cpu->env;
char node_path[DT_PATH_LENGTH];
qemu_fdt_get_node_by_name(fdt_g, node_path, "cpu");
int t;
int use_exc = 0;
env->pvr.regs[0] = 0;
env->pvr.regs[2] = PVR2_D_OPB_MASK \
| PVR2_D_LMB_MASK \
| PVR2_I_OPB_MASK \
| PVR2_I_LMB_MASK \
| 0;
/* Even if we don't have PVR's, we fill out everything
because QEMU will internally follow what the pvr regs
state about the HW. */
if (VAL("xlnx,use-barrel")) {
env->pvr.regs[0] |= PVR0_USE_BARREL_MASK;
env->pvr.regs[2] |= PVR2_USE_BARREL_MASK;
}
if (VAL("xlnx,use-div")) {
env->pvr.regs[0] |= PVR0_USE_DIV_MASK;
env->pvr.regs[2] |= PVR2_USE_DIV_MASK;
}
t = VAL("xlnx,use-hw-mul");
if (t) {
env->pvr.regs[0] |= PVR0_USE_HW_MUL_MASK;
env->pvr.regs[2] |= PVR2_USE_HW_MUL_MASK;
if (t >= 2) {
env->pvr.regs[2] |= PVR2_USE_MUL64_MASK;
}
}
if (VAL("xlnx,use-msr-instr")) {
env->pvr.regs[2] |= PVR2_USE_MSR_INSTR;
}
if (VAL("xlnx,use-pcmp-instr")) {
env->pvr.regs[2] |= PVR2_USE_PCMP_INSTR;
}
if (VAL("xlnx,opcode-0x0-illegal")) {
env->pvr.regs[2] |= PVR2_OPCODE_0x0_ILL_MASK;
}
if (VAL("xlnx,unaligned-exceptions")) {
env->pvr.regs[2] |= PVR2_UNALIGNED_EXC_MASK;
use_exc = 1;
}
if (VAL("xlnx,ill-opcode-exception")) {
env->pvr.regs[2] |= PVR2_ILL_OPCODE_EXC_MASK;
use_exc = 1;
}
if (VAL("xlnx,iopb-bus-exception")) {
env->pvr.regs[2] |= PVR2_IOPB_BUS_EXC_MASK;
use_exc = 1;
}
if (VAL("xlnx,dopb-bus-exception")) {
env->pvr.regs[2] |= PVR2_DOPB_BUS_EXC_MASK;
use_exc = 1;
}
if (VAL("xlnx,div-zero-exception")) {
env->pvr.regs[2] |= PVR2_DIV_ZERO_EXC_MASK;
use_exc = 1;
}
env->pvr.regs[0] |= VAL("xlnx,pvr-user1") & 0xff;
env->pvr.regs[1] = VAL("xlnx,pvr-user2");
/* MMU regs. */
t = VAL("xlnx,use-mmu");
if (use_exc || t) {
env->pvr.regs[0] |= PVR0_USE_EXC_MASK ;
}
env->pvr.regs[11] = t << 30;
t = VAL("xlnx,mmu-zones");
env->pvr.regs[11] |= t << 17;
env->mmu.c_mmu_zones = t;
t = VAL("xlnx,mmu-tlb-access");
env->mmu.c_mmu_tlb_access = t;
env->pvr.regs[11] |= t << 22;
{
char *str;
const struct {
const char *name;
unsigned int arch;
} arch_lookup[] = {
{"virtex2", 0x4},
{"virtex2pro", 0x5},
{"spartan3", 0x6},
{"virtex4", 0x7},
{"virtex5", 0x8},
{"spartan3e", 0x9},
{"spartan3a", 0xa},
{"spartan3an", 0xb},
{"spartan3adsp", 0xc},
{"spartan6", 0xd},
{"virtex6", 0xe},
{"virtex7", 0xf},
{"kintex7", 0x10},
{"artix7", 0x11},
{"zynq7000", 0x12},
{"spartan2", 0xf0},
{NULL, 0},
};
unsigned int i = 0;
str = qemu_fdt_getprop(fdt_g, node_path, "xlnx,family", NULL, false, NULL);
while (arch_lookup[i].name && str) {
if (strcmp(arch_lookup[i].name, str) == 0) {
break;
}
i++;
}
if (!str || !arch_lookup[i].arch) {
env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family. */
} else {
env->pvr.regs[10] = arch_lookup[i].arch << 24;
}
g_free(str);
}
{
env->pvr.regs[4] = PVR4_USE_ICACHE_MASK
| (21 << 26) /* Tag size. */
| (4 << 21)
| (11 << 16);
env->pvr.regs[6] = VAL("d-cache-baseaddr");
env->pvr.regs[7] = VAL("d-cache-highaddr");
env->pvr.regs[5] = PVR5_USE_DCACHE_MASK
| (21 << 26) /* Tag size. */
| (4 << 21)
| (11 << 16);
if (VAL("xlnx,dcache-use-writeback")) {
env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK;
}
env->pvr.regs[8] = VAL("i-cache-baseaddr");
env->pvr.regs[9] = VAL("i-cache-highaddr");
}
if (VAL("qemu,halt")) {
cpu_interrupt(ENV_GET_CPU(env), CPU_INTERRUPT_HALT);
}
}
