/* ------------------------------------------------------------------------*//**
* @FUNCTION clk_am335x_sysclk_rate_get
* @BRIEF Return the mandatory system clock speed, in MHz.
* @RETURNS > 0 system clock speed, in MHz.
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_UNEXPECTED
* @param[in] none
* @DESCRIPTION Return the mandatory system clock speed, in MHz.
*//*------------------------------------------------------------------------ */
double clk_am335x_sysclk_rate_get(void)
{
unsigned int reg_val;
static double sysclk = 0.0;
sysclk_am335x_id sysclk_id;
if (!cpu_is_am335x())
return (double) OMAPCONF_ERR_CPU;
if (sysclk > 0.0) {
dprintf("%s(): sysclk rate=%.1lfMHz\n", __func__, sysclk);
return sysclk;
}
if (!mem_fake_access_get()) {
mem_read(AM335X_STATUS, ®_val);
sysclk_id = extract_bitfield(reg_val, 22, 2);
} else {
sysclk_id = SYSCLK_AM335X_19_2_MHZ; /* AM335X EVM PoR */
}
sysclk = sysclk_am335x_rate_table[sysclk_id];
if (sysclk == 0.0) {
fprintf(stderr, "%s(): bad CONTROL_STATUS value(%d)\n",
__func__, sysclk_id);
sysclk = (double) OMAPCONF_ERR_UNEXPECTED;
} else {
dprintf("%s(): CONTROL_STATUS=0x%x, sysclk rate=%.1lfMHz\n",
__func__, sysclk_id, sysclk);
}
return sysclk;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION powerdm_deinit
* @BRIEF free dynamically allocated internal data.
* @DESCRIPTION free dynamically allocated internal data.
* MUST BE CALLED AT END OF EXECUTION.
*//*------------------------------------------------------------------------ */
void powerdm_deinit(void)
{
if (cpu_is_omap44xx()) {
pwrdm44xx_deinit();
} else if (cpu_is_omap54xx()) {
pwrdm54xx_deinit();
} else if (cpu_is_am335x()) {
pwrdm_am335x_deinit();
} else {
fprintf(stderr,
"omapconf: %s(): cpu not supported!!!\n", __func__);
}
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION powerdm_count_get
* @BRIEF return the number of power domains
* @RETURNS number of power domains (> 0) in case of success
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_ARG
* @DESCRIPTION return the number of power domains
*//*------------------------------------------------------------------------ */
int powerdm_count_get(void)
{
if (cpu_is_omap44xx()) {
return pwrdm44xx_count_get();
} else if (cpu_is_omap54xx()) {
return pwrdm54xx_count_get();
} else if (cpu_is_am335x()) {
return pwrdm_am335x_count_get();
} else {
fprintf(stderr,
"omapconf: %s(): cpu not supported!!!\n", __func__);
return OMAPCONF_ERR_CPU;
}
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION powerdm_list_get
* @BRIEF return the list of power domains
* @RETURNS list of power domains in case of success
* NULL in case of error
* @DESCRIPTION return the list of power domains
*//*------------------------------------------------------------------------ */
const genlist *powerdm_list_get(void)
{
if (cpu_is_omap44xx()) {
return pwrdm44xx_list_get();
} else if (cpu_is_omap54xx()) {
return pwrdm54xx_list_get();
} else if (cpu_is_am335x()) {
return pwrdm_am335x_list_get();
} else {
fprintf(stderr,
"omapconf: %s(): cpu not supported!!!\n", __func__);
return NULL;
}
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION cpu_die_id_get
* @BRIEF return SoC DIE ID (4x 32-bit integers, string).
* @RETURNS OMAP DIE ID string (as "DIEID3-DIEID2-DIEID1-DIEID0")
* NULL in case of error
* @param[in,out] die_id_3: DIE ID (part 3, MSB)
* @param[in,out] die_id_2: DIE ID (part 2)
* @param[in,out] die_id_1: DIE ID (part 1)
* @param[in,out] die_id_0: DIE ID (part 0, LSB)
* @param[in,out] die_id: DIE ID string ("DIEID3-DIEID2-DIEID1-DIEID0")
* @DESCRIPTION return SoC DIE ID (4x 32-bit integers, string).
*//*------------------------------------------------------------------------ */
char *cpu_die_id_get(unsigned int *die_id_3, unsigned int *die_id_2,
unsigned int *die_id_1, unsigned int *die_id_0,
char die_id[CPU_DIE_ID_LENGTH])
{ unsigned int die_id_add_3;
unsigned int die_id_add_2;
unsigned int die_id_add_1;
unsigned int die_id_add_0;
CHECK_NULL_ARG(die_id, NULL);
/*
* The DIE ID for the AM335X is TI proprietary information
* NULL is returned since it cannot be shown
*/
if (cpu_is_am335x() || cpu_is_am437x())
return NULL;
if (cpu_get() == DRA_75X || cpu_get() == DRA_72X) {
die_id_add_3 = DRA7_CONTROL_STD_FUSE_DIE_ID_3;
die_id_add_2 = DRA7_CONTROL_STD_FUSE_DIE_ID_2;
die_id_add_1 = DRA7_CONTROL_STD_FUSE_DIE_ID_1;
die_id_add_0 = DRA7_CONTROL_STD_FUSE_DIE_ID_0;
} else {
die_id_add_3 = CONTROL_STD_FUSE_DIE_ID_3;
die_id_add_2 = CONTROL_STD_FUSE_DIE_ID_2;
die_id_add_1 = CONTROL_STD_FUSE_DIE_ID_1;
die_id_add_0 = CONTROL_STD_FUSE_DIE_ID_0;
}
if (mem_read(die_id_add_3, die_id_3) != 0)
return NULL;
dprintf("%s(): die_id_3 = 0x%08X\n", __func__, *die_id_3);
if (mem_read(die_id_add_2, die_id_2) != 0)
return NULL;
dprintf("%s(): die_id_2 = 0x%08X\n", __func__, *die_id_2);
if (mem_read(die_id_add_1, die_id_1) != 0)
return NULL;
dprintf("%s(): die_id_1 = 0x%08X\n", __func__, *die_id_1);
if (mem_read(die_id_add_0, die_id_0) != 0)
return NULL;
dprintf("%s(): die_id_0 = 0x%08X\n", __func__, *die_id_0);
sprintf(die_id, "%08X-%08X-%08X-%08X",
*die_id_3, *die_id_2, *die_id_1, *die_id_0);
dprintf("%s(): die_id = %s\n", __func__, die_id);
return die_id;
}
static int tlc59108_probe(struct i2c_client *c, const struct i2c_device_id *id)
{
struct backlight_properties props;
struct tlc59108_bl *data = kzalloc(sizeof(struct tlc59108_bl),
GFP_KERNEL);
int ret = 0;
if (!data)
return -ENOMEM;
i2c_set_clientdata(c, data);
data->client = c;
/* FIXME: This is definitely how it should be done.
* Someone more familiar with the framework needs to make it proper
*/
if (cpu_is_am335x()) {
/* Set LED4 to always on in LEDOUT1 Register*/
ret = i2c_smbus_write_byte_data(data->client, TLC59108_LEDOUT1, 0x01);
if(ret < 0)
pr_err("Could not set LED4 to fully on\n");
}
memset(&props, 0, sizeof(struct backlight_properties));
props.max_brightness = TLC59108_MAX_BRIGHTNESS;
props.type = BACKLIGHT_RAW;
data->bl = backlight_device_register("tlc59108-bl", &c->dev, data,
&bl_ops, &props);
if (IS_ERR(data->bl)) {
ret = PTR_ERR(data->bl);
goto err_reg;
}
data->bl->props.brightness = TLC59108_MAX_BRIGHTNESS;
backlight_update_status(data->bl);
return 0;
err_reg:
data->bl = NULL;
kfree(data);
return ret;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION cpu_silicon_max_speed_get
* @BRIEF return silicon max speed
* @RETURNS Silicon max speed (in MHz)
* 0 in case of error
* @param[in] none
* @DESCRIPTION return silicon max speed
* (depending on cpu type and silicon type)
*//*------------------------------------------------------------------------ */
unsigned int cpu_silicon_max_speed_get(void)
{
unsigned int max_speed;
if (cpu_is_omap44xx()) {
max_speed = cpu44xx_silicon_max_speed_get();
} else if (cpu_is_omap54xx()) {
max_speed = cpu54xx_silicon_max_speed_get();
} else if (cpu_is_dra7xx()) {
max_speed = cpu_dra7xx_silicon_max_speed_get();
} else if(cpu_is_am335x()) {
max_speed = cpu_am335x_silicon_max_speed_get();
} else if(cpu_is_am437x()) {
max_speed = cpu_am437x_silicon_max_speed_get();
} else {
dprintf("%s(): unknown architecture!\n", __func__);
max_speed = 0;
}
dprintf("%s(): max speed = %dMHz\n", __func__, max_speed);
return max_speed;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION powerdm_init
* @BRIEF initialize internal data
* @DESCRIPTION initialize internal data (architecture dependent)
*//*------------------------------------------------------------------------ */
void powerdm_init(void)
{
#ifdef PWRDM_DEBUG
int i, count;
const genlist *pwrdm_list;
powerdm_info pwrdm;
#endif
if (cpu_is_omap44xx()) {
pwrdm44xx_init();
} else if (cpu_is_omap54xx()) {
pwrdm54xx_init();
} else if (cpu_is_am335x()) {
pwrdm_am335x_init();
} else {
fprintf(stderr,
"omapconf: %s(): cpu not supported!!!\n", __func__);
}
#ifdef PWRDM_DEBUG
pwrdm_list = powerdm_list_get();
count = genlist_getcount((genlist *) pwrdm_list);
printf("Power Domain List:\n");
for (i = 0; i < count; i++) {
genlist_get((genlist *) pwrdm_list, i, (powerdm_info *) &pwrdm);
printf(" %s:\n", pwrdm.name);
printf(" ID:%d\n", pwrdm.id);
printf(" VoltDM: %s\n", pwrdm.voltdm);
printf(" PWRSTCTRL REG: %s\n", (pwrdm.pwrstctrl)->name);
printf(" PWRSTST REG: %s\n", (pwrdm.pwrstst)->name);
printf(" Properties: %d\n", pwrdm.properties);
printf("\n\n");
}
printf("Power Domain count: %d\n\n", count);
#endif
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION pmic_detect
* @BRIEF detect platform PMIC chip(s) and retrieve PMIC details.
* @RETURNS 0
* @DESCRIPTION detect platform PMIC chip(s) and retrieve PMIC details.
*//*------------------------------------------------------------------------ */
int pmic_detect(void)
{
unsigned short is_twl6030, is_twl6032, is_twl6034, is_twl6035,
tps62361_present, tps659038_present, tps65217x_present;
if (pmic_detection_done())
return 0;
is_twl6030 = twl603x_is_twl6030();
is_twl6032 = twl603x_is_twl6032();
is_twl6034 = twl603x_is_twl6034();
is_twl6035 = twl603x_is_twl6035();
tps62361_present = tps62361_is_present();
tps659038_present = tps659038_is_present();
tps65217x_present = tps65217x_is_present();
dprintf(
"%s(): is_twl6030=%u is_twl6032=%u is_tps62361=%u "
"is_twl6034=%u is_twl6035=%u is_tps659038=%u is_tps65217x=%u\n",
__func__, is_twl6030,
is_twl6032, tps62361_present, is_twl6034, is_twl6035,
tps659038_present, tps65217x_present);
/*
* Detect PMIC powering VDD_MPU rail:
* OMAP4: can be either TWL6030, TWL6032, TWL6034 or TPS62361.
* OMAP5: TWL6035
* DRA7: TPS659038
* AM335X: TPS65217X
*/
pmic_smps_init(PMIC_SMPS_MPU, is_twl6030, is_twl6032, is_twl6034, is_twl6035,
tps62361_present, tps659038_present, tps65217x_present);
/*
* Detect PMIC powering VDD_[IVA-MM] rail:
* OMAP4: can be either TWL6030 or TWL6032 or TWL6034.
* OMAP5: TWL6035
* DRA7: TPS659038
* AM335X: N/A.
*/
pmic_smps_init(PMIC_SMPS_MM, is_twl6030, is_twl6032, is_twl6034, is_twl6035,
tps62361_present, tps659038_present, tps65217x_present);
/*
* Detect PMIC powering VDD_CORE rail:
* OMAP4: can be either TWL6030 or TWL6032 or TWL6034.
* OMAP5: TWL6035
* DRA7: TPS659038
* AM335X: TPS65217X
*/
pmic_smps_init(PMIC_SMPS_CORE, is_twl6030, is_twl6032, is_twl6034, is_twl6035,
tps62361_present, tps659038_present, tps65217x_present);
/*
* Detect PMIC powering VDD_GPU, DSPEVE rail:
* OMAP4 & OMAP5: N/A.
* DRA7: TPS659038
* AM335X: N/A.
*/
if (cpu_get() == DRA_75X) {
pmic_smps_init(PMIC_SMPS_GPU, is_twl6030, is_twl6032, is_twl6034, is_twl6035,
tps62361_present, tps659038_present, tps65217x_present);
pmic_smps_init(PMIC_SMPS_DSPEVE, is_twl6030, is_twl6032, is_twl6034, is_twl6035,
tps62361_present, tps659038_present, tps65217x_present);
}
/* Set single-chip flag accordingly */
if (((pmic_chip[PMIC_SMPS_MPU] == pmic_chip[PMIC_SMPS_MM]) &&
(pmic_chip[PMIC_SMPS_MPU] == pmic_chip[PMIC_SMPS_CORE])) ||
cpu_is_am335x()) {
pmic_single_chip_flag = 1;
dprintf("%s(): PMIC is single chip\n", __func__);
} else {
pmic_single_chip_flag = 0;
dprintf("%s(): PMIC is multi-chip\n", __func__);
}
pmic_detection_done_flag = 1;
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION cpu_detect
* @BRIEF Detect cpu and set internal global variables accordingly
* @RETURNS 0 on success
* OMAPCONF_ERR_UNEXPECTED
* OMAPCONF_ERR_CPU if cpu not recognized
* OMAPCONF_ERR_REG_ACCESS
* @param[in] none
* @DESCRIPTION Detect cpu and set internal global variables accordingly
*//*------------------------------------------------------------------------ */
int cpu_detect(void)
{
unsigned int status;
unsigned int efuse;
unsigned int prod_id_1;
int ret;
unsigned char status_bit_start;
#ifdef CPUID_DEBUG
char s[CPU_FULL_NAME_MAX_LENGTH];
char rev_s[CPU_REVISION_MAX_NAME_LENGTH];
char dev_type_s[CPU_DEVICE_TYPE_MAX_NAME_LENGTH];
#endif
/* Init variables */
cpu_init();
/* Retrieve OMAP chip & ES */
/* Determine if device is of the AM or OMAP family */
if (cpu_is_omap())
ret = identify_omap();
else
ret = identify_sitara();
if (ret)
return ret;
dprintf("%s(): Chip is %s ES%s\n", __func__,
cpu_gets(s), cpu_revision_gets(rev_s));
/* Retrieve device type */
if (cpu_is_omap44xx()) {
ret = mem_read(OMAP44XX_STATUS, &status);
status_bit_start = 8;
} else if (cpu_is_omap54xx() || cpu_is_dra7xx()) {
ret = mem_read(OMAP54XX_STATUS, &status);
status_bit_start = 6;
} else if (cpu_is_am335x() || cpu_is_am437x()) {
ret = mem_read(AM335X_STATUS, &status);
status_bit_start = 8;
} else {
ret = -1;
}
if (ret)
return OMAPCONF_ERR_REG_ACCESS;
dprintf("%s(): OMAP44XX_STATUS = 0x%08X\n", __func__, status);
switch (extract_bitfield(status, status_bit_start, 2)) {
case 3:
cpu_device_type_set(DEV_GP);
break;
case 2:
cpu_device_type_set(DEV_HS);
break;
case 1:
cpu_device_type_set(DEV_EMU);
break;
default:
cpu_device_type_set(DEV_TEST);
}
dprintf("%s(): Device Type is %s\n", __func__,
cpu_device_type_gets(dev_type_s));
/* Retrieve silicon performance type from EFuse */
if (cpu_is_omap44xx()) {
if (mem_read(CONTROL_STD_FUSE_PROD_ID_1, &prod_id_1) != 0) {
fprintf(stderr,
"omapconf (%s()): could not read CONTROL_STD_FUSE_PROD_ID_1 register!\n",
__func__);
return OMAPCONF_ERR_REG_ACCESS;
}
dprintf("%s(): CONTROL_STD_FUSE_PROD_ID_1 = 0x%08X\n",
__func__, prod_id_1);
si_type = (silicon_type) extract_bitfield(prod_id_1, 16, 2);
} else if (cpu_is_omap54xx()) {
if (cpu_revision_get() == REV_ES1_0) {
if (cpu_silicon_max_speed_get() != 1200)
cpu_silicon_type_set(STANDARD_PERF_SI);
else
cpu_silicon_type_set(SPEEDBIN_SI);
} else {
if (cpu_silicon_max_speed_get() != 1700)
cpu_silicon_type_set(STANDARD_PERF_SI);
else
cpu_silicon_type_set(SPEEDBIN_SI);
}
} else if (cpu_is_dra7xx()) {
/* TBD: implement true detection when ID data is available */
cpu_silicon_type_set(STANDARD_PERF_SI);
} else if (cpu_is_am335x()){
if (mem_read(EFUSE_SMA_REG, &efuse) != 0) {
fprintf(stderr,
"omapconf: (%s()): could not read EFUSE_SMA register!\n",
__func__);
return OMAPCONF_ERR_REG_ACCESS;
}
switch (extract_bitfield(efuse, 16, 2)) {
case 0:
/*
* Silicon revision 1.0 does not support EFUSE SMA REG
* (returns all 0's if read)
* Setting as unknown until there is an alternate method
*/
cpu_package_type_set(PACKAGE_TYPE_MAX);
break;
case 1:
cpu_package_type_set(ZCZ);
break;
case 2:
cpu_package_type_set(ZCE);
break;
default:
fprintf(stderr,
"omapconf: (%s()): could not identify package type!\n",
__func__);
return OMAPCONF_ERR_UNEXPECTED;
}
}
dprintf("%s(): Silicon performance type is %s (%uMHz)\n",
__func__, cpu_silicon_type_gets(s),
cpu_silicon_max_speed_get());
/* Set CPU full name */
cpu_full_name_set();
dprintf("%s(): CPU full name is %s\n", __func__, cpu_full_name);
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION clk_am335x_rate_get
* @BRIEF convert bitfield value from register into string
* @RETURNS > 0 clock speed in MHz
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_ARG
* @param[in] clk_id: am335x clock id
* @param[in] ignore: do not consider DPLL stop status.
* Useful for functions that needs the DPLL output
* frequencies whatever its status
* (e.g. audit, clock tree, etc)
* @DESCRIPTION convert bitfield value from register into string
*//*------------------------------------------------------------------------ */
double clk_am335x_rate_get(clk_am335x_id clk_id,
unsigned short ignore)
{
unsigned int reg_val;
double src_clk_speed, out_clk_speed;
clk_am335x_id src_clk_id;
double div;
if (!cpu_is_am335x())
return (double) OMAPCONF_ERR_CPU;
switch (clk_id) {
/* 32K CLKS */
case CLK_AM335X_CLK_32KHZ:
mem_read(AM335X_CLK32K_DIVRATIO_CTRL, ®_val);
if (extract_bit(reg_val, 0) == 0)
div = 732.4219;
else
div = 366.2109;
src_clk_id = CLK_AM335X_CLK_24;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed / div;
DPRINT_CLK_SPEED3(clk_id, src_clk_id, src_clk_speed, div,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_CLK_RC32K:
out_clk_speed = AM335X_SYS_32K_SPEED;
DPRINT_CLK_SPEED1(clk_id, out_clk_speed);
return out_clk_speed;
case CLK_AM335X_CLK_32K_RTC:
out_clk_speed = AM335X_EXT_32K_SPEED;
DPRINT_CLK_SPEED1(clk_id, out_clk_speed);
return out_clk_speed;
/* SYS CLKS */
case CLK_AM335X_SYS_CLK:
/* Listed as M_OSC (Master Oscillator) in TRM */
out_clk_speed = clk_am335x_sysclk_rate_get();
DPRINT_CLK_SPEED1(clk_id, out_clk_speed);
return out_clk_speed;
case CLK_AM335X_TCLKIN:
out_clk_speed = AM335X_TCLKIN_SPEED;
DPRINT_CLK_SPEED1(clk_id, out_clk_speed);
return out_clk_speed;
case CLK_AM335X_CLK_48:
src_clk_id = CLK_AM335X_PER_CLKOUTM2;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed / 4;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_CLK_24:
src_clk_id = CLK_AM335X_CLK_48;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed / 2;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_MHZ_250_CLK:
src_clk_id = CLK_AM335X_CORE_CLKOUTM5;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_MHZ_125_CLK:
src_clk_id = CLK_AM335X_CORE_CLKOUTM5;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed / 2;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_MHZ_50_CLK:
src_clk_id = CLK_AM335X_CORE_CLKOUTM5;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed / 5;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_MHZ_5_CLK:
src_clk_id = CLK_AM335X_MHZ_50_CLK;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed / 10;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
/* DPLL CORE OUTPUT CLKS */
case CLK_AM335X_CORE_CLKOUTM4:
src_clk_speed = dpll_am335x_output_rate_get(
DPLL_AM335X_CORE, DPLL_AM335X_CORE_CLKOUT_M4, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2_DPLL(clk_id, "DPLL_CORE CORE_CLKOUT_M4",
src_clk_speed, out_clk_speed);
return out_clk_speed;
case CLK_AM335X_CORE_CLKOUTM5:
src_clk_speed = dpll_am335x_output_rate_get(
DPLL_AM335X_CORE, DPLL_AM335X_CORE_CLKOUT_M5, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2_DPLL(clk_id, "DPLL_CORE CORE_CLKOUT_M5",
src_clk_speed, out_clk_speed);
return out_clk_speed;
case CLK_AM335X_CORE_CLKOUTM6:
src_clk_speed = dpll_am335x_output_rate_get(
DPLL_AM335X_CORE, DPLL_AM335X_CORE_CLKOUT_M6, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2_DPLL(clk_id, "DPLL_CORE CORE_CLKOUT_M6",
src_clk_speed, out_clk_speed);
return out_clk_speed;
case CLK_AM335X_SGX_CORECLK:
reg_val = reg_read(&am335x_clksel_gfx_fclk);
if (extract_bit(reg_val, 1) == 0)
src_clk_id = CLK_AM335X_CORE_CLKOUTM4;
else
src_clk_id = CLK_AM335X_PER_CLKOUTM2;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
div = (double) (1 << extract_bit(reg_val, 0));
out_clk_speed = src_clk_speed / div;
DPRINT_CLK_SPEED3(clk_id, src_clk_id, src_clk_speed, div,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_L3S_CLK:
src_clk_id = CLK_AM335X_CORE_CLKOUTM4;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed / 2;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_L4_PER_CLK:
src_clk_id = CLK_AM335X_CORE_CLKOUTM4;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed / 2;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_L4_WKUPCLK:
src_clk_id = CLK_AM335X_CORE_CLKOUTM4;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed / 2;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_L3F_CLK:
src_clk_id = CLK_AM335X_CORE_CLKOUTM4;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_L4F_CLK:
src_clk_id = CLK_AM335X_CORE_CLKOUTM4;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_PRU_ICSS_IEP_CLK:
src_clk_id = CLK_AM335X_CORE_CLKOUTM4;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_DEBUGSS_CLKA:
src_clk_id = CLK_AM335X_CORE_CLKOUTM4;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_PRU_ICSS_OCP_CLKL:
reg_val = reg_read(&am335x_clksel_pru_icss_ocp_clk);
if (extract_bit(reg_val, 0) == 0)
src_clk_id = CLK_AM335X_CORE_CLKOUTM4;
else
src_clk_id = CLK_AM335X_DISP_CLKOUT;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_CPTS_RFT_CLK:
reg_val = reg_read(&am335x_cm_cpts_rft_clksel);
if (extract_bit(reg_val, 0) == 0)
src_clk_id = CLK_AM335X_CORE_CLKOUTM4;
else
src_clk_id = CLK_AM335X_CORE_CLKOUTM5;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
/* DPLL PER OUTPUT CLKS */
case CLK_AM335X_USB_PHY_CLK:
src_clk_speed = dpll_am335x_output_rate_get(
DPLL_AM335X_PER, DPLL_AM335X_CLKDCOLDO, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2_DPLL(clk_id, "DPLL_PER CLKOUT", src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_PER_CLKOUTM2:
src_clk_speed = dpll_am335x_output_rate_get(
DPLL_AM335X_PER, DPLL_AM335X_CLKOUT, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2_DPLL(clk_id, "DPLL_PER CLKOUT", src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_PRU_ICSS_UART_CLK:
src_clk_id = CLK_AM335X_PER_CLKOUTM2;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_MMC_CLK:
src_clk_id = CLK_AM335X_PER_CLKOUTM2;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed / 2;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_SPI_CLK:
src_clk_id = CLK_AM335X_CLK_48;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_UART_CLK:
src_clk_id = CLK_AM335X_CLK_48;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_I2C_CLK:
src_clk_id = CLK_AM335X_CLK_48;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
/* DPLL MPU OUTPUT CLKS */
case CLK_AM335X_MPU_CLK:
src_clk_speed = dpll_am335x_output_rate_get(
DPLL_AM335X_MPU, DPLL_AM335X_CLKOUT, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2_DPLL(clk_id, "DPLL_MPU CLKOUT", src_clk_speed,
out_clk_speed);
return out_clk_speed;
/* DPLL DISP OUTPUT CLKS */
case CLK_AM335X_DISP_CLKOUT:
src_clk_speed = dpll_am335x_output_rate_get(
DPLL_AM335X_DISP, DPLL_AM335X_CLKOUT, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2_DPLL(clk_id, "DPLL_DISP CLKOUT", src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_LCD_CLK:
reg_val = reg_read(&am335x_clksel_lcdc_pixel_clk);
if (extract_bitfield(reg_val, 0, 2) == 2)
src_clk_id = CLK_AM335X_PER_CLKOUTM2;
else if (extract_bitfield(reg_val, 0, 2) == 1)
src_clk_id = CLK_AM335X_CORE_CLKOUTM5;
else
src_clk_id = CLK_AM335X_DISP_CLKOUT;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
/* DPLL DDR OUTPUT CLKS */
case CLK_AM335X_DDR_CLKOUTM2:
src_clk_speed = dpll_am335x_output_rate_get(
DPLL_AM335X_DDR, DPLL_AM335X_CLKOUT, ignore);
out_clk_speed = src_clk_speed;
DPRINT_CLK_SPEED2_DPLL(clk_id, "DPLL_DDR CLKOUT", src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_EMIF_M_CLK:
src_clk_id = CLK_AM335X_DDR_CLKOUTM2;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed / 2;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_GFX_SYSCLK:
src_clk_id = CLK_AM335X_CORE_CLKOUTM4;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed / 2;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_GFX_MEMCLK:
src_clk_id = CLK_AM335X_CORE_CLKOUTM4;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
out_clk_speed = src_clk_speed / 2;
DPRINT_CLK_SPEED2(clk_id, src_clk_id, src_clk_speed,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_GFX_CORECLK:
reg_val = reg_read(&am335x_clksel_gfx_fclk);
if (extract_bit(reg_val, 1))
src_clk_id = CLK_AM335X_PER_CLKOUTM2;
else
src_clk_id = CLK_AM335X_CORE_CLKOUTM4;
src_clk_speed = clk_am335x_rate_get(src_clk_id, ignore);
if (extract_bit(reg_val, 0))
div = 2;
else
div = 1;
out_clk_speed = src_clk_speed / div;
DPRINT_CLK_SPEED3(clk_id, src_clk_id, src_clk_speed, div,
out_clk_speed);
return out_clk_speed;
case CLK_AM335X_ID_MAX:
out_clk_speed = 0;
DPRINT_CLK_SPEED1(clk_id, out_clk_speed);
return out_clk_speed;
default:
fprintf(stderr, "%s(): invalid clock id %s(%u)!\n",
__func__, clk_am335x_name_table[clk_id], clk_id);
return (double) OMAPCONF_ERR_ARG;
}
return 0;
}