void davinci_gpio_init(void)
{
struct gpio_bank *gpio_bank;
#if defined(CONFIG_ARCH_DAVINCI644x) || defined(CONFIG_ARCH_DAVINCI_DM357)
if (cpu_is_davinci_dm644x() || cpu_is_davinci_dm357())
gpio_bank = &gpio_bank_dm6446;
#endif
#ifdef CONFIG_ARCH_DAVINCI_DM355
if (cpu_is_davinci_dm355())
gpio_bank = &gpio_bank_dm355;
#endif
#ifdef CONFIG_ARCH_DAVINCI_DM365
if (cpu_is_davinci_dm365())
gpio_bank = &gpio_bank_dm365;
#endif
#ifdef CONFIG_ARCH_DAVINCI_DM646x
if (cpu_is_davinci_dm6467())
gpio_bank = &gpio_bank_dm646x;
#endif
if (!gpio_bank)
BUG();
davinci_gpio_irq_setup(gpio_bank);
}
void __init davinci_mux_init(void)
{
const struct pin_config *table;
unsigned size;
if (cpu_is_davinci_dm365()) {
davinci_pins = dm365_pins;
davinci_num_pins = ARRAY_SIZE(dm365_pins);
table = davinci_dm365_pinmux;
size = ARRAY_SIZE(davinci_dm365_pinmux);
} else if (cpu_is_davinci_dm355()) {
davinci_pins = dm355_pins;
davinci_num_pins = ARRAY_SIZE(dm355_pins);
table = davinci_dm355_pinmux;
size = ARRAY_SIZE(davinci_dm355_pinmux);
} else if (cpu_is_davinci_dm6467()) {
davinci_pins = dm646x_pins;
davinci_num_pins = ARRAY_SIZE(dm646x_pins);
table = davinci_dm646x_pinmux;
size = ARRAY_SIZE(davinci_dm646x_pinmux);
} else if (cpu_is_davinci_dm644x()) {
davinci_pins = dm644x_pins;
davinci_num_pins = ARRAY_SIZE(dm644x_pins);
table = davinci_dm644x_pinmux;
size = ARRAY_SIZE(davinci_dm644x_pinmux);
} else {
if (!cpu_is_davinci_dm357())
BUG();
davinci_pins = dm357_pins;
davinci_num_pins = ARRAY_SIZE(dm357_pins);
table = davinci_dm357_pinmux;
size = ARRAY_SIZE(davinci_dm357_pinmux);
}
davinci_mux_register(table, size, davinci_get_pins, pinmux_in_use);
}
void __init davinci_map_common_io(void)
{
iotable_init(davinci_io_desc, ARRAY_SIZE(davinci_io_desc));
/* We want to check CPU revision early for cpu_is_davinci_xxxx() macros.
* IO space mapping must be initialized before we can do that.
*/
davinci_check_revision();
if (cpu_is_davinci_dm644x()) {
iotable_init(dm644x_io_desc, ARRAY_SIZE(dm644x_io_desc));
} else if (cpu_is_davinci_dm6467()) {
davinci_cpu_index = DM6467_CPU_IDX;
iotable_init(dm646x_io_desc, ARRAY_SIZE(dm646x_io_desc));
} else if (cpu_is_davinci_dm355()) {
davinci_cpu_index = DM355_CPU_IDX;
}
/* Normally devicemaps_init() would flush caches and tlb after
* mdesc->map_io(), but we must also do it here because of the CPU
* revision check below.
*/
flush_tlb_all();
flush_cache_all();
davinci_mux_init();
davinci_clk_init();
}
/* type = 0 for TVP5146 and 1 for Image sensor */
int tvp514x_set_input_mux(unsigned char channel)
{
int err = 0;
u8 val[2];
u32 val1;
val[0] = 8;
val[1] = 0x0;
if (cpu_is_davinci_dm644x())
return err;
/* Logi if (cpu_is_davinci_dm355())
err = davinci_i2c_write(2, val, MSP430_I2C_ADDR);
else */if (cpu_is_davinci_dm365()) {
/* drive the sensor reset line low */
image_sensor_hw_reset(0);
/* set tvp5146 reset line high */
tvp514x_hw_reset(1);
/* Set Mux for TVP5146 */
val1 = cpld_read(DM365_CPLD_REGISTER3);
val1 &= ~DM365_VIDEO_MUX_MASK;
val1 |= DM365_TVP5146_SEL;
cpld_write(val1, DM365_CPLD_REGISTER3);
}
return err;
}
int mt9xxx_set_input_mux(unsigned char channel)
{
int err = 0;
u8 val[2];
u32 val1;
val[0] = 8;
if (cpu_is_davinci_dm644x())
return err;
val[1] = 0x80;
if (cpu_is_davinci_dm355()) {
//Logi err = davinci_i2c_write(2, val, MSP430_I2C_ADDR);
if (err)
return err;
} else if (cpu_is_davinci_dm365()) {
/* Drive TVP5146 Reset to low */
tvp514x_hw_reset(0);
/* drive the sensor reset line high */
image_sensor_hw_reset(1);
/* Set Mux for image sensor */
val1 = cpld_read(DM365_CPLD_REGISTER3);
val1 &= ~DM365_VIDEO_MUX_MASK;
val1 |= DM365_SENSOR_SEL;
cpld_write(val1, DM365_CPLD_REGISTER3);
}
/* For image sensor we need to program I2C switch
* PCA9543A
*/
//Logi val[0] = 0x01;
//Logi davinci_i2c_write(1, val, PCA9543A_I2C_ADDR);
return 0;
}
void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
{
if (cpu_is_davinci_dm644x())
davinci_cfg_reg(DM644X_I2C);
davinci_i2c_device.dev.platform_data = pdata;
(void) platform_device_register(&davinci_i2c_device);
}
static int __init dm644x_init_devices(void)
{
if (!cpu_is_davinci_dm644x())
return 0;
platform_device_register(&dm644x_edma_device);
platform_device_register(&dm644x_mdio_device);
platform_device_register(&dm644x_emac_device);
return 0;
}
/* ARM Interrupt Controller Initialization */
void __init davinci_irq_init(void)
{
unsigned i;
if (cpu_is_davinci_dm644x())
davinci_def_priorities = dm644x_default_priorities;
else if (cpu_is_davinci_dm646x())
davinci_def_priorities = dm646x_default_priorities;
else if (cpu_is_davinci_dm355())
davinci_def_priorities = dm355_default_priorities;
/* Clear all interrupt requests */
davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
/* Disable all interrupts */
davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);
/* Interrupts disabled immediately, IRQ entry reflects all */
davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);
/* we don't use the hardware vector table, just its entry addresses */
davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET);
/* Clear all interrupt requests */
davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
unsigned j;
u32 pri;
for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
pri |= (*davinci_def_priorities & 0x07) << j;
davinci_irq_writel(pri, i);
}
/* set up genirq dispatch for ARM INTC */
for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) {
set_irq_chip(i, &davinci_irq_chip_0);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
if (i != IRQ_TINT1_TINT34)
set_irq_handler(i, handle_edge_irq);
else
set_irq_handler(i, handle_level_irq);
}
}
static int __init dm644x_init_devices(void)
{
if (!cpu_is_davinci_dm644x())
return 0;
platform_device_register(&dm644x_edma_device);
platform_device_register(&dm644x_mdio_device);
platform_device_register(&dm644x_emac_device);
clk_add_alias(NULL, dev_name(&dm644x_mdio_device.dev),
NULL, &dm644x_emac_device.dev);
return 0;
}
/* Connect the I2C pins to the I2C controller. */
static void enable_i2c_pins(void)
{
unsigned long flags;
local_irq_save(flags);
if (cpu_is_davinci_dm644x())
davinci_cfg_reg(DM644X_I2C);
else if (cpu_is_davinci_dm355()) {
davinci_cfg_reg(DM355_I2C_SDA);
davinci_cfg_reg(DM355_I2C_SCL);
}
local_irq_restore(flags);
}
void __init davinci_init_ide(void)
{
if (cpu_is_davinci_dm644x()) {
davinci_cfg_reg(DM644X_HPIEN_DISABLE);
davinci_cfg_reg(DM644X_ATAEN);
davinci_cfg_reg(DM644X_HDIREN);
} else if (cpu_is_davinci_dm646x()) {
/* IRQ_DM646X_IDE is the same as IRQ_IDE */
davinci_cfg_reg(DM646X_ATAEN);
} else {
WARN_ON(1);
return;
}
platform_device_register(&ide_device);
}
/* Generate a pulse on the I2C clock pin. */
static void pulse_i2c_clock(void)
{
if (cpu_is_davinci_dm644x()) {
/* I2C clock on GPIO43 */
gpio_set_value(43, 0);
udelay(20);
gpio_set_value(43, 1);
udelay(20);
} else if (cpu_is_davinci_dm355()) {
/* I2C clock on GPIO14 */
gpio_set_value(14, 0);
udelay(20);
gpio_set_value(14, 1);
udelay(20);
}
}
static int __init dm644x_init_devices(void)
{
if (!cpu_is_davinci_dm644x())
return 0;
/* Add ccdc clock aliases */
clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL);
clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL);
platform_device_register(&dm644x_edma_device);
platform_device_register(&dm644x_mdio_device);
platform_device_register(&dm644x_emac_device);
clk_add_alias(NULL, dev_name(&dm644x_mdio_device.dev),
NULL, &dm644x_emac_device.dev);
platform_device_register(&dm644x_vpss_device);
platform_device_register(&dm644x_ccdc_dev);
platform_device_register(&vpfe_capture_dev);
return 0;
}
/*
* Waiting on Bus Busy
*/
static int i2c_davinci_wait_for_bb(char allow_sleep, struct i2c_adapter *adap)
{
unsigned long timeout;
struct i2c_davinci_device *dev = i2c_get_adapdata(adap);
int i;
static char to_cnt = 0;
timeout = jiffies + DAVINCI_I2C_TIMEOUT;
while ((i2c_davinci_dev.regs->icstr) & DAVINCI_I2C_ICSTR_BB_MASK) {
if (to_cnt <= 2) {
if (time_after(jiffies, timeout)) {
i2c_warn("timeout waiting for bus ready");
to_cnt ++;
return -ETIMEDOUT;
}
} else if (cpu_is_davinci_dm644x() || cpu_is_davinci_dm355()) {
to_cnt = 0;
/* Send the NACK to the slave */
dev->regs->icmdr |= DAVINCI_I2C_ICMDR_NACKMOD_MASK;
/* Disable I2C */
disable_i2c_pins();
for (i = 0; i < 10; i++)
pulse_i2c_clock();
/* Re-enable I2C */
enable_i2c_pins();
i2c_davinci_reset(dev);
dev->cmd_complete = 0;
return -ETIMEDOUT;
}
if (allow_sleep)
schedule_timeout(1);
}
return 0;
}
static int __init dm644x_init_devices(void)
{
struct platform_device *edma_pdev;
int ret = 0;
if (!cpu_is_davinci_dm644x())
return 0;
edma_pdev = platform_device_register_full(&dm644x_edma_device);
if (IS_ERR(edma_pdev)) {
pr_warn("%s: Failed to register eDMA\n", __func__);
return PTR_ERR(edma_pdev);
}
platform_device_register(&dm644x_mdio_device);
platform_device_register(&dm644x_emac_device);
ret = davinci_init_wdt();
if (ret)
pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
return ret;
}
/*
* Configure the I2C data pin as a GPIO input and the I2C clock pin as a
* high GPIO output.
*/
static void disable_i2c_pins(void)
{
unsigned long flags;
local_irq_save(flags);
if (cpu_is_davinci_dm644x()) {
/* I2C clock on GPIO43, I2C data on GPIO44 */
gpio_direction_input(44);
gpio_direction_output(43, 0);
gpio_set_value(43, 1);
davinci_cfg_reg(DM644X_GPIO43_44);
} else if (cpu_is_davinci_dm355()) {
/* I2C clock on GPIO14, I2C data on GPIO15 */
gpio_direction_input(15);
gpio_direction_output(14, 0);
gpio_set_value(14, 1);
davinci_cfg_reg(DM355_GPIO14);
davinci_cfg_reg(DM355_GPIO15);
}
local_irq_restore(flags);
}
/*
* Low level master read/write transaction. This function is called
* from i2c_davinci_xfer.
*/
static int
i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
{
struct i2c_davinci_device *dev = i2c_get_adapdata(adap);
u8 zero_byte = 0;
u32 flag = 0, stat = 0;
int i;
DEB1("addr: 0x%04x, len: %d, flags: 0x%x, stop: %d",
msg->addr, msg->len, msg->flags, stop);
/* Introduce a 100musec delay. Required for Davinci EVM board only */
if (cpu_is_davinci_dm644x())
udelay(100);
/* set the slave address */
dev->regs->icsar = msg->addr;
/* Sigh, seems we can't do zero length transactions. Thus, we
* can't probe for devices w/o actually sending/receiving at least
* a single byte. So we'll set count to 1 for the zero length
* transaction case and hope we don't cause grief for some
* arbitrary device due to random byte write/read during
* probes.
*/
if (msg->len == 0) {
dev->buf = &zero_byte;
dev->buf_len = 1;
} else {
dev->buf = msg->buf;
dev->buf_len = msg->len;
}
dev->regs->iccnt = dev->buf_len;
dev->cmd_complete = 0;
dev->cmd_err = 0;
/* Clear any pending interrupts by reading the IVR */
stat = dev->regs->icivr;
/* Take I2C out of reset, configure it as master and set the start bit */
flag =
DAVINCI_I2C_ICMDR_IRS_MASK | DAVINCI_I2C_ICMDR_MST_MASK |
DAVINCI_I2C_ICMDR_STT_MASK;
/* if the slave address is ten bit address, enable XA bit */
if (msg->flags & I2C_M_TEN)
flag |= DAVINCI_I2C_ICMDR_XA_MASK;
if (!(msg->flags & I2C_M_RD))
flag |= DAVINCI_I2C_ICMDR_TRX_MASK;
if (stop)
flag |= DAVINCI_I2C_ICMDR_STP_MASK;
/* Enable receive and transmit interrupts */
if (msg->flags & I2C_M_RD)
dev->regs->icimr |= DAVINCI_I2C_ICIMR_ICRRDY_MASK;
else
dev->regs->icimr |= DAVINCI_I2C_ICIMR_ICXRDY_MASK;
/* write the data into mode register */
dev->regs->icmdr = flag;
/* wait for the transaction to complete */
wait_event_timeout (dev->cmd_wait, dev->cmd_complete, DAVINCI_I2C_TIMEOUT);
dev->buf_len = 0;
if (!dev->cmd_complete) {
i2c_warn("i2c: cmd complete failed: complete = 0x%x, \
icstr = 0x%x\n", dev->cmd_complete,
dev->regs->icstr);
if (cpu_is_davinci_dm644x() || cpu_is_davinci_dm355()) {
/* Send the NACK to the slave */
dev->regs->icmdr |= DAVINCI_I2C_ICMDR_NACKMOD_MASK;
/* Disable I2C */
disable_i2c_pins();
/* Send high and low on the SCL line */
for (i = 0; i < 10; i++)
pulse_i2c_clock();
/* Re-enable I2C */
enable_i2c_pins();
}
i2c_davinci_reset(dev);
dev->cmd_complete = 0;
return -ETIMEDOUT;
}
dev->cmd_complete = 0;
/* no error */
if (!dev->cmd_err)
return msg->len;
/* We have an error */
if (dev->cmd_err & DAVINCI_I2C_ICSTR_NACK_MASK) {
if (msg->flags & I2C_M_IGNORE_NAK)
return msg->len;
if (stop)
dev->regs->icmdr |= DAVINCI_I2C_ICMDR_STP_MASK;
return -EREMOTEIO;
}
if (dev->cmd_err & DAVINCI_I2C_ICSTR_AL_MASK) {
i2c_davinci_reset(dev);
return -EIO;
}
return msg->len;
}
void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
{
struct platform_device *pdev = NULL;
if (WARN_ON(cpu_is_davinci_dm646x()))
return;
/* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too;
* for example if MMCSD1 is used for SDIO, maybe DAT2 is unused.
*
* FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are
* not handled right here ...
*/
switch (module) {
case 1:
if (cpu_is_davinci_dm355()) {
/* REVISIT we may not need all these pins if e.g. this
* is a hard-wired SDIO device...
*/
davinci_cfg_reg(DM355_SD1_CMD);
davinci_cfg_reg(DM355_SD1_CLK);
davinci_cfg_reg(DM355_SD1_DATA0);
davinci_cfg_reg(DM355_SD1_DATA1);
davinci_cfg_reg(DM355_SD1_DATA2);
davinci_cfg_reg(DM355_SD1_DATA3);
} else if (cpu_is_davinci_dm365()) {
/* Configure pull down control */
unsigned v;
v = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
__raw_writel(v & ~0xfc0,
DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
SZ_4K - 1;
mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1;
davinci_mmcsd1_device.name = "da830-mmc";
} else
break;
pdev = &davinci_mmcsd1_device;
break;
case 0:
if (cpu_is_davinci_dm355()) {
mmcsd0_resources[0].start = DM355_MMCSD0_BASE;
mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0;
/* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */
davinci_cfg_reg(DM355_MMCSD0);
/* enable RX EDMA */
davinci_cfg_reg(DM355_EVT26_MMC0_RX);
} else if (cpu_is_davinci_dm365()) {
mmcsd0_resources[0].start = DM365_MMCSD0_BASE;
mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
davinci_mmcsd0_device.name = "da830-mmc";
} else if (cpu_is_davinci_dm644x()) {
/* REVISIT: should this be in board-init code? */
/* Power-on 3.3V IO cells */
__raw_writel(0,
DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
/*Set up the pull regiter for MMC */
davinci_cfg_reg(DM644X_MSTK);
}
pdev = &davinci_mmcsd0_device;
break;
}
if (WARN_ON(!pdev))
return;
pdev->dev.platform_data = config;
platform_device_register(pdev);
}
int __init dma_init(void)
{
struct dma_init_info info;
info.edma_num_dmach = EDMA_DAVINCI_NUM_DMACH;
info.edma_num_tcc = EDMA_DAVINCI_NUM_TCC;
info.cc_reg0_int = IRQ_CCINT0;
info.cc_error_int = IRQ_CCERRINT;
if (cpu_is_davinci_dm6467()) {
info.edma_num_evtq = EDMA_DM646X_NUM_EVQUE;
info.edma_num_tc = EDMA_DM646X_NUM_TC;
info.edma_num_param = EDMA_DM646X_NUM_PARAMENTRY;
info.edma_chmap_exist = EDMA_DM646X_CHMAP_EXIST;
info.edmatc_base_addrs = dm646x_edmatc_base_addrs;
info.edma2event_map = dm646x_dma_ch_hw_event_map;
info.edma_channels_arm = dm646x_edma_channels_arm;
info.qdma_channels_arm = dm646x_qdma_channels_arm;
info.param_entry_arm = dm646x_param_entry_arm;
info.tcc_arm = dm646x_tcc_arm;
info.param_entry_reserved = dm646x_param_entry_reserved;
info.q_pri = dm646x_queue_priority_mapping;
info.q_tc = dm646x_queue_tc_mapping;
info.q_wm = dm646x_queue_watermark_level;
info.tc_error_int = dm646x_tc_error_int;
} else if (cpu_is_davinci_dm355()) {
info.edma_num_evtq = EDMA_DM355_NUM_EVQUE;
info.edma_num_tc = EDMA_DM355_NUM_TC;
info.edma_num_param = EDMA_DM355_NUM_PARAMENTRY;
info.edma_chmap_exist = EDMA_DM355_CHMAP_EXIST;
info.edmatc_base_addrs = dm355_edmatc_base_addrs;
info.edma2event_map = dm355_dma_ch_hw_event_map;
info.edma_channels_arm = dm355_edma_channels_arm;
info.qdma_channels_arm = dm355_qdma_channels_arm;
info.param_entry_arm = dm355_param_entry_arm;
info.tcc_arm = dm355_tcc_arm;
info.param_entry_reserved = dm355_param_entry_reserved;
info.q_pri = dm355_queue_priority_mapping;
info.q_tc = dm355_queue_tc_mapping;
info.q_wm = dm355_queue_watermark_level;
info.tc_error_int = dm355_tc_error_int;
} else if (cpu_is_davinci_dm365()) {
info.edma_num_evtq = EDMA_DM365_NUM_EVQUE;
info.edma_num_tc = EDMA_DM365_NUM_TC;
info.edma_num_param = EDMA_DM365_NUM_PARAMENTRY;
info.edma_chmap_exist = EDMA_DM365_CHMAP_EXIST;
info.edmatc_base_addrs = dm365_edmatc_base_addrs;
info.edma2event_map = dm365_dma_ch_hw_event_map;
info.edma_channels_arm = dm365_edma_channels_arm;
info.qdma_channels_arm = dm365_qdma_channels_arm;
info.param_entry_arm = dm365_param_entry_arm;
info.tcc_arm = dm365_tcc_arm;
info.param_entry_reserved = dm365_param_entry_reserved;
info.q_pri = dm365_queue_priority_mapping;
info.q_tc = dm365_queue_tc_mapping;
info.q_wm = dm365_queue_watermark_level;
info.tc_error_int = dm365_tc_error_int;
} else { /* Must be dm6446 or dm357 */
if (!cpu_is_davinci_dm644x() && !cpu_is_davinci_dm357())
BUG();
info.edma_num_evtq = EDMA_DM644X_NUM_EVQUE;
info.edma_num_tc = EDMA_DM644X_NUM_TC;
info.edma_num_param = EDMA_DM644X_NUM_PARAMENTRY;
info.edma_chmap_exist = EDMA_DM644X_CHMAP_EXIST;
info.edmatc_base_addrs = dm644x_edmatc_base_addrs;
info.edma2event_map = dm644x_dma_ch_hw_event_map;
info.edma_channels_arm = dm644x_edma_channels_arm;
info.qdma_channels_arm = dm644x_qdma_channels_arm;
info.param_entry_arm = dm644x_param_entry_arm;
info.tcc_arm = dm644x_tcc_arm;
info.param_entry_reserved = dm644x_param_entry_reserved;
info.q_pri = dm644x_queue_priority_mapping;
info.q_tc = dm644x_queue_tc_mapping;
info.q_wm = dm644x_queue_watermark_level;
info.tc_error_int = dm644x_tc_error_int;
}
return davinci_dma_init(&info);
}
void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
{
struct platform_device *pdev = NULL;
if (WARN_ON(cpu_is_davinci_dm646x()))
return;
switch (module) {
case 1:
if (cpu_is_davinci_dm355()) {
davinci_cfg_reg(DM355_SD1_CMD);
davinci_cfg_reg(DM355_SD1_CLK);
davinci_cfg_reg(DM355_SD1_DATA0);
davinci_cfg_reg(DM355_SD1_DATA1);
davinci_cfg_reg(DM355_SD1_DATA2);
davinci_cfg_reg(DM355_SD1_DATA3);
} else if (cpu_is_davinci_dm365()) {
void __iomem *pupdctl1 =
IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c);
__raw_writel((__raw_readl(pupdctl1) & ~0x400),
pupdctl1);
mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM365_SDIOINT1;
} else
break;
pdev = &davinci_mmcsd1_device;
break;
case 0:
if (cpu_is_davinci_dm355()) {
mmcsd0_resources[0].start = DM355_MMCSD0_BASE;
mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0;
davinci_cfg_reg(DM355_MMCSD0);
davinci_cfg_reg(DM355_EVT26_MMC0_RX);
} else if (cpu_is_davinci_dm365()) {
mmcsd0_resources[0].start = DM365_MMCSD0_BASE;
mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
} else if (cpu_is_davinci_dm644x()) {
void __iomem *base =
IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
__raw_writel(0, base + DM64XX_VDD3P3V_PWDN);
davinci_cfg_reg(DM644X_MSTK);
}
pdev = &davinci_mmcsd0_device;
break;
}
if (WARN_ON(!pdev))
return;
pdev->dev.platform_data = config;
platform_device_register(pdev);
}
