void __init mxc_arch_reset_init_dt(void)
{
struct device_node *np = NULL;
if (cpu_is_imx6q() || cpu_is_imx6dl())
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
else if (cpu_is_imx6sl())
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpc");
if (np)
of_property_read_u32(np, "fsl,wdog-reset", &wdog_source);
pr_info("Use WDOG%d as reset source\n", wdog_source);
np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
wdog_base = of_iomap(np, 0);
WARN_ON(!wdog_base);
/* Some i.MX6 boards use WDOG2 to reset board in ldo-bypass mode */
if (wdog_source == 2 && (cpu_is_imx6q() || cpu_is_imx6dl() ||
cpu_is_imx6sl())) {
np = of_find_compatible_node(np, NULL, "fsl,imx21-wdt");
wdog_base = of_iomap(np, 0);
WARN_ON(!wdog_base);
}
wdog_clk = of_clk_get(np, 0);
if (IS_ERR(wdog_clk)) {
pr_warn("%s: failed to get wdog clock\n", __func__);
wdog_clk = NULL;
return;
}
clk_prepare(wdog_clk);
}
static void reduce_bus_freq(void)
{
if (cpu_is_imx6())
clk_prepare_enable(pll3);
if (audio_bus_count && (low_bus_freq_mode || ultra_low_bus_freq_mode))
busfreq_notify(LOW_BUSFREQ_EXIT);
else if (!audio_bus_count)
busfreq_notify(LOW_BUSFREQ_ENTER);
if (cpu_is_imx7d())
enter_lpm_imx7d();
else if (cpu_is_imx6sl())
enter_lpm_imx6sl();
else if (cpu_is_imx6sx() || cpu_is_imx6ul())
enter_lpm_imx6_up();
else {
if (cpu_is_imx6dl())
/* Set axi to periph_clk */
imx_clk_set_parent(axi_sel_clk, periph_clk);
if (audio_bus_count) {
/* Need to ensure that PLL2_PFD_400M is kept ON. */
clk_prepare_enable(pll2_400);
update_ddr_freq_imx_smp(LOW_AUDIO_CLK);
/* Make sure periph clk's parent also got updated */
imx_clk_set_parent(periph_clk2_sel, pll3);
imx_clk_set_parent(periph_pre_clk, pll2_200);
imx_clk_set_parent(periph_clk, periph_pre_clk);
audio_bus_freq_mode = 1;
low_bus_freq_mode = 0;
cur_bus_freq_mode = BUS_FREQ_AUDIO;
} else {
update_ddr_freq_imx_smp(LPAPM_CLK);
/* Make sure periph clk's parent also got updated */
imx_clk_set_parent(periph_clk2_sel, osc_clk);
/* Set periph_clk parent to OSC via periph_clk2_sel */
imx_clk_set_parent(periph_clk, periph_clk2);
if (audio_bus_freq_mode)
clk_disable_unprepare(pll2_400);
low_bus_freq_mode = 1;
audio_bus_freq_mode = 0;
cur_bus_freq_mode = BUS_FREQ_LOW;
}
}
if (cpu_is_imx6())
clk_disable_unprepare(pll3);
med_bus_freq_mode = 0;
high_bus_freq_mode = 0;
if (audio_bus_freq_mode)
dev_dbg(busfreq_dev, "Bus freq set to audio mode. Count:\
high %d, med %d, audio %d\n",
high_bus_count, med_bus_count, audio_bus_count);
if (low_bus_freq_mode)
dev_dbg(busfreq_dev, "Bus freq set to low mode. Count:\
high %d, med %d, audio %d\n",
high_bus_count, med_bus_count, audio_bus_count);
}
int init_mmdc_lpddr2_settings(struct platform_device *busfreq_pdev)
{
unsigned long ddr_code_size;
busfreq_dev = &busfreq_pdev->dev;
ddr_code_size = (&imx6_lpddr2_freq_change_end -&imx6_lpddr2_freq_change_start) *4;
if (cpu_is_imx6sl())
mx6_change_lpddr2_freq = (void *)fncpy(
(void *)ddr_freq_change_iram_base,
&mx6_lpddr2_freq_change, ddr_code_size);
else if (cpu_is_imx6sx() || cpu_is_imx6ul())
mx6_change_lpddr2_freq = (void *)fncpy(
(void *)ddr_freq_change_iram_base,
&imx6_up_lpddr2_freq_change, ddr_code_size);
curr_ddr_rate = ddr_normal_rate;
return 0;
}
/*
* Reset the system. It is called by machine_restart().
*/
void mxc_restart(char mode, const char *cmd)
{
unsigned int wcr_enable;
arch_reset_special_mode(mode, cmd);
if (wdog_clk)
clk_enable(wdog_clk);
if (cpu_is_mx1())
wcr_enable = (1 << 0);
/*
* Some i.MX6 boards use WDOG2 to reset external pmic in bypass mode,
* so do WDOG2 reset here. Do not set SRS, since we will
* trigger external POR later. Use WDOG1 to reset in ldo-enable
* mode. You can set it by "fsl,wdog-reset" in dts.
* For i.MX6SX we have to trigger wdog-reset to reset QSPI-NOR flash to
* workaround qspi-nor reboot issue whatever ldo-bypass or not.
*/
else if ((wdog_source == 2 && (cpu_is_imx6q() || cpu_is_imx6dl() ||
cpu_is_imx6sl())) || cpu_is_imx6sx())
wcr_enable = 0x14;
else
wcr_enable = (1 << 2);
/* Assert SRS signal */
__raw_writew(wcr_enable, wdog_base);
/* write twice to ensure the request will not get ignored */
__raw_writew(wcr_enable, wdog_base);
/* wait for reset to assert... */
mdelay(500);
pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
/* delay to allow the serial port to show the message */
mdelay(50);
/* we'll take a jump through zero as a poor second */
soft_restart(0);
}
/*
* Set the DDR to either 528MHz or 400MHz for iMX6qd
* or 400MHz for iMX6dl.
*/
static int set_high_bus_freq(int high_bus_freq)
{
struct clk *periph_clk_parent;
if (bus_freq_scaling_initialized && bus_freq_scaling_is_active)
cancel_delayed_work_sync(&low_bus_freq_handler);
if (busfreq_suspended)
return 0;
if (cpu_is_imx6q())
periph_clk_parent = pll2_bus;
else
periph_clk_parent = pll2_400;
if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active)
return 0;
if (high_bus_freq_mode)
return 0;
/* medium bus freq is only supported for MX6DQ */
if (med_bus_freq_mode && !high_bus_freq)
return 0;
if (low_bus_freq_mode || ultra_low_bus_freq_mode)
busfreq_notify(LOW_BUSFREQ_EXIT);
if (cpu_is_imx6())
clk_prepare_enable(pll3);
if (cpu_is_imx7d())
exit_lpm_imx7d();
else if (cpu_is_imx6sl())
exit_lpm_imx6sl();
else if (cpu_is_imx6sx() || cpu_is_imx6ul())
exit_lpm_imx6_up();
else {
if (high_bus_freq) {
clk_prepare_enable(pll2_400);
update_ddr_freq_imx_smp(ddr_normal_rate);
/* Make sure periph clk's parent also got updated */
imx_clk_set_parent(periph_clk2_sel, pll3);
imx_clk_set_parent(periph_pre_clk, periph_clk_parent);
imx_clk_set_parent(periph_clk, periph_pre_clk);
if (cpu_is_imx6dl()) {
/* Set axi to pll3_pfd1_540m */
imx_clk_set_parent(axi_alt_sel_clk, pll3_pfd1_540m);
imx_clk_set_parent(axi_sel_clk, axi_alt_sel_clk);
}
clk_disable_unprepare(pll2_400);
} else {
update_ddr_freq_imx_smp(ddr_med_rate);
/* Make sure periph clk's parent also got updated */
imx_clk_set_parent(periph_clk2_sel, pll3);
imx_clk_set_parent(periph_pre_clk, pll2_400);
imx_clk_set_parent(periph_clk, periph_pre_clk);
}
if (audio_bus_freq_mode)
clk_disable_unprepare(pll2_400);
}
high_bus_freq_mode = 1;
med_bus_freq_mode = 0;
low_bus_freq_mode = 0;
audio_bus_freq_mode = 0;
cur_bus_freq_mode = BUS_FREQ_HIGH;
if (cpu_is_imx6())
clk_disable_unprepare(pll3);
if (high_bus_freq_mode)
dev_dbg(busfreq_dev, "Bus freq set to high mode. Count:\
high %d, med %d, audio %d\n",
high_bus_count, med_bus_count, audio_bus_count);
if (med_bus_freq_mode)
dev_dbg(busfreq_dev, "Bus freq set to med mode. Count:\
high %d, med %d, audio %d\n",
high_bus_count, med_bus_count, audio_bus_count);
return 0;
}
