void __init ixp4xx_sys_init(void) { ixp4xx_exp_bus_size = SZ_16M; platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices)); gpiochip_add(&ixp4xx_gpio_chip); if (cpu_is_ixp46x()) { int region; platform_add_devices(ixp46x_devices, ARRAY_SIZE(ixp46x_devices)); for (region = 0; region < 7; region++) { if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) { ixp4xx_exp_bus_size = SZ_32M; break; } } } printk("IXP4xx: Using %luMiB expansion bus window size\n", ixp4xx_exp_bus_size >> 20); }
void __init ixp4xx_init_irq(void) { int i = 0; /* Route all sources to IRQ instead of FIQ */ *IXP4XX_ICLR = 0x0; /* Disable all interrupt */ *IXP4XX_ICMR = 0x0; if (cpu_is_ixp46x() || cpu_is_ixp43x()) { /* Route upper 32 sources to IRQ instead of FIQ */ *IXP4XX_ICLR2 = 0x00; /* Disable upper 32 interrupts */ *IXP4XX_ICMR2 = 0x00; } /* Default to all level triggered */ for(i = 0; i < NR_IRQS; i++) { set_irq_chip(i, &ixp4xx_irq_chip); set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } }
static void ixp4xx_irq_mask(unsigned int irq) { if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32) *IXP4XX_ICMR2 &= ~(1 << (irq - 32)); else *IXP4XX_ICMR &= ~(1 << irq); }
static void ixp4xx_irq_mask(struct irq_data *d) { if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32) *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32)); else *IXP4XX_ICMR &= ~(1 << d->irq); }
void __init ixp4xx_init_irq(void) { int i = 0; /* * ixp4xx does not implement the XScale PWRMODE register * so it must not call cpu_do_idle(). */ disable_hlt(); /* Route all sources to IRQ instead of FIQ */ *IXP4XX_ICLR = 0x0; /* Disable all interrupt */ *IXP4XX_ICMR = 0x0; if (cpu_is_ixp46x() || cpu_is_ixp43x()) { /* Route upper 32 sources to IRQ instead of FIQ */ *IXP4XX_ICLR2 = 0x00; /* Disable upper 32 interrupts */ *IXP4XX_ICMR2 = 0x00; } /* Default to all level triggered */ for(i = 0; i < NR_IRQS; i++) { irq_set_chip_and_handler(i, &ixp4xx_irq_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID); } }
void __init ixp4xx_init_irq(void) { int i = 0; *IXP4XX_ICLR = 0x0; *IXP4XX_ICMR = 0x0; if (cpu_is_ixp46x() || cpu_is_ixp43x()) { *IXP4XX_ICLR2 = 0x00; *IXP4XX_ICMR2 = 0x00; } for(i = 0; i < NR_IRQS; i++) { set_irq_chip(i, &ixp4xx_irq_chip); set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } }
void __init ixp4xx_init_irq(void) { int i = 0; /* */ disable_hlt(); /* */ *IXP4XX_ICLR = 0x0; /* */ *IXP4XX_ICMR = 0x0; if (cpu_is_ixp46x() || cpu_is_ixp43x()) { /* */ *IXP4XX_ICLR2 = 0x00; /* */ *IXP4XX_ICMR2 = 0x00; } /* */ for(i = 0; i < NR_IRQS; i++) { irq_set_chip_and_handler(i, &ixp4xx_irq_chip, handle_level_irq); set_irq_flags(i, IRQF_VALID); } }
/* * Return a mask of the "fuse" bits that identify * which h/w features are present. * NB: assumes the expansion bus is mapped. */ uint32_t ixp4xx_read_feature_bits(void) { uint32_t bits = ~IXPREG(IXP425_EXP_VBASE + EXP_FCTRL_OFFSET); bits &= ~EXP_FCTRL_RESVD; if (!cpu_is_ixp46x()) bits &= ~EXP_FCTRL_IXP46X_ONLY; return bits; }
/* * Level triggered interrupts on GPIO lines can only be cleared when the * interrupt condition disappears. */ static void ixp4xx_irq_unmask(unsigned int irq) { if (!(ixp4xx_irq_edge & (1 << irq))) ixp4xx_irq_ack(irq); if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32) *IXP4XX_ICMR2 |= (1 << (irq - 32)); else *IXP4XX_ICMR |= (1 << irq); }
/* * Level triggered interrupts on GPIO lines can only be cleared when the * interrupt condition disappears. */ static void ixp4xx_irq_unmask(struct irq_data *d) { if (!(ixp4xx_irq_edge & (1 << d->irq))) ixp4xx_irq_ack(d); if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32) *IXP4XX_ICMR2 |= (1 << (d->irq - 32)); else *IXP4XX_ICMR |= (1 << d->irq); }
static int __init ixp4xx_wdt_init(void) { int ret; if (!(read_cpuid_id() & 0xf) && !cpu_is_ixp46x()) { printk(KERN_ERR "IXP4XXX Watchdog: Rev. A0 IXP42x CPU detected" " - watchdog disabled\n"); return -ENODEV; } spin_lock_init(&wdt_lock); boot_status = (*IXP4XX_OSST & IXP4XX_OSST_TIMER_WARM_RESET) ? WDIOF_CARDRESET : 0; ret = misc_register(&ixp4xx_wdt_miscdev); if (ret == 0) printk(KERN_INFO "IXP4xx Watchdog Timer: heartbeat %d sec\n", heartbeat); return ret; }
static int __init ptp_ixp_init(void) { if (!cpu_is_ixp46x()) return -ENODEV; ixp_clock.regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT; ixp_clock.caps = ptp_ixp_caps; ixp_clock.ptp_clock = ptp_clock_register(&ixp_clock.caps, NULL); if (IS_ERR(ixp_clock.ptp_clock)) return PTR_ERR(ixp_clock.ptp_clock); ixp46x_phc_index = ptp_clock_index(ixp_clock.ptp_clock); __raw_writel(DEFAULT_ADDEND, &ixp_clock.regs->addend); __raw_writel(1, &ixp_clock.regs->trgt_lo); __raw_writel(0, &ixp_clock.regs->trgt_hi); __raw_writel(TTIPEND, &ixp_clock.regs->event); if (MASTER_IRQ != setup_interrupt(MASTER_GPIO)) { pr_err("failed to setup gpio %d as irq\n", MASTER_GPIO); goto no_master; } if (SLAVE_IRQ != setup_interrupt(SLAVE_GPIO)) { pr_err("failed to setup gpio %d as irq\n", SLAVE_GPIO); goto no_slave; } return 0; no_slave: free_irq(MASTER_IRQ, &ixp_clock); no_master: ptp_clock_unregister(ixp_clock.ptp_clock); return -ENODEV; }