/* ------------------------------------------------------------------------*//** * @FUNCTION ctt44xx_dump * @BRIEF dump PRCM registers * @RETURNS 0 * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * @DESCRIPTION dump PRCM registers *//*------------------------------------------------------------------------ */ int ctt44xx_dump(void) { unsigned int i = 0; unsigned int ret, val = 0; int err = 0; CHECK_CPU(44xx, OMAPCONF_ERR_ARG); printf("The Clock Tree Tool can import register settings from a *.rd1 " "file.\n"); printf("The format of the *.rd1 file is:\n\n"); printf("DeviceName OMAPxxxx_ESx.x\n"); printf("<register address> <register value>\n"); printf("<register address> <register value>\n"); printf("...\n\n"); printf("Copy the below output between the begin and end separators " "into a\n"); printf("file with the extension *.rd1 and this file can be read by the" "\n"); printf("Clock Tree Tool\n\n"); printf("|--------------------------- ctt dump begin ------------------" "----|\n"); if (cpu_is_omap4430()) printf("DeviceName OMAP4430_ES2.x\n"); else if (cpu_is_omap4460()) printf("DeviceName OMAP4460_ES1.x\n"); else if (cpu_is_omap4470()) printf("DeviceName OMAP4470_ES1.0\n"); else return OMAPCONF_ERR_CPU; ctt44xx_regtable_init(); while (prcm_ctt_reg_table[i].addr != 0) { /* display register addr & content (hex) */ ret = mem_read(prcm_ctt_reg_table[i].addr, &val); if (ret == 0) printf("0x%08X 0x%08X\n", prcm_ctt_reg_table[i].addr, val); else { fprintf(stderr, "omapconf: read error! (addr=0x%08X, err=%d)\n", prcm_ctt_reg_table[i].addr, ret); err = OMAPCONF_ERR_REG_ACCESS; } i++; } printf("|---------------------------- ctt dump end --------------------" "---|\n"); return err; }
/* ------------------------------------------------------------------------*//** * @FUNCTION ctt44xx_rd1_export * @BRIEF export PRCM registers in CTT RD1 format * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * OMAPCONF_ERR_NOT_AVAILABLE * @param[in] filename: output file name * @DESCRIPTION export PRCM registers in CTT RD1 format *//*------------------------------------------------------------------------ */ int ctt44xx_rd1_export(char *filename) { unsigned int i = 0; unsigned int ret, val = 0; int err = 0; FILE *fd = NULL; CHECK_CPU(44xx, OMAPCONF_ERR_ARG); CHECK_NULL_ARG(filename, OMAPCONF_ERR_ARG); fd = fopen(filename, "w"); if (fd == NULL) { printf("error: could not create %s file!\n", filename); return OMAPCONF_ERR_NOT_AVAILABLE; } if (cpu_is_omap4430()) { fprintf(fd, "DeviceName OMAP4430_ES2.x\n"); } else if (cpu_is_omap4460()) { fprintf(fd, "DeviceName OMAP4460_ES1.x\n"); } else if (cpu_is_omap4470()) { fprintf(fd, "DeviceName OMAP4470_ES1.0\n"); } else { err = OMAPCONF_ERR_CPU; goto ctt44xx_rd1_export_end; } ctt44xx_regtable_init(); while (prcm_ctt_reg_table[i].addr != 0) { /* display register addr & content (hex) */ ret = mem_read(prcm_ctt_reg_table[i].addr, &val); if (ret == 0) fprintf(fd, "0x%08X 0x%08X\n", prcm_ctt_reg_table[i].addr, val); else { fprintf(stderr, "omapconf: read error! (addr=0x%08X, err=%d)\n", prcm_ctt_reg_table[i].addr, ret); err = OMAPCONF_ERR_REG_ACCESS; } i++; } printf("Output written to file '%s'.\n", filename); err = 0; ctt44xx_rd1_export_end: if (fd != NULL) fclose(fd); return err; }
/* * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly * @clk: struct clk * of DPLL to set * @m: DPLL multiplier to set * @n: DPLL divider to set * @freqsel: FREQSEL value to set * * Program the DPLL with the supplied M, N values, and wait for the DPLL to * lock.. Returns -EINVAL upon error, or 0 upon success. */ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel, unsigned long orig_rate) { struct dpll_data *dd = clk->dpll_data; u8 dco, sd_div; u32 v; /* * On OMAP4460, to obtain MPU DPLL frequency higher * than 1GHz, DCC (Duty Cycle Correction) needs to * be enabled. * Also the interconnect frequency to EMIF should * be switched between MPU clk divide by 4 (for * frequencies higher than 920Mhz) and MPU clk divide * by 2 (for frequencies lower than or equal to 920Mhz) * Lastly the async bridge to ABE must be MPU clk divide * by 8 for MPU clk > 748Mhz and MPU clk divide by 4 * for lower frequencies. * TODO: For now use a strcmp, but need to find a * better way to identify the MPU dpll. */ if (cpu_is_omap4460() && !strcmp(clk->name, "dpll_mpu_ck")) { /* DCC control */ v = __raw_readl(dd->mult_div1_reg); if ((orig_rate <= 1000000000) && (v & OMAP4460_DCC_EN_MASK)) { v &= ~OMAP4460_DCC_EN_MASK; /* Disable DCC */ __raw_writel(v, dd->mult_div1_reg); } } /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ _omap3_noncore_dpll_bypass(clk); /* * Set jitter correction. No jitter correction for OMAP4 and 3630 * since freqsel field is no longer present */ if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { v = __raw_readl(dd->control_reg); v &= ~dd->freqsel_mask; v |= freqsel << __ffs(dd->freqsel_mask); __raw_writel(v, dd->control_reg); } /* Set DPLL multiplier, divider */ v = __raw_readl(dd->mult_div1_reg); v &= ~(dd->mult_mask | dd->div1_mask); v |= m << __ffs(dd->mult_mask); v |= (n - 1) << __ffs(dd->div1_mask); /* Configure dco and sd_div for dplls that have these fields */ if (dd->dco_mask) { _lookup_dco(clk, &dco, m, n); v &= ~(dd->dco_mask); v |= dco << __ffs(dd->dco_mask); } if (dd->sddiv_mask) { _lookup_sddiv(clk, &sd_div, m, n); v &= ~(dd->sddiv_mask); v |= sd_div << __ffs(dd->sddiv_mask); } __raw_writel(v, dd->mult_div1_reg); /* We let the clock framework set the other output dividers later */ /* REVISIT: Set ramp-up delay? */ _omap3_noncore_dpll_lock(clk); if (cpu_is_omap4460() && !strcmp(clk->name, "dpll_mpu_ck")) { /* DCC control */ if (orig_rate > 1000000000) { v &= ~OMAP4460_DCC_COUNT_MAX_MASK; v |= (5 << OMAP4460_DCC_COUNT_MAX_SHIFT); __raw_writel(v, dd->mult_div1_reg); v |= OMAP4460_DCC_EN_MASK; /* Enable DCC */ __raw_writel(v, dd->mult_div1_reg); } /* EMIF/ABE clock rate control */ v = __raw_readl(OMAP4430_CM_MPU_MPU_CLKCTRL); if (orig_rate > 920000000) v |= OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK; else v &= ~OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK; if (orig_rate > 748000000) v |= OMAP4460_CLKSEL_ABE_DIV_MODE_MASK; else v &= ~OMAP4460_CLKSEL_ABE_DIV_MODE_MASK; __raw_writel(v, OMAP4430_CM_MPU_MPU_CLKCTRL); } return 0; }
/** * omap3_noncore_dpll_set_rate - set non-core DPLL rate * @clk: struct clk * of DPLL to set * @rate: rounded target rate * * Set the DPLL CLKOUT to the target rate. If the DPLL can enter * low-power bypass, and the target rate is the bypass source clock * rate, then configure the DPLL for bypass. Otherwise, round the * target rate if it hasn't been done already, then program and lock * the DPLL. Returns -EINVAL upon error, or 0 upon success. */ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) { struct clk *new_parent = NULL; u16 freqsel = 0; struct dpll_data *dd; int ret; unsigned long orig_rate = 0; if (!clk || !rate) return -EINVAL; dd = clk->dpll_data; if (!dd) return -EINVAL; if (rate == omap2_get_dpll_rate(clk)) return 0; /* * Ensure both the bypass and ref clocks are enabled prior to * doing anything; we need the bypass clock running to reprogram * the DPLL. */ omap2_clk_enable(dd->clk_bypass); omap2_clk_enable(dd->clk_ref); if (dd->clk_bypass->rate == rate && (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); ret = _omap3_noncore_dpll_bypass(clk); if (!ret) new_parent = dd->clk_bypass; } else { /* * On 4460, the MPU clk for frequencies higher than 1Ghz * is sourced from CLKOUTX2_M3, instead of CLKOUT_M2, while * value of M3 is fixed to 1. Hence for frequencies higher * than 1 Ghz, lock the DPLL at half the rate so the * CLKOUTX2_M3 then matches the requested rate. */ if (cpu_is_omap4460() && !strcmp(clk->name, "dpll_mpu_ck") && (rate > 1000000000)) { orig_rate = rate; rate = rate/2; } if (dd->last_rounded_rate != rate) rate = clk->round_rate(clk, rate); if (dd->last_rounded_rate == 0) return -EINVAL; /* No freqsel on OMAP4 and OMAP3630 */ if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); if (!freqsel) WARN_ON(1); } /* Set the rate back to original for book keeping*/ if (orig_rate) rate = orig_rate; pr_debug("clock: %s: set rate: locking rate to %lu.\n", clk->name, rate); ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, dd->last_rounded_n, freqsel, orig_rate); if (!ret) new_parent = dd->clk_ref; } if (!ret) { /* * Switch the parent clock in the heirarchy, and make sure * that the new parent's usecount is correct. Note: we * enable the new parent before disabling the old to avoid * any unnecessary hardware disable->enable transitions. */ if (clk->usecount) { omap2_clk_enable(new_parent); omap2_clk_disable(clk->parent); } clk_reparent(clk, new_parent); clk->rate = rate; } omap2_clk_disable(dd->clk_ref); omap2_clk_disable(dd->clk_bypass); return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION sr44xx_voltage_set * @BRIEF set voltage of a voltage domain using VC bypass method * @RETURNS 0 in case of success * OMAPCONF_ERR_ARG * OMAPCONF_ERR_REG_ACCESS * OMAPCONF_ERR_NOT_AVAILABLE * OMAPCONF_ERR_UNEXPECTED * @param[in] vdd_id: voltage domain ID * @param[in] uv: supply voltage (in uV) * @DESCRIPTION set voltage of a voltage domain using VC bypass method * NB: automatically disable SmartReflex (if enabled). * NB: do not re-enable smartreflex afterwards or * new voltage will be overriden. *//*------------------------------------------------------------------------ */ int sr44xx_voltage_set(unsigned int vdd_id, unsigned long uv) { omap4_sr_module_id sr_id; FILE *fp; int ret; unsigned char vsel, vsel_len; unsigned int vc_bypass_value; unsigned int volt_reg_addr; char voltdm_name[VOLTDM44XX_MAX_NAME_LENGTH]; unsigned char VR_slave_address; unsigned int prm_vc_val_cmd_vdd, prm_vc_val_cmd_vdd_addr; static const char filename[OMAP4_SR_ID_MAX][72] = { "/sys/kernel/debug/pm_debug/smartreflex/sr_mpu/autocomp", "/sys/kernel/debug/pm_debug/smartreflex/sr_iva/autocomp", "/sys/kernel/debug/pm_debug/smartreflex/sr_core/autocomp"}; if (!cpu_is_omap44xx()) return OMAPCONF_ERR_CPU; if ((uv < OMAP4_VOLTAGE_MIN) || (uv > OMAP4_VOLTAGE_MAX)) { fprintf(stderr, "Error: voltage out of range! (%1.3lfV)\n", (double) ((double) uv / 1000000.0)); return OMAPCONF_ERR_ARG; } if (cpu_is_omap4470()) { switch (vdd_id) { case OMAP4_VDD_MPU: sr_id = OMAP4_SR_MPU; VR_slave_address = PMIC_SLAVE_ADDR; volt_reg_addr = VOLT_REG_MPU_ADDR; prm_vc_val_cmd_vdd_addr = OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L; break; case OMAP4_VDD_IVA: sr_id = OMAP4_SR_IVA; VR_slave_address = PMIC_SLAVE_ADDR; volt_reg_addr = OMAP4470_VOLT_REG_IVA_ADDR; prm_vc_val_cmd_vdd_addr = OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L; break; case OMAP4_VDD_CORE: sr_id = OMAP4_SR_CORE; VR_slave_address = PMIC_SLAVE_ADDR; volt_reg_addr = OMAP4470_VOLT_REG_CORE_ADDR; prm_vc_val_cmd_vdd_addr = OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L; break; default: fprintf(stderr, "Error: invalid voltage domain ID! " "(%d)\n", vdd_id); return OMAPCONF_ERR_ARG; } } else if (cpu_is_omap4460()) { switch (vdd_id) { case OMAP4_VDD_MPU: sr_id = OMAP4_SR_MPU; VR_slave_address = TPS62361_SLAVE_ADDR; volt_reg_addr = TPS62361_VOLT_REG_ADDR; prm_vc_val_cmd_vdd_addr = OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L; break; case OMAP4_VDD_IVA: sr_id = OMAP4_SR_IVA; VR_slave_address = PMIC_SLAVE_ADDR; volt_reg_addr = VOLT_REG_IVA_ADDR; prm_vc_val_cmd_vdd_addr = OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L; break; case OMAP4_VDD_CORE: sr_id = OMAP4_SR_CORE; VR_slave_address = PMIC_SLAVE_ADDR; volt_reg_addr = OMAP4460_VOLT_REG_CORE_ADDR; prm_vc_val_cmd_vdd_addr = OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L; break; default: fprintf(stderr, "Error: invalid voltage domain ID! " "(%d)\n", vdd_id); return OMAPCONF_ERR_ARG; } } else { /* 4430 */ switch (vdd_id) { case OMAP4_VDD_MPU: sr_id = OMAP4_SR_MPU; VR_slave_address = PMIC_SLAVE_ADDR; volt_reg_addr = VOLT_REG_MPU_ADDR; prm_vc_val_cmd_vdd_addr = OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L; break; case OMAP4_VDD_IVA: sr_id = OMAP4_SR_IVA; VR_slave_address = PMIC_SLAVE_ADDR; volt_reg_addr = VOLT_REG_IVA_ADDR; prm_vc_val_cmd_vdd_addr = OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L; break; case OMAP4_VDD_CORE: sr_id = OMAP4_SR_CORE; VR_slave_address = PMIC_SLAVE_ADDR; volt_reg_addr = VOLT_REG_CORE_ADDR; prm_vc_val_cmd_vdd_addr = OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L; break; default: fprintf(stderr, "Error: invalid voltage domain ID! " "(%d)\n", vdd_id); return OMAPCONF_ERR_ARG; } } dprintf("%s(%d, %lduV): sr_id=0x%02X VR_slave_address=0x%02X " "volt_reg_addr=0x%02X\n", __func__, vdd_id, uv, sr_id, VR_slave_address, volt_reg_addr); /* Smartreflex must not be running, disable it */ if (sr44xx_is_enabled(sr_id)) { printf("Warning: %s smartreflex is enabled. Disabling it.\n", voltdm44xx_get_name(vdd_id, voltdm_name)); fp = fopen(filename[sr_id], "w"); if (fp == NULL) { fprintf(stderr, "Could not open %s! Is debugfs mounted???\n\n", filename[sr_id]); return OMAPCONF_ERR_NOT_AVAILABLE; } ret = fwrite("0", sizeof(char), 1, fp); fclose(fp); if (ret != 1) { fprintf(stderr, "Could not write into %s!\n\n", filename[sr_id]); return OMAPCONF_ERR_UNEXPECTED; } printf("Smartreflex disabled.\n"); } /* Get vsel corresponding to target voltage */ vsel = smps_uvolt2vsel(vdd_id2smps_id(vdd_id), uv); dprintf("%s(): domain=%s, target voltage=%lfV, " "target vsel=0x%02X\n", __func__, voltdm44xx_get_name(vdd_id, voltdm_name), (double) ((double) uv / 1000000.0), vsel); /* Use VC BYPASS method to change voltage */ vc_bypass_value = (vsel << VC_BYPASS_DATA_SHIFT) | (volt_reg_addr << VC_BYPASS_REG_ADDR_SHIFT) | (VR_slave_address << VC_BYPASS_SLAVE_ADDR_SHIFT); dprintf("vc_bypass_value = 0x%08X\n", vc_bypass_value); ret = mem_write(OMAP4430_PRM_VC_VAL_BYPASS, vc_bypass_value); if (ret != 0) { fprintf(stderr, "Error: could not write into " "PRM_VC_VAL_BYPASS register!!! (%d)\n\n", ret); return OMAPCONF_ERR_REG_ACCESS; } vc_bypass_value |= VC_BYPASS_CMD_VALID_MASK; dprintf("vc_bypass_value = 0x%08X\n", vc_bypass_value); ret = mem_write(OMAP4430_PRM_VC_VAL_BYPASS, vc_bypass_value); if (ret != 0) { fprintf(stderr, "Error: could not write into " "PRM_VC_VAL_BYPASS register!!! (%d)\n\n", ret); return OMAPCONF_ERR_REG_ACCESS; } /* Wait for VC BYPASS command to be acknowledge */ dprintf("%s(): Wait for VC BYPASS command to be acknowledged...\n", __func__); do { ret = mem_read(OMAP4430_PRM_VC_VAL_BYPASS, &vc_bypass_value); if (ret != 0) { fprintf(stderr, "Error: could not read " "PRM_VC_VAL_BYPASS register!!! (%d)\n\n", ret); return OMAPCONF_ERR_REG_ACCESS; } } while ((vc_bypass_value & VC_BYPASS_CMD_VALID_MASK) != 0); dprintf("%s supply voltage set to %lfV.\n", voltdm44xx_get_name(vdd_id, voltdm_name), (double) ((double) uv / 1000000.0)); /* * Update VC ONVALUE voltage, so that new voltage does not get lost * after a power transition on this domain */ /* Get currently programmed voltage from VC register */ dprintf("%s(): Get currently programmed voltage " "(prm_vc_val_cmd_vdd_addr=0x%08X)\n", __func__, prm_vc_val_cmd_vdd_addr); if (mem_read(prm_vc_val_cmd_vdd_addr, &prm_vc_val_cmd_vdd) != 0) return OMAPCONF_ERR_REG_ACCESS; if (cpu_is_omap4460() && (vdd_id == OMAP4_VDD_MPU)) /* TPS62361 vsel length is 8-bit, not 6-bit as for TWL6030 */ vsel_len = 8; else vsel_len = 6; dprintf("%s(): %s: prm_vc_val_cmd_vdd=0x%08X, vsel_len=%u\n", __func__, voltdm44xx_get_name(vdd_id, voltdm_name), prm_vc_val_cmd_vdd, vsel_len); prm_vc_val_cmd_vdd &= ~(((1 << vsel_len) - 1) << OMAP4_ON_VOLTAGE); prm_vc_val_cmd_vdd |= (vsel << OMAP4_ON_VOLTAGE); dprintf("%s(): %s: now prm_vc_val_cmd_vdd = 0x%08X\n", __func__, voltdm44xx_get_name(vdd_id, voltdm_name), prm_vc_val_cmd_vdd); mem_write(prm_vc_val_cmd_vdd_addr, prm_vc_val_cmd_vdd); return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION mpu44xx_config_show * @BRIEF analyze MPU power configuration * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * @param[in] stream: output file stream * @DESCRIPTION analyze MPU power configuration *//*------------------------------------------------------------------------ */ int mpu44xx_config_show(FILE *stream) { unsigned int pm_pda_cpu0_pwrstctrl; unsigned int pm_pda_cpu0_pwrstst; unsigned int rm_pda_cpu0_context; unsigned int cm_pda_cpu0_clkctrl; unsigned int cm_pda_cpu0_clkstctrl; unsigned int pm_pda_cpu1_pwrstctrl; unsigned int pm_pda_cpu1_pwrstst; unsigned int rm_pda_cpu1_context; unsigned int cm_pda_cpu1_clkctrl; unsigned int cm_pda_cpu1_clkstctrl; unsigned int scu_cpu_power_status; char s0[32], s1[32]; unsigned int cm_clkmode_dpll_mpu; unsigned int cm_idlest_dpll_mpu; unsigned int cm_autoidle_dpll_mpu; omap4_dpll_params dpll_mpu_params; unsigned int pm_pwstctrl; unsigned int pm_pwstst; unsigned int cm_clkstctrl; unsigned int rm_context; unsigned int cm_clkctrl; int ret; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); if (!init_done) mpu44xx_regtable_init(); if (mem_read(OMAP4430_PM_PDA_CPU0_PWRSTCTRL, &pm_pda_cpu0_pwrstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_PDA_CPU0_PWRSTST, &pm_pda_cpu0_pwrstst) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT, &rm_pda_cpu0_context) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL, &cm_pda_cpu0_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_PDA_CPU0_CLKSTCTRL, &cm_pda_cpu0_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_PDA_CPU1_PWRSTCTRL, &pm_pda_cpu1_pwrstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_PDA_CPU1_PWRSTST, &pm_pda_cpu1_pwrstst) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT, &rm_pda_cpu1_context) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL, &cm_pda_cpu1_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_PDA_CPU1_CLKSTCTRL, &cm_pda_cpu1_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_SCU_CPU_POWER_STATUS, &scu_cpu_power_status) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_CLKMODE_DPLL_MPU, &cm_clkmode_dpll_mpu) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_IDLEST_DPLL_MPU, &cm_idlest_dpll_mpu) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_AUTOIDLE_DPLL_MPU, &cm_autoidle_dpll_mpu) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = dpll44xx_dpll_params_get(DPLL44XX_MPU, &dpll_mpu_params, 0); if (ret < 0) return ret; /* MPU LPRM config */ fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "MPU LPRM Configuration", "CPU0", "CPU1"); fprintf(stream, "|--------------------------------|-----------|-------" "----|\n"); pwrdm_state2string(s0, (pwrdm_state) extract_bitfield(pm_pda_cpu0_pwrstst, 0, 2)); pwrdm_state2string(s1, (pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstst, 0, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Current Power State", s0, s1); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Current Logic State", ((extract_bit(pm_pda_cpu0_pwrstst, 2) == 1) ? "ON" : "OFF"), ((extract_bit(pm_pda_cpu1_pwrstst, 2) == 1) ? "ON" : "OFF")); pwrdm_state2string(s0, (pwrdm_state) extract_bitfield(pm_pda_cpu0_pwrstst, 4, 2)); pwrdm_state2string(s1, (pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstst, 4, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Current L1$ State", s0, s1); pwrdm_state2string(s0, (pwrdm_state)extract_bitfield(pm_pda_cpu0_pwrstctrl, 0, 2)); pwrdm_state2string(s1, (pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstctrl, 0, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Standby Status", ((extract_bit(cm_pda_cpu0_clkctrl, 0) == 1) ? "STANDBY" : "RUNNING"), ((extract_bit(cm_pda_cpu1_clkctrl, 0) == 1) ? "STANDBY" : "RUNNING")); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "", "", ""); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Target Power State", s0, s1); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Logic State When Domain is RET", ((extract_bit(pm_pda_cpu0_pwrstctrl, 2) == 1) ? "RET" : "OFF"), ((extract_bit(pm_pda_cpu1_pwrstctrl, 2) == 1) ? "RET" : "OFF")); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Clock Control", clkdm_ctrl_mode_name_get((clkdm_ctrl_mode) extract_bitfield(cm_pda_cpu0_clkstctrl, 0, 2)), clkdm_ctrl_mode_name_get((clkdm_ctrl_mode) extract_bitfield(cm_pda_cpu1_clkstctrl, 0, 2))); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "", "", ""); if ((cpu_is_omap4430() && (cpu_revision_get() != REV_ES1_0)) || cpu_is_omap4460() || cpu_is_omap4470()) { pwrdm_state2string(s0, (pwrdm_state) extract_bitfield(pm_pda_cpu0_pwrstst, 24, 2)); pwrdm_state2string(s1, (pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstst, 24, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Last Power State", s0, s1); } fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Last L1$ Context", ((extract_bit(rm_pda_cpu0_context, 8) == 1) ? "LOST" : "RETAINED"), ((extract_bit(rm_pda_cpu1_context, 8) == 1) ? "LOST" : "RETAINED")); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Last CPU Context", ((extract_bit(rm_pda_cpu0_context, 0) == 1) ? "LOST" : "RETAINED"), ((extract_bit(rm_pda_cpu1_context, 0) == 1) ? "LOST" : "RETAINED")); fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "\n"); /* SCU Configuration */ fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "SCU Configuration", "CPU0", "CPU1"); fprintf(stream, "|--------------------------------|-----------|-------" "----|\n"); OMAPCONF_SCU_CPU_POWER_STATUS_2_STRING(s0, extract_bitfield(scu_cpu_power_status, 0, 2)); OMAPCONF_SCU_CPU_POWER_STATUS_2_STRING(s1, extract_bitfield(scu_cpu_power_status, 8, 2)); fprintf(stream, "| %-30s | %-9s | %-9s |\n", "CPU Power Status", s0, s1); fprintf(stream, "|---------------------------------------------------" "-----|\n"); fprintf(stream, "\n"); /* MPU Power Domain Configuration */ if (mem_read(OMAP4430_PM_MPU_PWRSTCTRL, &pm_pwstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_MPU_PWRSTST, &pm_pwstst) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = pwrdm44xx_config_show(stream, "MPU", OMAP4430_PM_MPU_PWRSTCTRL, pm_pwstctrl, OMAP4430_PM_MPU_PWRSTST, pm_pwstst); if (ret != 0) return ret; /* MPU Clock Domain Configuration */ if (mem_read(OMAP4430_CM_MPU_CLKSTCTRL, &cm_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = clkdm44xx_config_show(stream, "MPU", OMAP4430_CM_MPU_CLKSTCTRL, cm_clkstctrl); if (ret != 0) return ret; /* MPU Module Power Configuration */ if (mem_read(OMAP4430_CM_MPU_MPU_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_MPU_MPU_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "MPU", OMAP4430_CM_MPU_MPU_CLKCTRL, cm_clkctrl, OMAP4430_RM_MPU_MPU_CONTEXT, rm_context); if (ret != 0) return ret; /* MPU DPLL Configuration */ fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "| MPU DPLL Configuration " " |\n"); fprintf(stream, "|--------------------------------|-------------------" "----|\n"); fprintf(stream, "| %-30s | %-21s |\n", "Status", dpll_status_name_get((dpll_status) dpll_mpu_params.status)); sprintf(s0, "%d", (unsigned int) dpll_mpu_params.M2_speed); fprintf(stream, "| %-30s | %-21s |\n", "Clock Speed (MHz)", s0); fprintf(stream, "| %-30s | %-21s |\n", "Mode", dpll_mode_name_get((dpll_mode) dpll_mpu_params.mode)); fprintf(stream, "| %-30s | %-21s |\n", "Low-Power Mode", (dpll_mpu_params.lpmode == 1) ? "Enabled" : "Disabled"); fprintf(stream, "| %-30s | %-21s |\n", "Autoidle Mode", dpll_autoidle_mode_name_get((dpll_autoidle_mode) dpll_mpu_params.autoidle_mode)); fprintf(stream, "| %-30s | %-21s |\n", "M2 Output Autogating", (dpll_mpu_params.M2_autogating == 1) ? "Enabled" : "Disabled"); fprintf(stream, "|----------------------------------------------------" "----|\n"); fprintf(stream, "\nNB: type \"omapconf dplls cfg\" " "for detailed DPLL configuration.\n\n"); return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION mpu44xx_regtable_init * @BRIEF initialize reg_table fields (not possible statically) * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * @DESCRIPTION initialize reg_table fields (not possible statically) *//*------------------------------------------------------------------------ */ int mpu44xx_regtable_init(void) { int i = 0; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); /* Init PRCM MPU registers table */ strcpy(prcm_mpu_reg_table[i].name, "PM_PDA_CPU0_PWRSTCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_PM_PDA_CPU0_PWRSTCTRL; strcpy(prcm_mpu_reg_table[i].name, "PM_PDA_CPU0_PWRSTST"); prcm_mpu_reg_table[i++].addr = OMAP4430_PM_PDA_CPU0_PWRSTST; strcpy(prcm_mpu_reg_table[i].name, "RM_PDA_CPU0_CONTEXT"); prcm_mpu_reg_table[i++].addr = OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT; strcpy(prcm_mpu_reg_table[i].name, "RM_PDA_CPU0_RSTCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL; strcpy(prcm_mpu_reg_table[i].name, "CM_PDA_CPU0_CLKCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL; strcpy(prcm_mpu_reg_table[i].name, "CM_PDA_CPU0_CLKSTCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_PDA_CPU0_CLKSTCTRL; strcpy(prcm_mpu_reg_table[i].name, "PM_PDA_CPU1_PWRSTCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_PM_PDA_CPU1_PWRSTCTRL; strcpy(prcm_mpu_reg_table[i].name, "PM_PDA_CPU1_PWRSTST"); prcm_mpu_reg_table[i++].addr = OMAP4430_PM_PDA_CPU1_PWRSTST; strcpy(prcm_mpu_reg_table[i].name, "RM_PDA_CPU1_CONTEXT"); prcm_mpu_reg_table[i++].addr = OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT; strcpy(prcm_mpu_reg_table[i].name, "RM_PDA_CPU1_RSTCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL; strcpy(prcm_mpu_reg_table[i].name, "CM_PDA_CPU1_CLKCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL; strcpy(prcm_mpu_reg_table[i].name, "CM_PDA_CPU1_CLKSTCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_PDA_CPU1_CLKSTCTRL; strcpy(prcm_mpu_reg_table[i].name, "PM_MPU_PWRSTCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_PM_MPU_PWRSTCTRL; strcpy(prcm_mpu_reg_table[i].name, "PM_MPU_PWRSTST"); prcm_mpu_reg_table[i++].addr = OMAP4430_PM_MPU_PWRSTST; strcpy(prcm_mpu_reg_table[i].name, "RM_MPU_MPU_CONTEXT"); prcm_mpu_reg_table[i++].addr = OMAP4430_RM_MPU_MPU_CONTEXT; strcpy(prcm_mpu_reg_table[i].name, "CM_MPU_CLKSTCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_MPU_CLKSTCTRL; strcpy(prcm_mpu_reg_table[i].name, "CM_MPU_MPU_CLKCTRL"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_MPU_MPU_CLKCTRL; strcpy(prcm_mpu_reg_table[i].name, "CM_MPU_STATICDEP"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_MPU_STATICDEP; strcpy(prcm_mpu_reg_table[i].name, "CM_MPU_DYNAMICDEP"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_MPU_DYNAMICDEP; strcpy(prcm_mpu_reg_table[i].name, "SCU_CPU_POWER_STATUS"); prcm_mpu_reg_table[i++].addr = OMAP4430_SCU_CPU_POWER_STATUS; strcpy(prcm_mpu_reg_table[i].name, "CM_CLKMODE_DPLL_MPU"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_CLKMODE_DPLL_MPU; strcpy(prcm_mpu_reg_table[i].name, "CM_IDLEST_DPLL_MPU"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_IDLEST_DPLL_MPU; strcpy(prcm_mpu_reg_table[i].name, "CM_AUTOIDLE_DPLL_MPU"); prcm_mpu_reg_table[i++].addr = OMAP4430_CM_AUTOIDLE_DPLL_MPU; strcpy(prcm_mpu_reg_table[i].name, "PRM_IRQSTATUS_MPU_A9"); prcm_mpu_reg_table[i++].addr = OMAP4430_PRM_IRQSTATUS_MPU; strcpy(prcm_mpu_reg_table[i].name, "PRM_IRQSTATUS_MPU_A9_2"); prcm_mpu_reg_table[i++].addr = OMAP4430_PRM_IRQSTATUS_MPU_2; strcpy(prcm_mpu_reg_table[i].name, "PRM_IRQENABLE_MPU_A9"); prcm_mpu_reg_table[i++].addr = OMAP4430_PRM_IRQENABLE_MPU; strcpy(prcm_mpu_reg_table[i].name, "PRM_IRQENABLE_MPU_A9_2"); prcm_mpu_reg_table[i++].addr = OMAP4430_PRM_IRQENABLE_MPU_2; strcpy(prcm_mpu_reg_table[i].name, "END"); prcm_mpu_reg_table[i].addr = 0; /* ES2.0 updates */ if ((cpu_is_omap4430() && (cpu_revision_get() != REV_ES1_0)) || cpu_is_omap4460() || cpu_is_omap4470()) { strcpy(omap44xx_prm_irq_names[22], "VC_CORE_VPACK"); strcpy(omap44xx_prm_irq_names[7], "RESERVED"); strcpy(omap44xx_prm_irq_names[5], "RESERVED"); } init_done = 1; return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION twl603x_smps_offset_get * @BRIEF return SMPS regulator offset for a given rail * @RETURNS >0 voltage offset in microvolts * OMAPCONF_ERR_NOT_AVAILABLE * @param[in] vdd_id: voltage rail * @DESCRIPTION return SMPS regulator offset for a given rail *//*------------------------------------------------------------------------ */ unsigned long twl603x_smps_offset_get(voltdm44xx_id vdd_id) { int ret; unsigned int val; char product_name[256]; if (twl603x_is_twl6035()) return TWL6035_VOFFSET_UV; if (twl603x_data.voffset[vdd_id - 1] >= 0) goto twl603x_smps_offset_get_end; /* * TWL6030: * Starting ES2.x, Phoenix PMIC may use 709mV offset instead of 608mV * depending on setting: OFFSET=1: 709mV, OFFSET=0: 608mV. */ if (twl603x_is_twl6030() && twl603x_chip_revision_get() == 1.0) { dprintf("%s(%u): TWL60ES1 => TWL6030_VOFFSET_0_UV\n", __func__, vdd_id); twl603x_data.voffset[vdd_id - 1] = TWL6030_VOFFSET_0_UV; goto twl603x_smps_offset_get_end; } ret = i2cget(TWL6030_I2C_BUS, 0x48, 0xE0, &val); if (ret != 0) { fprintf(stderr, "%s(%u): could not read register! (%d)\n", __func__, vdd_id, ret); twl603x_data.voffset[vdd_id - 1] = TWL6030_VOFFSET_1_UV; goto twl603x_smps_offset_get_end; } dprintf("%s(%u): val=0x%02X\n", __func__, vdd_id, val); switch (vdd_id) { case OMAP4_VDD_MPU: if (cpu_is_omap4460()) { android_product_name_get(product_name); if (strstr(product_name, "Kindle") == NULL) fprintf(stderr, "%s(%u): invalid vdd_id! omap4460 uses TPS62361 for VDD_MPU\n", __func__, vdd_id); } val &= 0x08; break; case OMAP4_VDD_IVA: if (cpu_is_omap4470()) val &= 0x02; else val &= 0x10; break; case OMAP4_VDD_CORE: if (cpu_is_omap4460()) val &= 0x08; else if (cpu_is_omap4470()) val &= 0x10; else val &= 0x20; break; default: fprintf(stderr, "%s(%u): invalid vdd_id!\n", __func__, vdd_id); return TWL6030_VOFFSET_1_UV; } if (val != 0) twl603x_data.voffset[vdd_id - 1] = TWL6030_VOFFSET_1_UV; else twl603x_data.voffset[vdd_id - 1] = TWL6030_VOFFSET_0_UV; twl603x_smps_offset_get_end: dprintf("%s(%u): voffset=%lduV\n", __func__, vdd_id, twl603x_data.voffset[vdd_id - 1]); return twl603x_data.voffset[vdd_id - 1]; }
/* ------------------------------------------------------------------------*//** * @FUNCTION pwrdm44xx_config_show * @BRIEF analyze power domain configuration * @RETURNS 0 in case of error * @param[in,out] stream: output file * @param[in,out] name: domain name * @param[in] pm_pwstctrl_addr: PM_xyz_PWSTCTRL register address * @param[in] pm_pwstctrl: PM_xyz_PWSTCTRL register content * @param[in] pm_pwstst_addr: PM_xyz_PWSTST register address * @param[in] pm_pwstst: PM_xyz_PWSTST register content * @DESCRIPTION analyze power domain configuration *//*------------------------------------------------------------------------ */ int pwrdm44xx_config_show(FILE *stream, const char name[11], unsigned int pm_pwstctrl_addr, unsigned int pm_pwstctrl, unsigned int pm_pwstst_addr, unsigned int pm_pwstst) { char curr[32], tgt[32], last[32]; dprintf("%s(): name=%s\n", __func__, name); dprintf("%s(): pm_pwstctrl addr=0x%08X\n", __func__, pm_pwstctrl_addr); dprintf("%s(): pm_pwstctrl=0x%08X\n", __func__, pm_pwstctrl); dprintf("%s(): pm_pwstst addr=0x%08X\n", __func__, pm_pwstst_addr); dprintf("%s(): pm_pwstst=0x%08X\n", __func__, pm_pwstst); dprintf("\n"); fprintf(stream, "|---------------------------------------------------" "-----------|\n"); fprintf(stream, "| %-10s Power Domain Configuration " " |\n", name); fprintf(stream, "|---------------------------------------------------" "-----------|\n"); fprintf(stream, "| %-30s | %-7s | %-7s | %-7s |\n", "Power State", "Current", "Target", "Last"); fprintf(stream, "|--------------------------------|---------|--------" "-|---------|\n"); pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 0, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bitfield(pm_pwstctrl, 0, 2)); if ((cpu_is_omap4430() && (cpu_revision_get() != REV_ES1_0)) || cpu_is_omap4460() || cpu_is_omap4470()) { switch (pm_pwstst_addr) { case OMAP4430_PM_MPU_PWRSTST: case OMAP4430_PM_DSP_PWRSTST: case OMAP4430_PM_ABE_PWRSTST: case OMAP4430_PM_CORE_PWRSTST: case OMAP4430_PM_IVAHD_PWRSTST: case OMAP4430_PM_L3INIT_PWRSTST: case OMAP4430_PM_L4PER_PWRSTST: pwrdm_state2string(last, (pwrdm_state) extract_bitfield(pm_pwstst, 24, 2)); break; case OMAP4430_PM_CAM_PWRSTST: case OMAP4430_PM_DSS_PWRSTST: case OMAP4430_PM_GFX_PWRSTST: case OMAP4430_PM_EMU_PWRSTST: if (!cpu_is_omap4430()) pwrdm_state2string(last, (pwrdm_state) extract_bitfield(pm_pwstst, 24, 2)); else strcpy(last, ""); break; default: strcpy(last, ""); } } else { strcpy(last, ""); } fprintf(stream, "| %-30s | %-7s | %-7s | %-7s |\n", "Domain", curr, tgt, last); if ((pm_pwstctrl_addr == OMAP4430_PM_CAM_PWRSTCTRL) || (pm_pwstctrl_addr == OMAP4430_PM_EMU_PWRSTCTRL) || (pm_pwstctrl_addr == OMAP4430_PM_GFX_PWRSTCTRL)) { fprintf(stream, "| %-30s | %-7s | %-7s | |\n", "Logic", ((extract_bit(pm_pwstst, 2) == 1) ? "ON" : "OFF"), ""); } else { fprintf(stream, "| %-30s | %-7s | %-7s | |\n", "Logic", ((extract_bit(pm_pwstst, 2) == 1) ? "ON" : "OFF"), ((extract_bit(pm_pwstctrl, 2) == 1) ? "RET" : "OFF")); } fprintf(stream, "| %-30s | %-7s | %-7s | |\n", "Memory", "", ""); switch (pm_pwstctrl_addr) { case OMAP4430_PM_CORE_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 12, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 12)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " OCP_WP Bank & DMM Bank2", curr, tgt); break; default: break; } switch (pm_pwstctrl_addr) { case OMAP4430_PM_IVAHD_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 10, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 11)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " TCM2", curr, tgt); break; case OMAP4430_PM_CORE_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 10, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 11)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " MPU_M3 Unicache", curr, tgt); default: break; } switch (pm_pwstctrl_addr) { case OMAP4430_PM_MPU_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 8, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 10)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " RAM", curr, tgt); break; case OMAP4430_PM_DSP_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 8, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 10)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " EDMA", curr, tgt); break; case OMAP4430_PM_DSS_PWRSTCTRL: case OMAP4430_PM_CAM_PWRSTCTRL: case OMAP4430_PM_GFX_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " MEM", curr, tgt); break; case OMAP4430_PM_IVAHD_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 8, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 10)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " TCM1", curr, tgt); case OMAP4430_PM_CORE_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 8, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 10)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " MPU_M3 L2 RAM", curr, tgt); default: break; } switch (pm_pwstctrl_addr) { case OMAP4430_PM_ABE_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 8, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 10)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " PERIPHMEM", curr, tgt); pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " AESSMEM", curr, tgt); break; case OMAP4430_PM_MPU_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 6, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 9)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " L2$", curr, tgt); if (cpu_is_omap4430()) pwrdm_state2string(curr, extract_bitfield(pm_pwstst, 4, 2)); else strcpy(curr, ""); /* not available on OMAP44[60-70] */ pwrdm_state2string(tgt, extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " L1$", curr, tgt); break; case OMAP4430_PM_DSP_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 6, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 9)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " L2$", curr, tgt); pwrdm_state2string(curr, extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " L1$", curr, tgt); break; case OMAP4430_PM_IVAHD_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 6, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 9)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " SL2", curr, tgt); pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " HWA", curr, tgt); break; case OMAP4430_PM_L4PER_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 6, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 9)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " NONRETAINED", curr, tgt); pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " RETAINED", curr, tgt); break; case OMAP4430_PM_CORE_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 6, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 9)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " OCM RAM", curr, tgt); pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " DMA/ICR Bank & DMM Bank1", curr, tgt); break; case OMAP4430_PM_L3INIT_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bit(pm_pwstctrl, 8)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " L3INIT Bank1", curr, tgt); break; case OMAP4430_PM_EMU_PWRSTCTRL: pwrdm_state2string(curr, (pwrdm_state) extract_bitfield(pm_pwstst, 4, 2)); pwrdm_state2string(tgt, (pwrdm_state) extract_bitfield(pm_pwstctrl, 16, 2)); fprintf(stream, "| %-30s | %-7s | %-7s | |\n", " EMU Bank", curr, tgt); break; default: break; } fprintf(stream, "|---------------------------------------------------" "-----------|\n"); fprintf(stream, "| %-30s | %-27s |\n", "Ongoing Power Transition?", ((extract_bit(pm_pwstst, 20) == 1) ? "YES" : "NO")); fprintf(stream, "|---------------------------------------------------" "-----------|\n"); fprintf(stream, "\n"); return 0; }