void __init omap_usb_init(struct omap_usb_config *pdata) { if (cpu_is_omap7xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) omap_otg_init(pdata); else if (cpu_is_omap15xx()) omap_1510_usb_init(pdata); else printk(KERN_ERR "USB: No init for your chip yet\n"); }
void __init omap1_i2c_mux_pins(int bus_id) { if (cpu_is_omap7xx()) { omap_cfg_reg(I2C_7XX_SDA); omap_cfg_reg(I2C_7XX_SCL); } else { omap_cfg_reg(I2C_SDA); omap_cfg_reg(I2C_SCL); } }
/* * The amount of SRAM depends on the core type. * Note that we cannot try to test for SRAM here because writes * to secure SRAM will hang the system. Also the SRAM is not * yet mapped at this point. */ static void __init omap_detect_sram(void) { omap_sram_skip = SRAM_BOOTLOADER_SZ; if (cpu_class_is_omap2()) { if (is_sram_locked()) { if (cpu_is_omap34xx()) { omap_sram_start = OMAP3_SRAM_PUB_PA; if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) || (omap_type() == OMAP2_DEVICE_TYPE_SEC)) { omap_sram_size = 0x7000; /* 28K */ omap_sram_skip += SZ_16K; } else { omap_sram_size = 0x8000; /* 32K */ } } else if (cpu_is_omap44xx()) { omap_sram_start = OMAP4_SRAM_PUB_PA; omap_sram_size = 0xa000; /* 40K */ } else { omap_sram_start = OMAP2_SRAM_PUB_PA; omap_sram_size = 0x800; /* 2K */ } } else { if (cpu_is_am33xx()) { omap_sram_start = AM33XX_SRAM_PA; omap_sram_size = 0x10000; /* 64K */ } else if (cpu_is_omap34xx()) { omap_sram_start = OMAP3_SRAM_PA; omap_sram_size = 0x10000; /* 64K */ } else if (cpu_is_omap44xx()) { omap_sram_start = OMAP4_SRAM_PA; omap_sram_size = 0xe000; /* 56K */ } else { omap_sram_start = OMAP2_SRAM_PA; if (cpu_is_omap242x()) omap_sram_size = 0xa0000; /* 640K */ else if (cpu_is_omap243x()) omap_sram_size = 0x10000; /* 64K */ } } } else { omap_sram_start = OMAP1_SRAM_PA; if (cpu_is_omap7xx()) omap_sram_size = 0x32000; /* 200K */ else if (cpu_is_omap15xx()) omap_sram_size = 0x30000; /* 192K */ else if (cpu_is_omap1610() || cpu_is_omap1611() || cpu_is_omap1621() || cpu_is_omap1710()) omap_sram_size = 0x4000; /* 16K */ else { pr_err("Could not detect SRAM size\n"); omap_sram_size = 0x4000; } } }
/* * omap7xx_gpio_init needs to be done before * machine_init functions access gpio APIs. * Hence omap7xx_gpio_init is a postcore_initcall. */ static int __init omap7xx_gpio_init(void) { int i; if (!cpu_is_omap7xx()) return -EINVAL; for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++) platform_device_register(omap7xx_gpio_dev[i]); return 0; }
/* * Register MMC devices. */ static int __init omap_mmc_add(const char *name, int id, unsigned long base, unsigned long size, unsigned int irq, unsigned rx_req, unsigned tx_req, struct omap_mmc_platform_data *data) { struct platform_device *pdev; struct resource res[OMAP_MMC_NR_RES]; int ret; pdev = platform_device_alloc(name, id); if (!pdev) return -ENOMEM; memset(res, 0, OMAP_MMC_NR_RES * sizeof(struct resource)); res[0].start = base; res[0].end = base + size - 1; res[0].flags = IORESOURCE_MEM; res[1].start = res[1].end = irq; res[1].flags = IORESOURCE_IRQ; res[2].start = rx_req; res[2].name = "rx"; res[2].flags = IORESOURCE_DMA; res[3].start = tx_req; res[3].name = "tx"; res[3].flags = IORESOURCE_DMA; if (cpu_is_omap7xx()) data->slots[0].features = MMC_OMAP7XX; if (cpu_is_omap15xx()) data->slots[0].features = MMC_OMAP15XX; if (cpu_is_omap16xx()) data->slots[0].features = MMC_OMAP16XX; ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); if (ret == 0) ret = platform_device_add_data(pdev, data, sizeof(*data)); if (ret) goto fail; ret = platform_device_add(pdev); if (ret) goto fail; /* return device handle to board setup code */ data->dev = &pdev->dev; return 0; fail: platform_device_put(pdev); return ret; }
static int __init omap1_mcbsp_init(void) { if (!cpu_class_is_omap1()) return -ENODEV; if (cpu_is_omap7xx()) omap_mcbsp_count = OMAP7XX_MCBSP_COUNT; else if (cpu_is_omap15xx()) omap_mcbsp_count = OMAP15XX_MCBSP_COUNT; else if (cpu_is_omap16xx()) omap_mcbsp_count = OMAP16XX_MCBSP_COUNT; mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), GFP_KERNEL); if (!mcbsp_ptr) return -ENOMEM; if (cpu_is_omap7xx()) omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res_0, OMAP7XX_MCBSP_RES_SZ, omap7xx_mcbsp_pdata, OMAP7XX_MCBSP_COUNT); if (cpu_is_omap15xx()) omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res_0, OMAP15XX_MCBSP_RES_SZ, omap15xx_mcbsp_pdata, OMAP15XX_MCBSP_COUNT); if (cpu_is_omap16xx()) omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res_0, OMAP16XX_MCBSP_RES_SZ, omap16xx_mcbsp_pdata, OMAP16XX_MCBSP_COUNT); return omap_mcbsp_init(); }
int __init omap1_mux_init(void) { if (cpu_is_omap7xx()) { arch_mux_cfg.pins = omap7xx_pins; arch_mux_cfg.size = OMAP7XX_PINS_SZ; arch_mux_cfg.cfg_reg = omap1_cfg_reg; } if (cpu_is_omap15xx() || cpu_is_omap16xx()) { arch_mux_cfg.pins = omap1xxx_pins; arch_mux_cfg.size = OMAP1XXX_PINS_SZ; arch_mux_cfg.cfg_reg = omap1_cfg_reg; } return omap_mux_register(&arch_mux_cfg); }
/* * The amount of SRAM depends on the core type. * Note that we cannot try to test for SRAM here because writes * to secure SRAM will hang the system. Also the SRAM is not * yet mapped at this point. */ static void __init omap_detect_sram(void) { if (cpu_class_is_omap2()) { if (is_sram_locked()) { if (cpu_is_omap34xx()) { omap_sram_start = OMAP3_SRAM_PUB_PA; if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) || (omap_type() == OMAP2_DEVICE_TYPE_SEC)) { omap_sram_size = 0x7000; /* 28K */ } else { omap_sram_size = 0x8000; /* 32K */ } } else if (cpu_is_omap44xx()) { omap_sram_start = OMAP4_SRAM_START_PA; omap_sram_size = OMAP4_SRAM_SIZE; /* 56KB */ omap_sram_size -= OMAP4_SRAM_HS_RESERVE; omap_sram_start += OMAP4_SRAM_HS_RESERVE; } else if (cpu_is_omap54xx()) { omap_sram_start = OMAP4_SRAM_START_PA; omap_sram_size = OMAP5_SRAM_SIZE; /* 128KB */ omap_sram_size -= OMAP5_SRAM_HS_RESERVE; omap_sram_start += OMAP5_SRAM_HS_RESERVE; } else { omap_sram_start = OMAP2_SRAM_PUB_PA; omap_sram_size = 0x800; /* 2K */ } } else { if (cpu_is_am33xx()) { omap_sram_start = AM33XX_SRAM_PA; omap_sram_size = 0x10000; /* 64K */ } else if (cpu_is_omap34xx()) { omap_sram_start = OMAP3_SRAM_PA; omap_sram_size = 0x10000; /* 64K */ } else if (cpu_is_omap44xx()) { omap_sram_start = OMAP4_SRAM_START_PA; omap_sram_size = OMAP4_SRAM_SIZE; /* 56K */ omap_sram_size -= OMAP4_SRAM_GP_RESERVE; omap_sram_start += OMAP4_SRAM_GP_RESERVE; } else if (cpu_is_omap54xx()) { omap_sram_start = OMAP4_SRAM_START_PA; omap_sram_size = OMAP5_SRAM_SIZE; /* 128KB */ omap_sram_size -= OMAP5_SRAM_GP_RESERVE; omap_sram_start += OMAP5_SRAM_GP_RESERVE; } else { omap_sram_start = OMAP2_SRAM_PA; if (cpu_is_omap242x()) omap_sram_size = 0xa0000; /* 640K */ else if (cpu_is_omap243x()) omap_sram_size = 0x10000; /* 64K */ } } } else { omap_sram_start = OMAP1_SRAM_PA; if (cpu_is_omap7xx()) omap_sram_size = 0x32000; /* 200K */ else if (cpu_is_omap15xx()) omap_sram_size = 0x30000; /* 192K */ else if (cpu_is_omap1610() || cpu_is_omap1611() || cpu_is_omap1621() || cpu_is_omap1710()) omap_sram_size = 0x4000; /* 16K */ else { pr_err("Could not detect SRAM size\n"); omap_sram_size = 0x4000; } } }
int __init omap1_clk_init(void) { struct omap_clk *c; int crystal_type = 0; /* Default 12 MHz */ u32 reg; #ifdef CONFIG_DEBUG_LL /* * Resets some clocks that may be left on from bootloader, * but leaves serial clocks on. */ omap_writel(0x3 << 29, MOD_CONF_CTRL_0); #endif /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ reg = omap_readw(SOFT_REQ_REG) & (1 << 4); omap_writew(reg, SOFT_REQ_REG); if (!cpu_is_omap15xx()) omap_writew(0, SOFT_REQ_REG2); /* By default all idlect1 clocks are allowed to idle */ arm_idlect1_mask = ~0; for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) clk_preinit(c->lk.clk); cpu_mask = 0; if (cpu_is_omap1710()) cpu_mask |= CK_1710; if (cpu_is_omap16xx()) cpu_mask |= CK_16XX; if (cpu_is_omap1510()) cpu_mask |= CK_1510; if (cpu_is_omap7xx()) cpu_mask |= CK_7XX; if (cpu_is_omap310()) cpu_mask |= CK_310; for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) if (c->cpu & cpu_mask) { clkdev_add(&c->lk); clk_register(c->lk.clk); } /* Pointers to these clocks are needed by code in clock.c */ api_ck_p = clk_get(NULL, "api_ck"); ck_dpll1_p = clk_get(NULL, "ck_dpll1"); ck_ref_p = clk_get(NULL, "ck_ref"); if (cpu_is_omap7xx()) ck_ref.rate = 13000000; if (cpu_is_omap16xx() && crystal_type == 2) ck_ref.rate = 19200000; pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), omap_readw(ARM_CKCTL)); /* We want to be in syncronous scalable mode */ omap_writew(0x1000, ARM_SYSST); /* * Initially use the values set by bootloader. Determine PLL rate and * recalculate dependent clocks as if kernel had changed PLL or * divisors. See also omap1_clk_late_init() that can reprogram dpll1 * after the SRAM is initialized. */ { unsigned pll_ctl_val = omap_readw(DPLL_CTL); ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ if (pll_ctl_val & 0x10) { /* PLL enabled, apply multiplier and divisor */ if (pll_ctl_val & 0xf80) ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; } else { /* PLL disabled, apply bypass divisor */ switch (pll_ctl_val & 0xc) { case 0: break; case 0x4: ck_dpll1.rate /= 2; break; default: ck_dpll1.rate /= 4; break; } } }
/* * Note that on Innovator-1510 UART2 pins conflict with USB2. * By default UART2 does not work on Innovator-1510 if you have * USB OHCI enabled. To use UART2, you must disable USB2 first. */ void __init omap_serial_init(void) { int i; if (cpu_is_omap7xx()) { serial_platform_data[0].regshift = 0; serial_platform_data[1].regshift = 0; serial_platform_data[0].irq = INT_7XX_UART_MODEM_1; serial_platform_data[1].irq = INT_7XX_UART_MODEM_IRDA_2; } if (cpu_is_omap15xx()) { serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16; serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16; serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16; } for (i = 0; i < ARRAY_SIZE(serial_platform_data) - 1; i++) { /* Don't look at UARTs higher than 2 for omap7xx */ if (cpu_is_omap7xx() && i > 1) { serial_platform_data[i].membase = NULL; serial_platform_data[i].mapbase = 0; continue; } /* Static mapping, never released */ serial_platform_data[i].membase = ioremap(serial_platform_data[i].mapbase, SZ_2K); if (!serial_platform_data[i].membase) { printk(KERN_ERR "Could not ioremap uart%i\n", i); continue; } switch (i) { case 0: uart1_ck = clk_get(NULL, "uart1_ck"); if (IS_ERR(uart1_ck)) printk("Could not get uart1_ck\n"); else { clk_enable(uart1_ck); if (cpu_is_omap15xx()) clk_set_rate(uart1_ck, 12000000); } break; case 1: uart2_ck = clk_get(NULL, "uart2_ck"); if (IS_ERR(uart2_ck)) printk("Could not get uart2_ck\n"); else { clk_enable(uart2_ck); if (cpu_is_omap15xx()) clk_set_rate(uart2_ck, 12000000); else clk_set_rate(uart2_ck, 48000000); } break; case 2: uart3_ck = clk_get(NULL, "uart3_ck"); if (IS_ERR(uart3_ck)) printk("Could not get uart3_ck\n"); else { clk_enable(uart3_ck); if (cpu_is_omap15xx()) clk_set_rate(uart3_ck, 12000000); } break; } omap_serial_reset(&serial_platform_data[i]); } }
int __init omap1_clk_init(void) { struct omap_clk *c; const struct omap_clock_config *info; int crystal_type = 0; /* Default 12 MHz */ u32 reg, cpu_mask; #ifdef CONFIG_DEBUG_LL /* * Resets some clocks that may be left on from bootloader, * but leaves serial clocks on. */ omap_writel(0x3 << 29, MOD_CONF_CTRL_0); #endif /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ reg = omap_readw(SOFT_REQ_REG) & (1 << 4); omap_writew(reg, SOFT_REQ_REG); if (!cpu_is_omap15xx()) omap_writew(0, SOFT_REQ_REG2); clk_init(&omap1_clk_functions); /* By default all idlect1 clocks are allowed to idle */ arm_idlect1_mask = ~0; for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) clk_preinit(c->lk.clk); cpu_mask = 0; if (cpu_is_omap16xx()) cpu_mask |= CK_16XX; if (cpu_is_omap1510()) cpu_mask |= CK_1510; if (cpu_is_omap7xx()) cpu_mask |= CK_7XX; if (cpu_is_omap310()) cpu_mask |= CK_310; for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) if (c->cpu & cpu_mask) { clkdev_add(&c->lk); clk_register(c->lk.clk); } /* Pointers to these clocks are needed by code in clock.c */ api_ck_p = clk_get(NULL, "api_ck"); ck_dpll1_p = clk_get(NULL, "ck_dpll1"); ck_ref_p = clk_get(NULL, "ck_ref"); info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); if (info != NULL) { if (!cpu_is_omap15xx()) crystal_type = info->system_clock_type; } #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) ck_ref.rate = 13000000; #elif defined(CONFIG_ARCH_OMAP16XX) if (crystal_type == 2) ck_ref.rate = 19200000; #endif pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: " "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), omap_readw(ARM_CKCTL)); /* We want to be in syncronous scalable mode */ omap_writew(0x1000, ARM_SYSST); #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER /* Use values set by bootloader. Determine PLL rate and recalculate * dependent clocks as if kernel had changed PLL or divisors. */ { unsigned pll_ctl_val = omap_readw(DPLL_CTL); ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ if (pll_ctl_val & 0x10) { /* PLL enabled, apply multiplier and divisor */ if (pll_ctl_val & 0xf80) ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; } else { /* PLL disabled, apply bypass divisor */ switch (pll_ctl_val & 0xc) { case 0: break; case 0x4: ck_dpll1.rate /= 2; break; default: ck_dpll1.rate /= 4; break; } } }
static int __devinit mmc_omap_probe(struct platform_device *pdev) { struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; struct mmc_omap_host *host = NULL; struct resource *res; int i, ret = 0; int irq; if (pdata == NULL) { dev_err(&pdev->dev, "platform data missing\n"); return -ENXIO; } if (pdata->nr_slots == 0) { dev_err(&pdev->dev, "no slots\n"); return -ENXIO; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); irq = platform_get_irq(pdev, 0); if (res == NULL || irq < 0) return -ENXIO; res = request_mem_region(res->start, resource_size(res), pdev->name); if (res == NULL) return -EBUSY; host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL); if (host == NULL) { ret = -ENOMEM; goto err_free_mem_region; } INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work); INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work); INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command); setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer, (unsigned long) host); spin_lock_init(&host->clk_lock); setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host); spin_lock_init(&host->dma_lock); setup_timer(&host->dma_timer, mmc_omap_dma_timer, (unsigned long) host); spin_lock_init(&host->slot_lock); init_waitqueue_head(&host->slot_wq); host->pdata = pdata; host->dev = &pdev->dev; platform_set_drvdata(pdev, host); host->id = pdev->id; host->mem_res = res; host->irq = irq; host->use_dma = 1; host->dev->dma_mask = &pdata->dma_mask; host->dma_ch = -1; host->irq = irq; host->phys_base = host->mem_res->start; host->virt_base = ioremap(res->start, resource_size(res)); if (!host->virt_base) goto err_ioremap; host->iclk = clk_get(&pdev->dev, "ick"); if (IS_ERR(host->iclk)) { ret = PTR_ERR(host->iclk); goto err_free_mmc_host; } clk_enable(host->iclk); host->fclk = clk_get(&pdev->dev, "fck"); if (IS_ERR(host->fclk)) { ret = PTR_ERR(host->fclk); goto err_free_iclk; } ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host); if (ret) goto err_free_fclk; if (pdata->init != NULL) { ret = pdata->init(&pdev->dev); if (ret < 0) goto err_free_irq; } host->nr_slots = pdata->nr_slots; host->reg_shift = (cpu_is_omap7xx() ? 1 : 2); host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0); if (!host->mmc_omap_wq) goto err_plat_cleanup; for (i = 0; i < pdata->nr_slots; i++) { ret = mmc_omap_new_slot(host, i); if (ret < 0) { while (--i >= 0) mmc_omap_remove_slot(host->slots[i]); goto err_destroy_wq; } } return 0; err_destroy_wq: destroy_workqueue(host->mmc_omap_wq); err_plat_cleanup: if (pdata->cleanup) pdata->cleanup(&pdev->dev); err_free_irq: free_irq(host->irq, host); err_free_fclk: clk_put(host->fclk); err_free_iclk: clk_disable(host->iclk); clk_put(host->iclk); err_free_mmc_host: iounmap(host->virt_base); err_ioremap: kfree(host); err_free_mem_region: release_mem_region(res->start, resource_size(res)); return ret; }
static int __devinit mmc_omap_probe(struct platform_device *pdev) { struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; struct mmc_omap_host *host = NULL; struct resource *res; dma_cap_mask_t mask; unsigned sig; int i, ret = 0; int irq; if (pdata == NULL) { dev_err(&pdev->dev, "platform data missing\n"); return -ENXIO; } if (pdata->nr_slots == 0) { dev_err(&pdev->dev, "no slots\n"); return -ENXIO; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); irq = platform_get_irq(pdev, 0); if (res == NULL || irq < 0) return -ENXIO; res = request_mem_region(res->start, resource_size(res), pdev->name); if (res == NULL) return -EBUSY; host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL); if (host == NULL) { ret = -ENOMEM; goto err_free_mem_region; } INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work); INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work); INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command); setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer, (unsigned long) host); spin_lock_init(&host->clk_lock); setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host); spin_lock_init(&host->dma_lock); spin_lock_init(&host->slot_lock); init_waitqueue_head(&host->slot_wq); host->pdata = pdata; host->dev = &pdev->dev; platform_set_drvdata(pdev, host); host->id = pdev->id; host->mem_res = res; host->irq = irq; host->use_dma = 1; host->irq = irq; host->phys_base = host->mem_res->start; host->virt_base = ioremap(res->start, resource_size(res)); if (!host->virt_base) goto err_ioremap; host->iclk = clk_get(&pdev->dev, "ick"); if (IS_ERR(host->iclk)) { ret = PTR_ERR(host->iclk); goto err_free_mmc_host; } clk_enable(host->iclk); host->fclk = clk_get(&pdev->dev, "fck"); if (IS_ERR(host->fclk)) { ret = PTR_ERR(host->fclk); goto err_free_iclk; } dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask); host->dma_tx_burst = -1; host->dma_rx_burst = -1; if (cpu_is_omap24xx()) sig = host->id == 0 ? OMAP24XX_DMA_MMC1_TX : OMAP24XX_DMA_MMC2_TX; else sig = host->id == 0 ? OMAP_DMA_MMC_TX : OMAP_DMA_MMC2_TX; host->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig); #if 0 if (!host->dma_tx) { dev_err(host->dev, "unable to obtain TX DMA engine channel %u\n", sig); goto err_dma; } #else if (!host->dma_tx) dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n", sig); #endif if (cpu_is_omap24xx()) sig = host->id == 0 ? OMAP24XX_DMA_MMC1_RX : OMAP24XX_DMA_MMC2_RX; else sig = host->id == 0 ? OMAP_DMA_MMC_RX : OMAP_DMA_MMC2_RX; host->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig); #if 0 if (!host->dma_rx) { dev_err(host->dev, "unable to obtain RX DMA engine channel %u\n", sig); goto err_dma; } #else if (!host->dma_rx) dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n", sig); #endif ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host); if (ret) goto err_free_dma; if (pdata->init != NULL) { ret = pdata->init(&pdev->dev); if (ret < 0) goto err_free_irq; } host->nr_slots = pdata->nr_slots; host->reg_shift = (cpu_is_omap7xx() ? 1 : 2); host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0); if (!host->mmc_omap_wq) goto err_plat_cleanup; for (i = 0; i < pdata->nr_slots; i++) { ret = mmc_omap_new_slot(host, i); if (ret < 0) { while (--i >= 0) mmc_omap_remove_slot(host->slots[i]); goto err_destroy_wq; } } return 0; err_destroy_wq: destroy_workqueue(host->mmc_omap_wq); err_plat_cleanup: if (pdata->cleanup) pdata->cleanup(&pdev->dev); err_free_irq: free_irq(host->irq, host); err_free_dma: if (host->dma_tx) dma_release_channel(host->dma_tx); if (host->dma_rx) dma_release_channel(host->dma_rx); clk_put(host->fclk); err_free_iclk: clk_disable(host->iclk); clk_put(host->iclk); err_free_mmc_host: iounmap(host->virt_base); err_ioremap: kfree(host); err_free_mem_region: release_mem_region(res->start, resource_size(res)); return ret; }
/* * Intercept ioremap() requests for addresses in our fixed mapping regions. */ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type) { #ifdef CONFIG_ARCH_OMAP1 if (cpu_class_is_omap1()) { if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE)) return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT); } if (cpu_is_omap7xx()) { if (BETWEEN(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_SIZE)) return XLATE(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_START); if (BETWEEN(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_SIZE)) return XLATE(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_START); } if (cpu_is_omap15xx()) { if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE)) return XLATE(p, OMAP1510_DSP_BASE, OMAP1510_DSP_START); if (BETWEEN(p, OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_SIZE)) return XLATE(p, OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_START); } if (cpu_is_omap16xx()) { if (BETWEEN(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_SIZE)) return XLATE(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_START); if (BETWEEN(p, OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_SIZE)) return XLATE(p, OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_START); } #endif #ifdef CONFIG_ARCH_OMAP2 if (cpu_is_omap24xx()) { if (BETWEEN(p, L3_24XX_PHYS, L3_24XX_SIZE)) return XLATE(p, L3_24XX_PHYS, L3_24XX_VIRT); if (BETWEEN(p, L4_24XX_PHYS, L4_24XX_SIZE)) return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT); } if (cpu_is_omap2420()) { if (BETWEEN(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_SIZE)) return XLATE(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_VIRT); if (BETWEEN(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE)) return XLATE(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE); if (BETWEEN(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_SIZE)) return XLATE(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_VIRT); } if (cpu_is_omap2430()) { if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE)) return XLATE(p, L4_WK_243X_PHYS, L4_WK_243X_VIRT); if (BETWEEN(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_SIZE)) return XLATE(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_VIRT); if (BETWEEN(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_SIZE)) return XLATE(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_VIRT); if (BETWEEN(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_SIZE)) return XLATE(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_VIRT); } #endif #ifdef CONFIG_ARCH_OMAP3 if (cpu_is_omap34xx()) { if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE)) return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT); if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE)) return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT); if (BETWEEN(p, L4_WK_34XX_PHYS, L4_WK_34XX_SIZE)) return XLATE(p, L4_WK_34XX_PHYS, L4_WK_34XX_VIRT); if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE)) return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT); if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE)) return XLATE(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_VIRT); if (BETWEEN(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_SIZE)) return XLATE(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_VIRT); if (BETWEEN(p, L4_PER_34XX_PHYS, L4_PER_34XX_SIZE)) return XLATE(p, L4_PER_34XX_PHYS, L4_PER_34XX_VIRT); if (BETWEEN(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_SIZE)) return XLATE(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_VIRT); } #endif #ifdef CONFIG_ARCH_OMAP4 if (cpu_is_omap44xx()) { if (BETWEEN(p, L3_44XX_PHYS, L3_44XX_SIZE)) return XLATE(p, L3_44XX_PHYS, L3_44XX_VIRT); if (BETWEEN(p, L4_44XX_PHYS, L4_44XX_SIZE)) return XLATE(p, L4_44XX_PHYS, L4_44XX_VIRT); if (BETWEEN(p, L4_WK_44XX_PHYS, L4_WK_44XX_SIZE)) return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT); if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE)) return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT); if (BETWEEN(p, OMAP44XX_EMIF1_PHYS, OMAP44XX_EMIF1_SIZE)) return XLATE(p, OMAP44XX_EMIF1_PHYS, \ OMAP44XX_EMIF1_VIRT); if (BETWEEN(p, OMAP44XX_EMIF2_PHYS, OMAP44XX_EMIF2_SIZE)) return XLATE(p, OMAP44XX_EMIF2_PHYS, \ OMAP44XX_EMIF2_VIRT); if (BETWEEN(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_SIZE)) return XLATE(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_VIRT); if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE)) return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT); if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE)) return XLATE(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_VIRT); } #endif return __arm_ioremap(p, size, type); }
void __init omap_init_irq(void) { int i, j; #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) if (cpu_is_omap7xx()) { irq_banks = omap7xx_irq_banks; irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks); } #endif #ifdef CONFIG_ARCH_OMAP15XX if (cpu_is_omap1510()) { irq_banks = omap1510_irq_banks; irq_bank_count = ARRAY_SIZE(omap1510_irq_banks); } if (cpu_is_omap310()) { irq_banks = omap310_irq_banks; irq_bank_count = ARRAY_SIZE(omap310_irq_banks); } #endif #if defined(CONFIG_ARCH_OMAP16XX) if (cpu_is_omap16xx()) { irq_banks = omap1610_irq_banks; irq_bank_count = ARRAY_SIZE(omap1610_irq_banks); } #endif printk("Total of %i interrupts in %i interrupt banks\n", irq_bank_count * 32, irq_bank_count); /* Mask and clear all interrupts */ for (i = 0; i < irq_bank_count; i++) { irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET); irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET); } /* Clear any pending interrupts */ irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET); irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET); /* Enable interrupts in global mask */ if (cpu_is_omap7xx()) irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET); /* Install the interrupt handlers for each bank */ for (i = 0; i < irq_bank_count; i++) { for (j = i * 32; j < (i + 1) * 32; j++) { int irq_trigger; irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); omap_irq_set_cfg(j, 0, 0, irq_trigger); set_irq_chip(j, &omap_irq_chip); set_irq_handler(j, handle_level_irq); set_irq_flags(j, IRQF_VALID); } } /* Unmask level 2 handler */ if (cpu_is_omap7xx()) omap_unmask_irq(INT_7XX_IH2_IRQ); else if (cpu_is_omap15xx()) omap_unmask_irq(INT_1510_IH2_IRQ); else if (cpu_is_omap16xx()) omap_unmask_irq(INT_1610_IH2_IRQ); }
int omap_request_dma(int dev_id, const char *dev_name, void (*callback)(int lch, u16 ch_status, void *data), void *data, int *dma_ch_out) { int ch, free_ch = -1; unsigned long flags; struct omap_dma_lch *chan; spin_lock_irqsave(&dma_chan_lock, flags); for (ch = 0; ch < dma_chan_count; ch++) { if (free_ch == -1 && dma_chan[ch].dev_id == -1) { free_ch = ch; if (dev_id == 0) break; } } if (free_ch == -1) { spin_unlock_irqrestore(&dma_chan_lock, flags); return -EBUSY; } chan = dma_chan + free_ch; chan->dev_id = dev_id; if (cpu_class_is_omap1()) clear_lch_regs(free_ch); if (cpu_class_is_omap2()) omap_clear_dma(free_ch); spin_unlock_irqrestore(&dma_chan_lock, flags); chan->dev_name = dev_name; chan->callback = callback; chan->data = data; chan->flags = 0; #ifndef CONFIG_ARCH_OMAP1 if (cpu_class_is_omap2()) { chan->chain_id = -1; chan->next_linked_ch = -1; } #endif chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; if (cpu_class_is_omap1()) chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; else if (cpu_class_is_omap2()) chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ; if (cpu_is_omap16xx()) { /* If the sync device is set, configure it dynamically. */ if (dev_id != 0) { set_gdma_dev(free_ch + 1, dev_id); dev_id = free_ch + 1; } /* * Disable the 1510 compatibility mode and set the sync device * id. */ dma_write(dev_id | (1 << 10), CCR(free_ch)); } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) { dma_write(dev_id, CCR(free_ch)); } if (cpu_class_is_omap2()) { omap2_enable_irq_lch(free_ch); omap_enable_channel_irq(free_ch); /* Clear the CSR register and IRQ status register */ dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch)); dma_write(1 << free_ch, IRQSTATUS_L0); } *dma_ch_out = free_ch; return 0; }
/* * Intercept ioremap() requests for addresses in our fixed mapping regions. */ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type) { WARN(!initialized, "Do not use ioremap before init_early\n"); #ifdef CONFIG_ARCH_OMAP1 if (cpu_class_is_omap1()) { if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE)) return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT); } if (cpu_is_omap7xx()) { if (BETWEEN(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_SIZE)) return XLATE(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_START); if (BETWEEN(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_SIZE)) return XLATE(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_START); } if (cpu_is_omap15xx()) { if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE)) return XLATE(p, OMAP1510_DSP_BASE, OMAP1510_DSP_START); if (BETWEEN(p, OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_SIZE)) return XLATE(p, OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_START); } if (cpu_is_omap16xx()) { if (BETWEEN(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_SIZE)) return XLATE(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_START); if (BETWEEN(p, OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_SIZE)) return XLATE(p, OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_START); } #endif #ifdef CONFIG_ARCH_OMAP2 if (cpu_is_omap24xx()) { if (BETWEEN(p, L3_24XX_PHYS, L3_24XX_SIZE)) return XLATE(p, L3_24XX_PHYS, L3_24XX_VIRT); if (BETWEEN(p, L4_24XX_PHYS, L4_24XX_SIZE)) return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT); } if (cpu_is_omap2420()) { if (BETWEEN(p, DSP_MEM_2420_PHYS, DSP_MEM_2420_SIZE)) return XLATE(p, DSP_MEM_2420_PHYS, DSP_MEM_2420_VIRT); if (BETWEEN(p, DSP_IPI_2420_PHYS, DSP_IPI_2420_SIZE)) return XLATE(p, DSP_IPI_2420_PHYS, DSP_IPI_2420_SIZE); if (BETWEEN(p, DSP_MMU_2420_PHYS, DSP_MMU_2420_SIZE)) return XLATE(p, DSP_MMU_2420_PHYS, DSP_MMU_2420_VIRT); } if (cpu_is_omap2430()) { if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE)) return XLATE(p, L4_WK_243X_PHYS, L4_WK_243X_VIRT); if (BETWEEN(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_SIZE)) return XLATE(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_VIRT); if (BETWEEN(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_SIZE)) return XLATE(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_VIRT); if (BETWEEN(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_SIZE)) return XLATE(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_VIRT); } #endif #ifdef CONFIG_ARCH_OMAP3 if (cpu_is_ti816x()) { if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE)) return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT); } else if (cpu_is_omap34xx()) { if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE)) return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT); if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE)) return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT); if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE)) return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT); if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE)) return XLATE(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_VIRT); if (BETWEEN(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_SIZE)) return XLATE(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_VIRT); if (BETWEEN(p, L4_PER_34XX_PHYS, L4_PER_34XX_SIZE)) return XLATE(p, L4_PER_34XX_PHYS, L4_PER_34XX_VIRT); if (BETWEEN(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_SIZE)) return XLATE(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_VIRT); } #endif #ifdef CONFIG_ARCH_OMAP4 if (cpu_is_omap44xx()) { if (BETWEEN(p, L3_44XX_PHYS, L3_44XX_SIZE)) return XLATE(p, L3_44XX_PHYS, L3_44XX_VIRT); if (BETWEEN(p, L4_44XX_PHYS, L4_44XX_SIZE)) return XLATE(p, L4_44XX_PHYS, L4_44XX_VIRT); if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE)) return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT); if (BETWEEN(p, OMAP44XX_EMIF1_PHYS, OMAP44XX_EMIF1_SIZE)) return XLATE(p, OMAP44XX_EMIF1_PHYS, \ OMAP44XX_EMIF1_VIRT); if (BETWEEN(p, OMAP44XX_EMIF2_PHYS, OMAP44XX_EMIF2_SIZE)) return XLATE(p, OMAP44XX_EMIF2_PHYS, \ OMAP44XX_EMIF2_VIRT); if (BETWEEN(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_SIZE)) return XLATE(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_VIRT); if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE)) return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT); if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE)) return XLATE(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_VIRT); } #endif return __arm_ioremap_caller(p, size, type, __builtin_return_address(0)); }
void __init omap_otg_init(struct omap_usb_config *config) { u32 syscon; int status; int alt_pingroup = 0; /* NOTE: no bus or clock setup (yet?) */ syscon = omap_readl(OTG_SYSCON_1) & 0xffff; if (!(syscon & OTG_RESET_DONE)) pr_debug("USB resets not complete?\n"); //omap_writew(0, OTG_IRQ_EN); /* pin muxing and transceiver pinouts */ if (config->pins[0] > 2) /* alt pingroup 2 */ alt_pingroup = 1; syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config)); syscon |= omap_usb1_init(config->pins[1]); syscon |= omap_usb2_init(config->pins[2], alt_pingroup); pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); omap_writel(syscon, OTG_SYSCON_1); syscon = config->hmc_mode; syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */; #ifdef CONFIG_USB_OTG if (config->otg) syscon |= OTG_EN; #endif if (cpu_class_is_omap1()) pr_debug("USB_TRANSCEIVER_CTRL = %03x\n", omap_readl(USB_TRANSCEIVER_CTRL)); pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2)); omap_writel(syscon, OTG_SYSCON_2); printk("USB: hmc %d", config->hmc_mode); if (!alt_pingroup) printk(", usb2 alt %d wires", config->pins[2]); else if (config->pins[0]) printk(", usb0 %d wires%s", config->pins[0], is_usb0_device(config) ? " (dev)" : ""); if (config->pins[1]) printk(", usb1 %d wires", config->pins[1]); if (!alt_pingroup && config->pins[2]) printk(", usb2 %d wires", config->pins[2]); if (config->otg) printk(", Mini-AB on usb%d", config->otg - 1); printk("\n"); if (cpu_class_is_omap1()) { u16 w; /* leave USB clocks/controllers off until needed */ w = omap_readw(ULPD_SOFT_REQ); w &= ~SOFT_USB_CLK_REQ; omap_writew(w, ULPD_SOFT_REQ); w = omap_readw(ULPD_CLOCK_CTRL); w &= ~USB_MCLK_EN; w |= DIS_USB_PVCI_CLK; omap_writew(w, ULPD_CLOCK_CTRL); } syscon = omap_readl(OTG_SYSCON_1); syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN; #ifdef CONFIG_USB_GADGET_OMAP if (config->otg || config->register_dev) { syscon &= ~DEV_IDLE_EN; udc_device.dev.platform_data = config; /* IRQ numbers for omap7xx */ if(cpu_is_omap7xx()) { udc_resources[1].start = INT_7XX_USB_GENI; udc_resources[2].start = INT_7XX_USB_NON_ISO; udc_resources[3].start = INT_7XX_USB_ISO; } status = platform_device_register(&udc_device); if (status) pr_debug("can't register UDC device, %d\n", status); } #endif #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) if (config->otg || config->register_host) { syscon &= ~HST_IDLE_EN; ohci_device.dev.platform_data = config; if (cpu_is_omap7xx()) ohci_resources[1].start = INT_7XX_USB_HHC_1; status = platform_device_register(&ohci_device); if (status) pr_debug("can't register OHCI device, %d\n", status); } #endif #ifdef CONFIG_USB_OTG if (config->otg) { syscon &= ~OTG_IDLE_EN; otg_device.dev.platform_data = config; if (cpu_is_omap7xx()) otg_resources[1].start = INT_7XX_USB_OTG; status = platform_device_register(&otg_device); if (status) pr_debug("can't register OTG device, %d\n", status); } #endif pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); omap_writel(syscon, OTG_SYSCON_1); status = 0; }
static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) { u32 syscon1 = 0; if (cpu_is_omap24xx()) omap2_usb_devconf_clear(0, USB_BIDIR_TLL); if (nwires == 0) { if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { u32 l; /* pulldown D+/D- */ l = omap_readl(USB_TRANSCEIVER_CTRL); l &= ~(3 << 1); omap_writel(l, USB_TRANSCEIVER_CTRL); } return 0; } if (is_device) { if (cpu_is_omap24xx()) omap_cfg_reg(J20_24XX_USB0_PUEN); else omap_cfg_reg(W4_USB_PUEN); } /* internal transceiver (unavailable on 17xx, 24xx) */ if (!cpu_class_is_omap2() && nwires == 2) { u32 l; // omap_cfg_reg(P9_USB_DP); // omap_cfg_reg(R8_USB_DM); if (cpu_is_omap15xx()) { /* This works on 1510-Innovator */ return 0; } /* NOTES: * - peripheral should configure VBUS detection! * - only peripherals may use the internal D+/D- pulldowns * - OTG support on this port not yet written */ /* Don't do this for omap7xx -- it causes USB to not work correctly */ if (!cpu_is_omap7xx()) { l = omap_readl(USB_TRANSCEIVER_CTRL); l &= ~(7 << 4); if (!is_device) l |= (3 << 1); omap_writel(l, USB_TRANSCEIVER_CTRL); } return 3 << 16; } /* alternate pin config, external transceiver */ if (cpu_is_omap15xx()) { printk(KERN_ERR "no usb0 alt pin config on 15xx\n"); return 0; } if (cpu_is_omap24xx()) { omap_cfg_reg(K18_24XX_USB0_DAT); omap_cfg_reg(K19_24XX_USB0_TXEN); omap_cfg_reg(J14_24XX_USB0_SE0); if (nwires != 3) omap_cfg_reg(J18_24XX_USB0_RCV); } else { omap_cfg_reg(V6_USB0_TXD); omap_cfg_reg(W9_USB0_TXEN); omap_cfg_reg(W5_USB0_SE0); if (nwires != 3) omap_cfg_reg(Y5_USB0_RCV); } /* NOTE: SPEED and SUSP aren't configured here. OTG hosts * may be able to use I2C requests to set those bits along * with VBUS switching and overcurrent detection. */ if (cpu_class_is_omap1() && nwires != 6) { u32 l; l = omap_readl(USB_TRANSCEIVER_CTRL); l &= ~CONF_USB2_UNI_R; omap_writel(l, USB_TRANSCEIVER_CTRL); } switch (nwires) { case 3: syscon1 = 2; if (cpu_is_omap24xx()) omap2_usb_devconf_set(0, USB_BIDIR); break; case 4: syscon1 = 1; if (cpu_is_omap24xx()) omap2_usb_devconf_set(0, USB_BIDIR); break; case 6: syscon1 = 3; if (cpu_is_omap24xx()) { omap_cfg_reg(J19_24XX_USB0_VP); omap_cfg_reg(K20_24XX_USB0_VM); omap2_usb_devconf_set(0, USB_UNIDIR); } else { u32 l; omap_cfg_reg(AA9_USB0_VP); omap_cfg_reg(R9_USB0_VM); l = omap_readl(USB_TRANSCEIVER_CTRL); l |= CONF_USB2_UNI_R; omap_writel(l, USB_TRANSCEIVER_CTRL); } break; default: printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", 0, nwires); } return syscon1 << 16; }