static int __init pxa168_init(void) { if (cpu_is_pxa168()) { mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(pxa168_mfp_addr_map); pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); clks_register(ARRAY_AND_SIZE(pxa168_clkregs)); } return 0; }
static int __init pxa168_init(void) { if (cpu_is_pxa168()) { mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(pxa168_mfp_addr_map); pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); pxa168_clk_init(); } return 0; }
int pxa168_usb_phy_deinit(unsigned base) { if (cpu_is_pxa168()) u2o_clear(base, UTMI_OTG_ADDON, UTMI_OTG_ADDON_OTG_ON); u2o_clear(base, UTMI_CTRL, UTMI_CTRL_RXBUF_PDWN); u2o_clear(base, UTMI_CTRL, UTMI_CTRL_TXBUF_PDWN); u2o_clear(base, UTMI_CTRL, UTMI_CTRL_USB_CLK_EN); u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT); u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT); return 0; }
static int usb_phy_deinit_internal(void __iomem *base) { pr_info("Deinit usb phy!!!\n"); if (cpu_is_pxa168()) u2o_clear(base, UTMI_OTG_ADDON, UTMI_OTG_ADDON_OTG_ON); u2o_clear(base, UTMI_CTRL, UTMI_CTRL_RXBUF_PDWN); u2o_clear(base, UTMI_CTRL, UTMI_CTRL_TXBUF_PDWN); u2o_clear(base, UTMI_CTRL, UTMI_CTRL_USB_CLK_EN); u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT); u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT); return 0; }
void mfp_config(unsigned long *mfp_cfgs, int num) { unsigned long flags; int i, drv_b11 = 0, no_lpm = 0; #ifdef CONFIG_ARCH_MMP if (cpu_is_pxa910() || cpu_is_pxa988() || cpu_is_pxa986() || cpu_is_mmp2() || cpu_is_mmp3() || cpu_is_pxa1088()) drv_b11 = 1; if (cpu_is_pxa168() || cpu_is_pxa910()) no_lpm = 1; #elif defined(CONFIG_ARCH_PXA) if (cpu_is_pxa95x()) drv_b11 = 1; #endif spin_lock_irqsave(&mfp_spin_lock, flags); for (i = 0; i < num; i++, mfp_cfgs++) { unsigned long tmp, c = *mfp_cfgs; struct mfp_pin *p; int pin, af, drv, lpm, edge, pull; pin = MFP_PIN(c); BUG_ON(pin >= MFP_PIN_MAX); p = &mfp_table[pin]; af = MFP_AF(c); drv = MFP_DS(c); lpm = MFP_LPM_STATE(c); edge = MFP_LPM_EDGE(c); pull = MFP_PULL(c); if (drv_b11) drv = drv << 1; if (no_lpm) lpm = 0; tmp = MFPR_AF_SEL(af) | MFPR_DRIVE(drv); tmp |= mfpr_pull[pull] | mfpr_lpm[lpm] | mfpr_edge[edge]; p->mfpr_run = tmp; p->mfpr_lpm = p->mfpr_run; p->config = c; __mfp_config_run(p); } mfpr_sync(); spin_unlock_irqrestore(&mfp_spin_lock, flags); }
void mmp_arch_reset(char mode, const char *cmd) { int count = 10; static unsigned char data; if ((!cpu_is_pxa910()) && (!cpu_is_pxa168()) && (!cpu_is_pxa988()) && (!cpu_is_pxa986()) && (!cpu_is_pxa1088())) return; printk("%s (%c)\n", __func__, mode); switch (mode) { case 's': /* Jump into ROM at address 0 */ cpu_reset(0); break; case 'w': default: #if defined(CONFIG_MFD_D2199) if (is_panic) { /* dump buck1 voltage */ d2199_extern_reg_read(D2199_BUCK2PH_BUCK1_REG, &data); pr_info("buck1 voltage: 0x%x\n", data); d2199_extern_reg_write(D2199_BUCK2PH_BUCK1_REG, 0xd8); /* double check */ d2199_extern_reg_read(D2199_BUCK2PH_BUCK1_REG, &data); pr_info("buck1 voltage: 0x%x\n", data); } #endif while(count--) { flush_cache_all(); outer_flush_all(); do_wdt_reset(cmd); mdelay(1000); printk("Watchdog fail...retry\n"); } break; } }
static int __init pxa168_pm_init(void) { if (!cpu_is_pxa168()) return -EIO; if (sysfs_create_group(power_kobj, &attr_group)) return -1; dmc_membase = ioremap(0xb0000000, 0x00001000); sram_membase = ioremap(0xd1020000, 0x00020000); /* ex_gpio = GPIO_EXT0(1); if (gpio_request(ex_gpio, "EXP2_SYS_DIS_N")) { printk("EXP2_SYS_DIS_N Request Failed\n"); return -EIO; } currently not required */ suspend_set_ops(&pxa168_pm_ops); return 0; }
/* Using watchdog reset */ static void do_wdt_reset(const char *cmd) { u32 reg, backup; void __iomem *watchdog_virt_base; int i; int match = 0, count = 0; if (cpu_is_pxa910() || cpu_is_pxa988() || cpu_is_pxa986() || cpu_is_pxa1088()) watchdog_virt_base = CP_TIMERS2_VIRT_BASE; else if (cpu_is_pxa168()) watchdog_virt_base = TIMERS1_VIRT_BASE; else return; /*Hold cp to avoid reset watchdog*/ if (cpu_is_pxa910() || cpu_is_pxa988() || cpu_is_pxa986() || cpu_is_pxa1088()) { /*hold CP first */ reg = readl(MPMU_APRR) | MPMU_APRR_CPR; writel(reg, MPMU_APRR); udelay(10); /*CP reset MSA */ reg = readl(MPMU_CPRR) | MPMU_CPRR_DSPR | MPMU_CPRR_BBR; writel(reg, MPMU_CPRR); udelay(10); } /*If reboot by recovery, store info for uboot*/ if (cpu_is_pxa910() || cpu_is_pxa988() || cpu_is_pxa986() || cpu_is_pxa1088()) { if (cmd && !strcmp(cmd, "recovery")) { for (i = 0, backup = 0; i < 4; i++) { backup <<= 8; backup |= *(cmd + i); } do { writel(backup, REG_RTC_BR0); } while (readl(REG_RTC_BR0) != backup); } } /* reset/enable WDT clock */ writel(0x7, MPMU_WDTPCR); readl(MPMU_WDTPCR); writel(0x3, MPMU_WDTPCR); readl(MPMU_WDTPCR); /* enable WDT reset */ writel(0xbaba, watchdog_virt_base + TMR_WFAR); writel(0xeb10, watchdog_virt_base + TMR_WSAR); writel(0x3, watchdog_virt_base + TMR_WMER); /* negate hardware reset to the WDT after system reset */ reg = readl(MPMU_APRR) | MPMU_APRR_WDTR; writel(reg, MPMU_APRR); /* clear previous WDT status */ writel(0xbaba, watchdog_virt_base + TMR_WFAR); writel(0xeb10, watchdog_virt_base + TMR_WSAR); writel(0, watchdog_virt_base + TMR_WSR); match = readl(watchdog_virt_base + TMR_WMR); count = readl(watchdog_virt_base + TMR_WVR); /* set match counter */ writel(0xbaba, watchdog_virt_base + TMR_WFAR); writel(0xeb10, watchdog_virt_base + TMR_WSAR); writel((0x20 + count) & 0xFFFF, watchdog_virt_base + TMR_WMR); }
static int usb_phy_init_internal(void __iomem *base) { int loops; pr_info("Init usb phy!!!\n"); /* Initialize the USB PHY power */ if (cpu_is_pxa910()) { u2o_set(base, UTMI_CTRL, (1<<UTMI_CTRL_INPKT_DELAY_SOF_SHIFT) | (1<<UTMI_CTRL_PU_REF_SHIFT)); } u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT); u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT); /* UTMI_PLL settings */ u2o_clear(base, UTMI_PLL, UTMI_PLL_PLLVDD18_MASK | UTMI_PLL_PLLVDD12_MASK | UTMI_PLL_PLLCALI12_MASK | UTMI_PLL_FBDIV_MASK | UTMI_PLL_REFDIV_MASK | UTMI_PLL_ICP_MASK | UTMI_PLL_KVCO_MASK); u2o_set(base, UTMI_PLL, 0xee<<UTMI_PLL_FBDIV_SHIFT | 0xb<<UTMI_PLL_REFDIV_SHIFT | 3<<UTMI_PLL_PLLVDD18_SHIFT | 3<<UTMI_PLL_PLLVDD12_SHIFT | 3<<UTMI_PLL_PLLCALI12_SHIFT | 1<<UTMI_PLL_ICP_SHIFT | 3<<UTMI_PLL_KVCO_SHIFT); /* UTMI_TX */ u2o_clear(base, UTMI_TX, UTMI_TX_REG_EXT_FS_RCAL_EN_MASK | UTMI_TX_TXVDD12_MASK | UTMI_TX_CK60_PHSEL_MASK | UTMI_TX_IMPCAL_VTH_MASK | UTMI_TX_REG_EXT_FS_RCAL_MASK | UTMI_TX_AMP_MASK); u2o_set(base, UTMI_TX, 3<<UTMI_TX_TXVDD12_SHIFT | 4<<UTMI_TX_CK60_PHSEL_SHIFT | 4<<UTMI_TX_IMPCAL_VTH_SHIFT | 8<<UTMI_TX_REG_EXT_FS_RCAL_SHIFT | 3<<UTMI_TX_AMP_SHIFT); /* UTMI_RX */ u2o_clear(base, UTMI_RX, UTMI_RX_SQ_THRESH_MASK | UTMI_REG_SQ_LENGTH_MASK); u2o_set(base, UTMI_RX, 7<<UTMI_RX_SQ_THRESH_SHIFT | 2<<UTMI_REG_SQ_LENGTH_SHIFT); /* UTMI_IVREF */ if (cpu_is_pxa168()) /* fixing Microsoft Altair board interface with NEC hub issue - * Set UTMI_IVREF from 0x4a3 to 0x4bf */ u2o_write(base, UTMI_IVREF, 0x4bf); /* toggle VCOCAL_START bit of UTMI_PLL */ udelay(200); u2o_set(base, UTMI_PLL, VCOCAL_START); udelay(40); u2o_clear(base, UTMI_PLL, VCOCAL_START); /* toggle REG_RCAL_START bit of UTMI_TX */ udelay(400); u2o_set(base, UTMI_TX, REG_RCAL_START); udelay(40); u2o_clear(base, UTMI_TX, REG_RCAL_START); udelay(400); /* Make sure PHY PLL is ready */ loops = 0; while ((u2o_get(base, UTMI_PLL) & PLL_READY) == 0) { mdelay(1); loops++; if (loops > 100) { printk(KERN_WARNING "calibrate timeout, UTMI_PLL %x\n", u2o_get(base, UTMI_PLL)); break; } } if (cpu_is_pxa168()) { u2o_set(base, UTMI_RESERVE, 1 << 5); /* Turn on UTMI PHY OTG extension */ u2o_write(base, UTMI_OTG_ADDON, 1); } return 0; }
/******************************************************************** * USB 2.0 OTG controller */ int pxa168_usb_phy_init(unsigned base) { static int init_done; int count; if (init_done) { printk(KERN_DEBUG "re-init phy\n\n"); /* return; */ } /* enable the pull up */ if (cpu_is_pxa910_z0()) { if (cpu_is_pxa910()) { u32 U2H_UTMI_CTRL = (u32)ioremap_nocache(0xc0000004, 4); writel(1<<20, U2H_UTMI_CTRL); } } /* Initialize the USB PHY power */ if (cpu_is_pxa910()) { u2o_set(base, UTMI_CTRL, (1<<UTMI_CTRL_INPKT_DELAY_SOF_SHIFT) | (1<<UTMI_CTRL_PU_REF_SHIFT)); } u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT); u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT); /* UTMI_PLL settings */ u2o_clear(base, UTMI_PLL, UTMI_PLL_PLLVDD18_MASK | UTMI_PLL_PLLVDD12_MASK | UTMI_PLL_PLLCALI12_MASK | UTMI_PLL_FBDIV_MASK | UTMI_PLL_REFDIV_MASK | UTMI_PLL_ICP_MASK | UTMI_PLL_KVCO_MASK); u2o_set(base, UTMI_PLL, 0xee<<UTMI_PLL_FBDIV_SHIFT | 0xb<<UTMI_PLL_REFDIV_SHIFT | 3<<UTMI_PLL_PLLVDD18_SHIFT | 3<<UTMI_PLL_PLLVDD12_SHIFT | 3<<UTMI_PLL_PLLCALI12_SHIFT | 2<<UTMI_PLL_ICP_SHIFT | 3<<UTMI_PLL_KVCO_SHIFT); /* UTMI_TX */ u2o_clear(base, UTMI_TX, UTMI_TX_TXVDD12_MASK | UTMI_TX_CK60_PHSEL_MASK | UTMI_TX_IMPCAL_VTH_MASK); u2o_set(base, UTMI_TX, 3<<UTMI_TX_TXVDD12_SHIFT | 4<<UTMI_TX_CK60_PHSEL_SHIFT | 5<<UTMI_TX_IMPCAL_VTH_SHIFT); /* UTMI_RX */ u2o_clear(base, UTMI_RX, UTMI_RX_SQ_THRESH_MASK | UTMI_REG_SQ_LENGTH_MASK); if (cpu_is_pxa168()) u2o_set(base, UTMI_RX, 7<<UTMI_RX_SQ_THRESH_SHIFT | 2<<UTMI_REG_SQ_LENGTH_SHIFT); else u2o_set(base, UTMI_RX, 0xa<<UTMI_RX_SQ_THRESH_SHIFT | 2<<UTMI_REG_SQ_LENGTH_SHIFT); /* UTMI_IVREF */ if (cpu_is_pxa168()) /* fixing Microsoft Altair board interface with NEC hub issue - * Set UTMI_IVREF from 0x4a3 to 0x4bf */ u2o_write(base, UTMI_IVREF, 0x4bf); /* calibrate */ count = 10000; while(((u2o_get(base, UTMI_PLL) & PLL_READY)==0) && count--); if (count <= 0) printk("%s %d: calibrate timeout, UTMI_PLL %x\n", __func__, __LINE__, u2o_get(base, UTMI_PLL)); /* toggle VCOCAL_START bit of UTMI_PLL */ udelay(200); u2o_set(base, UTMI_PLL, VCOCAL_START); udelay(40); u2o_clear(base, UTMI_PLL, VCOCAL_START); /* toggle REG_RCAL_START bit of UTMI_TX */ udelay(200); u2o_set(base, UTMI_TX, REG_RCAL_START); udelay(40); u2o_clear(base, UTMI_TX, REG_RCAL_START); udelay(200); /* make sure phy is ready */ count = 1000; while(((u2o_get(base, UTMI_PLL) & PLL_READY)==0) && count--); if (count <= 0) printk("%s %d: calibrate timeout, UTMI_PLL %x\n", __func__, __LINE__, u2o_get(base, UTMI_PLL)); if (cpu_is_pxa168()) { u2o_set(base, UTMI_RESERVE, 1<<5); u2o_write(base, UTMI_OTG_ADDON, 1); /* Turn on UTMI PHY OTG extension */ } init_done = 1; return 0; }