int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
{
int ret;
if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
}
if (cpu_is_pxa27x()) {
/* Use GPIO 113 as AC97 Reset on Bulverde */
pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
if (IS_ERR(ac97conf_clk)) {
ret = PTR_ERR(ac97conf_clk);
ac97conf_clk = NULL;
goto err_conf;
}
}
ac97_clk = clk_get(&dev->dev, "AC97CLK");
if (IS_ERR(ac97_clk)) {
ret = PTR_ERR(ac97_clk);
ac97_clk = NULL;
goto err_clk;
}
ret = clk_enable(ac97_clk);
if (ret)
goto err_clk2;
ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL);
if (ret < 0)
goto err_irq;
return 0;
err_irq:
GCR |= GCR_ACLINK_OFF;
err_clk2:
clk_put(ac97_clk);
ac97_clk = NULL;
err_clk:
if (ac97conf_clk) {
clk_put(ac97conf_clk);
ac97conf_clk = NULL;
}
err_conf:
return ret;
}
int pxa2xx_ac97_hw_resume(void)
{
if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
}
if (cpu_is_pxa27x()) {
/* Use GPIO 113 or 95 as AC97 Reset on Bulverde */
set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
}
clk_enable(ac97_clk);
return 0;
}
int pxa2xx_ac97_hw_resume(void)
{
if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
}
if (cpu_is_pxa27x()) {
/* Use GPIO 113 as AC97 Reset on Bulverde */
pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
}
clk_enable(ac97_clk);
return 0;
}
bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
{
#ifdef CONFIG_PXA25x
if (cpu_is_pxa25x())
pxa_ac97_cold_pxa25x();
else
#endif
#ifdef CONFIG_PXA27x
if (cpu_is_pxa27x())
pxa_ac97_cold_pxa27x();
else
#endif
#ifdef CONFIG_PXA3xx
if (cpu_is_pxa3xx())
pxa_ac97_cold_pxa3xx();
else
#endif
BUG();
if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) {
printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
__func__, gsr_bits);
return false;
}
return true;
}
static int pxa27x_start_hc(struct device *dev)
{
int retval = 0;
struct pxaohci_platform_data *inf;
inf = dev->platform_data;
clk_enable(usb_clk);
UHCHR |= UHCHR_FHR;
udelay(11);
UHCHR &= ~UHCHR_FHR;
UHCHR |= UHCHR_FSBIR;
while (UHCHR & UHCHR_FSBIR)
cpu_relax();
if (inf->init)
retval = inf->init(dev);
if (retval < 0)
return retval;
UHCHR &= ~UHCHR_SSE;
UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
/* Clear any OTG Pin Hold */
if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
PSSR |= PSSR_OTGPH;
return 0;
}
bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
{
unsigned long gsr;
#ifdef CONFIG_PXA25x
if (cpu_is_pxa25x())
pxa_ac97_warm_pxa25x();
else
#endif
#ifdef CONFIG_PXA27x
if (cpu_is_pxa27x())
pxa_ac97_warm_pxa27x();
else
#endif
#ifdef CONFIG_PXA3xx
if (cpu_is_pxa3xx())
pxa_ac97_warm_pxa3xx();
else
#endif
BUG();
gsr = GSR | gsr_bits;
if (!(gsr & (GSR_PCR | GSR_SCR))) {
printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
__func__, gsr);
return false;
}
return true;
}
void __init pxa_init_irq(int irq_nr, set_wake_t fn)
{
int irq, i;
BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
pxa_internal_irq_nr = irq_nr;
for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) {
_ICMR(irq) = 0; /* disable all IRQs */
_ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */
}
/* initialize interrupt priority */
if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
for (i = 0; i < irq_nr; i++)
IPR(i) = i | (1 << 31);
}
/* only unmasked interrupts kick us out of idle */
ICCR = 1;
for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) {
set_irq_chip(irq, &pxa_internal_irq_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
pxa_internal_irq_chip.set_wake = fn;
pxa_init_low_gpio_irq(fn);
}
static void pxa2xx_ac97_warm_reset(struct snd_ac97 *ac97)
{
int timeout = 100;
gsr_bits = 0;
if (cpu_is_pxa27x()) {
/* warm reset broken on Bulverde, so manually keep
* AC97 reset high */
pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH);
udelay(10);
GCR |= GCR_WARM_RST;
pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
udelay(500);
} else if (cpu_is_pxa3xx()) {
/* Can't use interrupts */
GCR |= GCR_WARM_RST;
while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
mdelay(1);
} else {
GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
}
if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
__FUNCTION__, gsr_bits);
GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
}
static void __exit cmx2xx_pcmcia_exit(void)
{
if (machine_is_armcore() && cpu_is_pxa25x())
cmx255_pcmcia_exit();
else if (machine_is_armcore() && cpu_is_pxa27x())
cmx270_pcmcia_exit();
}
unsigned int get_clk_frequency_khz(int info)
{
if (cpu_is_pxa25x())
return pxa25x_get_clk_frequency_khz(info);
else if (cpu_is_pxa27x())
return pxa27x_get_clk_frequency_khz(info);
return 0;
}
static void __init cmx2xx_map_io(void)
{
if (cpu_is_pxa25x())
pxa25x_map_io();
if (cpu_is_pxa27x())
pxa27x_map_io();
}
/*
* Return the current memory clock frequency in units of 10kHz
* Only pxa2xx_pcmcia device needs this API.
*/
unsigned int get_memclk_frequency_10khz(void)
{
if (cpu_is_pxa25x())
return pxa25x_get_memclk_frequency_10khz();
else if (cpu_is_pxa27x())
return pxa27x_get_memclk_frequency_10khz();
return 0;
}
/*
* For non device-tree builds, keep legacy timer init
*/
void __init pxa_timer_init(void)
{
if (cpu_is_pxa25x())
pxa25x_clocks_init();
if (cpu_is_pxa27x())
pxa27x_clocks_init();
if (cpu_is_pxa3xx())
pxa3xx_clocks_init();
pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000));
}
static int __init cmx2xx_pcmcia_init(void)
{
int ret = -ENODEV;
if (machine_is_armcore() && cpu_is_pxa25x())
ret = cmx255_pcmcia_init();
else if (machine_is_armcore() && cpu_is_pxa27x())
ret = cmx270_pcmcia_init();
return ret;
}
