void __init setup_arch(char **cmdline_p)
{
cpu_probe();
prom_init();
#ifdef CONFIG_EARLY_PRINTK
{
extern void setup_early_printk(void);
setup_early_printk();
}
#endif
cpu_report();
#if defined(CONFIG_VT)
#if defined(CONFIG_VGA_CONSOLE)
conswitchp = &vga_con;
#elif defined(CONFIG_DUMMY_CONSOLE)
conswitchp = &dummy_con;
#endif
#endif
arch_mem_init(cmdline_p);
resource_init();
#ifdef CONFIG_SMP
plat_smp_setup();
#endif
}
asmlinkage void __init init_arch(int argc, char **argv, char **envp,
int *prom_vec)
{
/* Determine which MIPS variant we are running on. */
cpu_probe();
prom_init(argc, argv, envp, prom_vec);
cpu_report();
/*
* Determine the mmu/cache attached to this machine, then flush the
* tlb and caches. On the r4xx0 variants this also sets CP0_WIRED to
* zero.
*/
load_mmu();
/*
* On IP27, I am seeing the TS bit set when the kernel is loaded.
* Maybe because the kernel is in ckseg0 and not xkphys? Clear it
* anyway ...
*/
clear_c0_status(ST0_BEV|ST0_TS|ST0_CU1|ST0_CU2|ST0_CU3);
set_c0_status(ST0_CU0|ST0_KX|ST0_SX|ST0_FR);
start_kernel();
}
/*
* First C code run on the secondary CPUs after being started up by
* the master.
*/
asmlinkage __cpuinit void start_secondary(void)
{
unsigned int cpu;
#ifdef CONFIG_MIPS_MT_SMTC
/* Only do cpu_probe for first TC of CPU */
if ((read_c0_tcbind() & TCBIND_CURTC) == 0)
#endif /* CONFIG_MIPS_MT_SMTC */
cpu_probe();
cpu_report();
per_cpu_trap_init();
prom_init_secondary();
/*
* XXX parity protection should be folded in here when it's converted
* to an option instead of something based on .cputype
*/
calibrate_delay();
preempt_disable();
cpu = smp_processor_id();
cpu_data[cpu].udelay_val = loops_per_jiffy;
prom_smp_finish();
cpu_set(cpu, cpu_callin_map);
cpu_idle();
}
/*
* First C code run on the secondary CPUs after being started up by
* the master.
*/
asmlinkage void start_secondary(void)
{
unsigned int cpu;
cpu_probe();
cpu_report();
per_cpu_trap_init();
prom_init_secondary();
/*
* XXX parity protection should be folded in here when it's converted
* to an option instead of something based on .cputype
*/
#ifndef CONFIG_CPU_CAVIUM_OCTEON
/* There is no reason to waste time doing this on Octeon. All the cores
are on the same chip and are the same speed by definition */
calibrate_delay();
#endif
preempt_disable();
cpu = smp_processor_id();
cpu_data[cpu].udelay_val = loops_per_jiffy;
prom_smp_finish();
cpu_set(cpu, cpu_callin_map);
cpu_idle();
}
asmlinkage void __init
init_arch(int argc, char **argv, char **envp, int *prom_vec)
{
unsigned int s;
/* Determine which MIPS variant we are running on. */
cpu_probe();
prom_init(argc, argv, envp, prom_vec);
#ifdef CONFIG_SGI_IP22
sgi_sysinit();
#endif
cpu_report();
/*
* Determine the mmu/cache attached to this machine,
* then flush the tlb and caches. On the r4xx0
* variants this also sets CP0_WIRED to zero.
*/
loadmmu();
/* Disable coprocessors and set FPU for 16/32 FPR register model */
clear_cp0_status(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_FR);
set_cp0_status(ST0_CU0);
start_kernel();
}
/*
* First C code run on the secondary CPUs after being started up by
* the master.
*/
asmlinkage void start_secondary(void)
{
unsigned int cpu;
cpu_probe();
cpu_report();
per_cpu_trap_init();
prom_init_secondary();
/*
* XXX parity protection should be folded in here when it's converted
* to an option instead of something based on .cputype
*/
calibrate_delay();
preempt_disable();
cpu = smp_processor_id();
cpu_data[cpu].udelay_val = loops_per_jiffy;
prom_smp_finish();
cpu_set(cpu, cpu_callin_map);
cpu_idle();
}
void __init setup_arch(char **cmdline_p)
{
/* the variable later on will be used in macros as well */
is_nlm_xlp2xx_compat = is_nlm_xlp2xx();
cpu_probe();
prom_init();
#ifdef CONFIG_EARLY_PRINTK
setup_early_printk();
#endif
cpu_report();
check_bugs_early();
#if defined(CONFIG_VT)
#if defined(CONFIG_VGA_CONSOLE)
conswitchp = &vga_con;
#elif defined(CONFIG_DUMMY_CONSOLE)
conswitchp = &dummy_con;
#endif
#endif
arch_mem_init(cmdline_p);
resource_init();
plat_smp_setup();
}
asmlinkage void __init init_arch(int argc, char **argv, char **envp,
int *prom_vec)
{
/* Determine which MIPS variant we are running on. */
cpu_probe();
prom_init(argc, argv, envp, prom_vec);
cpu_report();
/*
* Determine the mmu/cache attached to this machine, then flush the
* tlb and caches. On the r4xx0 variants this also sets CP0_WIRED to
* zero.
*/
load_mmu();
start_kernel();
}
asmlinkage void __init
init_arch(int argc, char **argv, char **envp, int *prom_vec)
{
/* Determine which MIPS variant we are running on. */
unsigned int s;
#ifdef CONFIG_RTL865X
char chipVersion[16]={0};
int rev;
GetChipVersion(chipVersion,sizeof(chipVersion), &rev);
printk("************************************\n");
printk("Powered by Realtek RTL%s SoC, rev %d\n",chipVersion, rev);
printk("************************************\n");
#endif
#ifdef CONFIG_RTL8186
printk("************************************\n");
printk("Powered by Realtek RTL8186 SoC\n");
printk("************************************\n");
#endif
cpu_probe();
prom_init(argc, argv, envp, prom_vec);
cpu_report();
/*
* Determine the mmu/cache attached to this machine,
* then flush the tlb and caches. On the r4xx0
* variants this also sets CP0_WIRED to zero.
*/
#ifdef CONFIG_RTL865X
printk("Init MMU (16 entries)\n");
#endif
load_mmu();
/* Disable coprocessors and set FPU for 16/32 FPR register model */
clear_c0_status(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_FR);
set_c0_status(ST0_CU0);
start_kernel();
}
void __init setup_arch(char **cmdline_p)
{
cpu_probe();
prom_init();
cpu_report();
#if defined(CONFIG_VT)
#if defined(CONFIG_VGA_CONSOLE)
conswitchp = &vga_con;
#elif defined(CONFIG_DUMMY_CONSOLE)
conswitchp = &dummy_con;
#endif
#endif
arch_mem_init(cmdline_p);
resource_init();
#ifdef CONFIG_SMP
plat_smp_setup();
#endif
}
