void mptsas_fix_scsi_task_mgmt_reply_endianness(MPIMsgSCSITaskMgmtReply *reply)
{
cpu_to_le32s(&reply->MsgContext);
cpu_to_le16s(&reply->IOCStatus);
cpu_to_le32s(&reply->IOCLogInfo);
cpu_to_le32s(&reply->TerminationCount);
}
void mptsas_fix_config_reply_endianness(MPIMsgConfigReply *reply)
{
cpu_to_le16s(&reply->ExtPageLength);
cpu_to_le32s(&reply->MsgContext);
cpu_to_le16s(&reply->IOCStatus);
cpu_to_le32s(&reply->IOCLogInfo);
}
static void mptsas_fix_sgentry_endianness_reply(MPISGEntry *sge)
{
if (sge->FlagsLength & MPI_SGE_FLAGS_64_BIT_ADDRESSING) {
cpu_to_le64s(&sge->u.Address64);
} else {
cpu_to_le32s(&sge->u.Address32);
}
cpu_to_le32s(&sge->FlagsLength);
}
void mptsas_fix_scsi_io_reply_endianness(MPIMsgSCSIIOReply *reply)
{
cpu_to_le32s(&reply->MsgContext);
cpu_to_le16s(&reply->IOCStatus);
cpu_to_le32s(&reply->IOCLogInfo);
cpu_to_le32s(&reply->TransferCount);
cpu_to_le32s(&reply->SenseCount);
cpu_to_le32s(&reply->ResponseInfo);
cpu_to_le16s(&reply->TaskTag);
}
void mptsas_fix_port_facts_reply_endianness(MPIMsgPortFactsReply *reply)
{
cpu_to_le32s(&reply->MsgContext);
cpu_to_le16s(&reply->IOCStatus);
cpu_to_le32s(&reply->IOCLogInfo);
cpu_to_le16s(&reply->MaxDevices);
cpu_to_le16s(&reply->PortSCSIID);
cpu_to_le16s(&reply->ProtocolFlags);
cpu_to_le16s(&reply->MaxPostedCmdBuffers);
cpu_to_le16s(&reply->MaxPersistentIDs);
cpu_to_le16s(&reply->MaxLanBuckets);
}
void mptsas_fix_event_notification_reply_endianness(MPIMsgEventNotifyReply *reply)
{
int length = reply->EventDataLength;
int i;
cpu_to_le16s(&reply->EventDataLength);
cpu_to_le32s(&reply->MsgContext);
cpu_to_le16s(&reply->IOCStatus);
cpu_to_le32s(&reply->IOCLogInfo);
cpu_to_le32s(&reply->Event);
cpu_to_le32s(&reply->EventContext);
/* Really depends on the event kind. This will do for now. */
for (i = 0; i < length; i++) {
cpu_to_le32s(&reply->Data[i]);
}
}
static int aqc111_write32_cmd(struct usbnet *dev, u8 cmd, u16 value,
u16 index, u32 *data)
{
u32 tmp = *data;
cpu_to_le32s(&tmp);
return aqc111_write_cmd(dev, cmd, value, index, sizeof(tmp), &tmp);
}
static int smsc95xx_tx_fixup(struct usbnet *dev,
void *buf, int len,
void *nbuf, int *nlen)
{
u32 tx_cmd_a, tx_cmd_b;
tx_cmd_a = (u32)(len) | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
cpu_to_le32s(&tx_cmd_a);
memcpy(nbuf, &tx_cmd_a, 4);
tx_cmd_b = (u32)(len);
cpu_to_le32s(&tx_cmd_b);
memcpy(nbuf + 4, &tx_cmd_b, 4);
memcpy(nbuf + 8, buf, len);
*nlen = len + 8;
return 0;
}
static int smsc95xx_write_reg(struct usbnet *dev, u32 index, u32 data)
{
int ret;
cpu_to_le32s(&data);
ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
USB_VENDOR_REQUEST_WRITE_REGISTER,
USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
00, index, &data, 4, USB_CTRL_SET_TIMEOUT);
if (ret < 0)
netdev_warn(dev->net, "Failed to write register index 0x%08x\n", index);
debug("%s: 0x%08x 0x%08x\n", __func__, index, data);
return ret;
}
void mptsas_fix_ioc_facts_reply_endianness(MPIMsgIOCFactsReply *reply)
{
cpu_to_le16s(&reply->MsgVersion);
cpu_to_le16s(&reply->HeaderVersion);
cpu_to_le32s(&reply->MsgContext);
cpu_to_le16s(&reply->IOCExceptions);
cpu_to_le16s(&reply->IOCStatus);
cpu_to_le32s(&reply->IOCLogInfo);
cpu_to_le16s(&reply->ReplyQueueDepth);
cpu_to_le16s(&reply->RequestFrameSize);
cpu_to_le16s(&reply->ProductID);
cpu_to_le32s(&reply->CurrentHostMfaHighAddr);
cpu_to_le16s(&reply->GlobalCredits);
cpu_to_le32s(&reply->CurrentSenseBufferHighAddr);
cpu_to_le16s(&reply->CurReplyFrameSize);
cpu_to_le32s(&reply->FWImageSize);
cpu_to_le32s(&reply->IOCCapabilities);
cpu_to_le16s(&reply->HighPriorityQueueDepth);
mptsas_fix_sgentry_endianness_reply(&reply->HostPageBufferSGE);
cpu_to_le32s(&reply->ReplyFifoHostSignalingAddr);
}
static void vdi_header_to_le(VdiHeader *header)
{
cpu_to_le32s(&header->signature);
cpu_to_le32s(&header->version);
cpu_to_le32s(&header->header_size);
cpu_to_le32s(&header->image_type);
cpu_to_le32s(&header->image_flags);
cpu_to_le32s(&header->offset_bmap);
cpu_to_le32s(&header->offset_data);
cpu_to_le32s(&header->cylinders);
cpu_to_le32s(&header->heads);
cpu_to_le32s(&header->sectors);
cpu_to_le32s(&header->sector_size);
cpu_to_le64s(&header->disk_size);
cpu_to_le32s(&header->block_size);
cpu_to_le32s(&header->block_extra);
cpu_to_le32s(&header->blocks_in_image);
cpu_to_le32s(&header->blocks_allocated);
cpu_to_le32s(&header->blocks_allocated);
uuid_convert(header->uuid_image);
uuid_convert(header->uuid_last_snap);
uuid_convert(header->uuid_link);
uuid_convert(header->uuid_parent);
}
/* Configure an endpoint */
int bdc_config_ep(struct bdc *bdc, struct bdc_ep *ep)
{
const struct usb_ss_ep_comp_descriptor *comp_desc;
const struct usb_endpoint_descriptor *desc;
u32 param0, param1, param2, cmd_sc;
u32 mps, mbs, mul, si;
int ret;
desc = ep->desc;
comp_desc = ep->comp_desc;
cmd_sc = mul = mbs = param2 = 0;
param0 = lower_32_bits(ep->bd_list.bd_table_array[0]->dma);
param1 = upper_32_bits(ep->bd_list.bd_table_array[0]->dma);
cpu_to_le32s(¶m0);
cpu_to_le32s(¶m1);
dev_dbg(bdc->dev, "%s: param0=%08x param1=%08x",
__func__, param0, param1);
si = desc->bInterval;
si = clamp_val(si, 1, 16) - 1;
mps = usb_endpoint_maxp(desc);
mps &= 0x7ff;
param2 |= mps << MP_SHIFT;
param2 |= usb_endpoint_type(desc) << EPT_SHIFT;
switch (bdc->gadget.speed) {
case USB_SPEED_SUPER:
if (usb_endpoint_xfer_int(desc) ||
usb_endpoint_xfer_isoc(desc)) {
param2 |= si;
if (usb_endpoint_xfer_isoc(desc) && comp_desc)
mul = comp_desc->bmAttributes;
}
param2 |= mul << EPM_SHIFT;
if (comp_desc)
mbs = comp_desc->bMaxBurst;
param2 |= mbs << MB_SHIFT;
break;
case USB_SPEED_HIGH:
if (usb_endpoint_xfer_isoc(desc) ||
usb_endpoint_xfer_int(desc)) {
param2 |= si;
mbs = (usb_endpoint_maxp(desc) & 0x1800) >> 11;
param2 |= mbs << MB_SHIFT;
}
break;
case USB_SPEED_FULL:
case USB_SPEED_LOW:
/* the hardware accepts SI in 125usec range */
if (usb_endpoint_xfer_isoc(desc))
si += 3;
/*
* FS Int endpoints can have si of 1-255ms but the controller
* accepts 2^bInterval*125usec, so convert ms to nearest power
* of 2
*/
if (usb_endpoint_xfer_int(desc))
si = fls(desc->bInterval * 8) - 1;
param2 |= si;
break;
default:
dev_err(bdc->dev, "UNKNOWN speed ERR\n");
return -EINVAL;
}
void mptsas_fix_port_enable_reply_endianness(MPIMsgPortEnableReply *reply)
{
cpu_to_le32s(&reply->MsgContext);
cpu_to_le16s(&reply->IOCStatus);
cpu_to_le32s(&reply->IOCLogInfo);
}
void mptsas_fix_ioc_init_reply_endianness(MPIMsgIOCInitReply *reply)
{
cpu_to_le32s(&reply->MsgContext);
cpu_to_le16s(&reply->IOCStatus);
cpu_to_le32s(&reply->IOCLogInfo);
}