void cpu_timer_set (int32_t id, bigtime_t deadline)
{
bigtime_t local_deadline = 0;
soclib_timer_port_t timer = & PLATFORM_TIMER_BASE[id];
local_deadline = deadline / PLATFORM_TIMER_RES;
cpu_write(UINT32, & (timer -> period), (uint32_t)local_deadline);
cpu_write(UINT32, & (timer -> mode), 3);
}
void platform_debug_puts (char * string)
{
uint32_t res = 0;
for (int32_t i = 0; string[i] != '\0'; i += 1)
{
do cpu_read (UINT32, & (PLATFORM_DBGU_BASE -> SR), res);
while ((res & 0x202) != 0x202);
cpu_write (UINT32, & (PLATFORM_DBGU_BASE -> THR), string[i]);
}
}
blargg_err_t Sgc_Impl::start_track( int track )
{
memset( ram .begin(), 0, ram .size() );
memset( ram2.begin(), 0, ram2.size() );
memset( vectors.begin(), 0xFF, vectors.size() );
cpu.reset( unmapped_write.begin(), rom.unmapped() );
if ( sega_mapping() )
{
vectors_addr = 0x10000 - Sgc_Cpu::page_size;
idle_addr = vectors_addr;
for ( int i = 1; i < 8; ++i )
{
vectors [i*8 + 0] = 0xC3; // JP addr
vectors [i*8 + 1] = header_.rst_addrs [i*2 + 0];
vectors [i*8 + 2] = header_.rst_addrs [i*2 + 1];
}
cpu.map_mem( 0xC000, 0x2000, ram.begin() );
cpu.map_mem( vectors_addr, cpu.page_size, unmapped_write.begin(), vectors.begin() );
bank2 = NULL;
for ( int i = 0; i < 4; ++i )
cpu_write( 0xFFFC + i, header_.mapping [i] );
}
else
{
if ( !coleco_bios )
return BLARGG_ERR( BLARGG_ERR_CALLER, "Coleco BIOS not set" );
vectors_addr = 0;
cpu.map_mem( 0, 0x2000, unmapped_write.begin(), coleco_bios );
for ( int i = 0; i < 8; ++i )
cpu.map_mem( 0x6000 + i*0x400, 0x400, ram.begin() );
idle_addr = 0x2000;
cpu.map_mem( 0x2000, cpu.page_size, unmapped_write.begin(), vectors.begin() );
for ( int i = 0; i < 0x8000 / bank_size; ++i )
{
int addr = 0x8000 + i*bank_size;
cpu.map_mem( addr, bank_size, unmapped_write.begin(), rom.at_addr( addr ) );
}
}
cpu.r.sp = get_le16( header_.stack_ptr );
cpu.r.b.a = track;
next_play = play_period;
jsr( header_.init_addr );
return blargg_ok;
}
static INLINE void memwrite(u32 addr,u8 data)
{
//handle dpcm cycle stealing
if(nes->cpu.pcmcycles)
nes->cpu.pcmcycles--;
//increment cycle counter, check irq lines
cpu_tick();
//write data to its address
cpu_write(addr,data);
}
void Nsf_Impl::write_mem( addr_t addr, int data )
{
(void) LOG_MEM( addr, "<", data );
int offset = addr - sram_addr;
if ( (unsigned) offset < sram_size )
{
sram() [offset] = data;
}
else
{
// after sram because CPU handles most low_ram accesses internally already
int temp = addr & (low_ram_size-1); // also handles wrap-around
if ( !(addr & 0xE000) )
{
low_ram [temp] = data;
}
else
{
int bank = addr - banks_addr;
if ( (unsigned) bank < bank_count )
{
write_bank( bank, data );
}
else if ( (unsigned) (addr - apu.io_addr) < apu.io_size )
{
apu.write_register( time(), addr, data );
}
else
{
#if !NSF_EMU_APU_ONLY
// 0x8000-0xDFFF is writable
int i = addr - 0x8000;
if ( (unsigned) i < fdsram_size && fds_enabled() )
fdsram() [i] = data;
else
#endif
cpu_write( addr, data );
}
}
}
}
static inline cpu_syscall(Cpu *cpu, int *ret_val){
printf("syscall");
reg call_type = cpu->r[Tyr];
reg arg_1 = cpu->r[Glu];
reg arg_2 = cpu->r[Lys];
switch (call_type){
case sys_read:
cpu_read(cpu, arg_1, arg_2);
break;
case sys_write:
cpu_write(cpu, arg_1, arg_2);
break;
case sys_exit:
cpu_exit(cpu, ret_val);
break;
default:
p_errno = INV_SYSCALL;
break;
}
}
blargg_err_t Nsf_Emu::start_track_( int track )
{
RETURN_ERR( Classic_Emu::start_track_( track ) );
memset( low_mem, 0, sizeof low_mem );
memset( sram, 0, sizeof sram );
cpu::reset( unmapped_code ); // also maps low_mem
cpu::map_code( sram_addr, sizeof sram, sram );
for ( int i = 0; i < bank_count; ++i )
cpu_write( bank_select_addr + i, initial_banks [i] );
apu.reset( pal_only, (header_.speed_flags & 0x20) ? 0x3F : 0 );
apu.write_register( 0, 0x4015, 0x0F );
apu.write_register( 0, 0x4017, (header_.speed_flags & 0x10) ? 0x80 : 0 );
#if !NSF_EMU_APU_ONLY
{
if ( namco ) namco->reset();
if ( vrc6 ) vrc6 ->reset();
if ( fme7 ) fme7 ->reset();
}
#endif
play_ready = 4;
play_extra = 0;
next_play = play_period / clock_divisor;
saved_state.pc = badop_addr;
low_mem [0x1FF] = (badop_addr - 1) >> 8;
low_mem [0x1FE] = (badop_addr - 1) & 0xFF;
r.sp = 0xFD;
r.pc = init_addr;
r.a = track;
r.x = pal_only;
return 0;
}
void cpu_mp_send_ipi (int32_t target, int32_t command, void * data)
{
cpu_write (UINT32, & (PLATFORM_IPI_BASE[target] . data), ((uint32_t)data));
cpu_write (UINT32, & (PLATFORM_IPI_BASE[target] . command), command);
}
void SNES_SPC::WriteByte(unsigned int address, unsigned char value)
{
cpu_write(value, address);
}
status_t d940_ethernet_write (void * handler, void * source, int64_t offset,
int32_t * p_count) {
d940_eth_data_t * pdata = (d940_eth_data_t *) handler;
d940_eth_t d940_ethernet_device = pdata->dev;
d940_eth_ncr_t ncr;
d940_eth_tsr_t tsr;
int32_t buffer_index;
void * data = source;
int32_t buffer_size;
int32_t i;
int32_t frame_size = *p_count;
interrupt_status_t it_status;
if(frame_size < 0)
{
return DNA_BAD_ARGUMENT;
}
if(pdata->tx_write == 0)
{
pdata->tx_write = *((int32_t *) data);
return DNA_OK;
}
it_status = cpu_trap_mask_and_backup();
lock_acquire(&pdata->lock);
/* Check/Clear the status of the transmit */
cpu_read(UINT32, &(d940_ethernet_device->tsr.raw), tsr.raw);
cpu_write(UINT32, &(d940_ethernet_device->tsr.raw), tsr.raw);
lock_release(&pdata->lock);
cpu_trap_restore(it_status);
if(tsr.bits.und)
{
log(INFO_LEVEL, "Underrun: Clear the transmit buffer list");
it_status = cpu_trap_mask_and_backup();
lock_acquire(&pdata->lock);
/* Stop the transmit in case of underrun */
cpu_read(UINT32, &(d940_ethernet_device->ncr.raw), ncr.raw);
ncr.bits.te = 0;
cpu_write(UINT32, &(d940_ethernet_device->ncr.raw), ncr.raw);
ncr.bits.te = 1;
cpu_write(UINT32, &(d940_ethernet_device->ncr.raw), ncr.raw);
lock_release(&pdata->lock);
cpu_trap_restore(it_status);
/* ReInit the transmit */
pdata->tx_tail = 0;
/* ReInit the semaphore */
while(semaphore_acquire(pdata->tx_sem, 1, DNA_RELATIVE_TIMEOUT, 0)
== DNA_OK);
semaphore_release(pdata->tx_sem, TX_PACKET_LIMIT, 0);
/* Clear the buffers */
for(i = 0; i < D940_ETH_TX_BUFFER_COUNT; i++)
{
pdata->transmit_descs[i].used = 1;
}
}
buffer_index = pdata->tx_tail;
while(frame_size > 0)
{
cpu_cache_invalidate(CPU_CACHE_DATA, &pdata->transmit_descs[buffer_index],
sizeof(struct tbde));
buffer_size = D940_ETH_TX_BUFFER_SIZE;
if(buffer_size > frame_size)
{
buffer_size = frame_size;
}
/* Copy in the transmit buffer */
dna_memcpy(&pdata->transmit_buffers[buffer_index * D940_ETH_TX_BUFFER_SIZE],
data, buffer_size);
data += buffer_size;
frame_size -= buffer_size;
pdata->tx_write -= buffer_size;
/* Set the transmit buffer as ready to send */
pdata->transmit_descs[buffer_index].len = buffer_size;
pdata->transmit_descs[buffer_index].used = 0;
/* Last chunk ? */
if(pdata->tx_write != 0)
{
pdata->transmit_descs[buffer_index].last = 0;
}
else
{
pdata->transmit_descs[buffer_index].last = 1;
}
buffer_index = NEXT_TX_BUFFER(buffer_index);
}
/* Next Packet invalid */
pdata->transmit_descs[buffer_index].used = 1;
pdata->tx_tail = buffer_index;
if(pdata->tx_write == 0)
{
/* Force to flush the cache */
cpu_cache_sync();
it_status = cpu_trap_mask_and_backup();
lock_acquire(&pdata->lock);
/* Restart the transmission */
cpu_read(UINT32, &(d940_ethernet_device->ncr.raw), ncr.raw);
ncr.bits.tstart = 1;
cpu_write(UINT32, &(d940_ethernet_device->ncr.raw), ncr.raw);
lock_release(&pdata->lock);
cpu_trap_restore(it_status);
semaphore_acquire(pdata->tx_sem, 1, 0, 0);
}
return DNA_OK;
}
status_t d940_ethernet_open (char * name, int32_t mode, void ** data)
{
d940_eth_t d940_ethernet_device;
d940_eth_data_t * pdata;
d940_eth_int_t interrupt;
d940_eth_ncr_t ncr;
d940_eth_ncfgr_t ncfgr;
d940_eth_usrio_t usrio;
interrupt_status_t it_status;
uint32_t i;
if(data == NULL) return DNA_ERROR;
/* /!\ Only for one device /!\ */
if(dna_strcmp (name, d940_ethernet_devices[0]) != 0) return DNA_ERROR;
pdata = d940_ethernet_handlers[0];
/* Exclusive access */
it_status = cpu_trap_mask_and_backup();
lock_acquire(&pdata->lock);
if(pdata->ref != 0)
{
lock_release(&pdata->lock);
cpu_trap_restore(it_status);
return DNA_ERROR;
}
pdata->ref += 1;
lock_release(&pdata->lock);
cpu_trap_restore(it_status);
/* Set device access */
d940_ethernet_device = pdata->dev;
*data = pdata;
/* Init all the semaphore */
while(semaphore_acquire(pdata->mio_sem, 1, DNA_RELATIVE_TIMEOUT, 0)
== DNA_OK);
while(semaphore_acquire(pdata->mio_comp_sem, 1, DNA_RELATIVE_TIMEOUT, 0)
== DNA_OK);
while(semaphore_acquire(pdata->tx_sem, 1, DNA_RELATIVE_TIMEOUT, 0)
== DNA_OK);
while(semaphore_acquire(pdata->rx_sem, 1, DNA_RELATIVE_TIMEOUT, 0)
== DNA_OK);
/* Set the limit of packet in the transmit buffers */
semaphore_release(pdata->mio_sem, 1, 0);
semaphore_release(pdata->tx_sem, TX_PACKET_LIMIT, 0);
/* Initialisation of transmit buffer descriptor */
for(i = 0; i < D940_ETH_TX_BUFFER_COUNT; i++)
{
pdata->transmit_descs[i].addr =
((uint32_t)(& pdata->transmit_buffers[i * D940_ETH_TX_BUFFER_SIZE]));
pdata->transmit_descs[i].used = 1;
pdata->transmit_descs[i].wrap = 0;
pdata->transmit_descs[i].no_crc = 0;
}
pdata->transmit_descs[i-1].wrap = 1;
/* Initialisation of receive buffer descriptor */
for(i = 0; i < D940_ETH_RX_BUFFER_COUNT; i++)
{
pdata->receive_descs[i].addr =
((uint32_t)(& pdata->receive_buffers[i * D940_ETH_RX_BUFFER_SIZE])) >> 2;
pdata->receive_descs[i].owner = 0;
pdata->receive_descs[i].wrap = 0;
}
pdata->receive_descs[i-1].wrap = 1;
/* Initialisation of the tails */
pdata->tx_tail = 0;
pdata->rx_tail = 0;
pdata->rx_read = false;
pdata->tx_write = 0;
/* Initialisation of the stats */
pdata->tx_count = 0;
pdata->rx_count = 0;
/* Configure the PHY */
pdata->phy_status = 0;
d940_ethernet_phy_probe(pdata);
d940_ethernet_phy_manage(pdata);
it_status = cpu_trap_mask_and_backup();
lock_acquire(&pdata->lock);
/* Configure the device (depends of PHY) */
cpu_read(UINT32, &(d940_ethernet_device->ncfgr.raw), ncfgr.raw);
ncfgr.bits.rbof = 0;
ncfgr.bits.drfcs = 1;
ncfgr.bits.pae = 1;
cpu_write(UINT32, &(d940_ethernet_device->ncfgr.raw), ncfgr.raw);
/* Configure MII */
cpu_read(UINT32, &(d940_ethernet_device->usrio.raw), usrio.raw);
usrio.bits.clken = 0;
usrio.bits.rmii = 0;
cpu_write(UINT32, &(d940_ethernet_device->usrio.raw), usrio.raw);
/* Enable Interrupt (NO TXUBR & NO MFD) */
interrupt.raw = 0x00003cf6;
cpu_write(UINT32, &(d940_ethernet_device->ier.raw), interrupt.raw);
/* Start Receive/Transmit */
cpu_read(UINT32, &(d940_ethernet_device->ncr.raw), ncr.raw);
ncr.bits.re = 1;
ncr.bits.te = 1;
ncr.bits.clrstat = 1;
cpu_write(UINT32, &(d940_ethernet_device->ncr.raw), ncr.raw);
lock_release(&pdata->lock);
cpu_trap_restore(it_status);
return DNA_OK;
}
