void
csa_clearserialfifos(csa_res *resp)
{
int i, j, pwr;
u_int8_t clkcr1, serbst;
/*
* See if the devices are powered down. If so, we must power them up first
* or they will not respond.
*/
pwr = 1;
clkcr1 = csa_readio(resp, BA0_CLKCR1);
if ((clkcr1 & CLKCR1_SWCE) == 0) {
csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE);
pwr = 0;
}
/*
* We want to clear out the serial port FIFOs so we don't end up playing
* whatever random garbage happens to be in them. We fill the sample FIFOs
* with zero (silence).
*/
csa_writeio(resp, BA0_SERBWP, 0);
/* Fill all 256 sample FIFO locations. */
serbst = 0;
for (i = 0 ; i < 256 ; i++) {
/* Make sure the previous FIFO write operation has completed. */
for (j = 0 ; j < 5 ; j++) {
DELAY(100);
serbst = csa_readio(resp, BA0_SERBST);
if ((serbst & SERBST_WBSY) == 0)
break;
}
if ((serbst & SERBST_WBSY) != 0) {
if (!pwr)
csa_writeio(resp, BA0_CLKCR1, clkcr1);
}
/* Write the serial port FIFO index. */
csa_writeio(resp, BA0_SERBAD, i);
/* Tell the serial port to load the new value into the FIFO location. */
csa_writeio(resp, BA0_SERBCM, SERBCM_WRC);
}
/*
* Now, if we powered up the devices, then power them back down again.
* This is kinda ugly, but should never happen.
*/
if (!pwr)
csa_writeio(resp, BA0_CLKCR1, clkcr1);
}
int
csa_writecodec(csa_res *resp, u_long offset, u_int32_t data)
{
int i;
u_int32_t acctl;
/*
* Setup the AC97 control registers on the CS461x to send the
* appropriate command to the AC97 to perform the write.
* ACCAD = Command Address Register = 46Ch
* ACCDA = Command Data Register = 470h
* ACCTL = Control Register = 460h
* set DCV - will clear when process completed
* set VFRM - valid frame enabled
* set ESYN - ASYNC generation enabled
* set RSTN - ARST# inactive, AC97 codec not reset
*/
/*
* Get the actual AC97 register from the offset
*/
csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
csa_writeio(resp, BA0_ACCDA, data);
csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
/*
* Wait for the write to occur.
*/
acctl = 0;
for (i = 0 ; i < 10 ; i++) {
/*
* First, we want to wait for a short time.
*/
DELAY(25);
/*
* Now, check to see if the read has completed.
* ACCTL = 460h, DCV should be reset by now and 460h = 17h
*/
acctl = csa_readio(resp, BA0_ACCTL);
if ((acctl & ACCTL_DCV) == 0)
break;
}
/*
* Make sure the write completed.
*/
if ((acctl & ACCTL_DCV) != 0)
return (EAGAIN);
return (0);
}
static int
csa_setup_intr(device_t bus, device_t child,
struct resource *irq, int flags,
#if __FreeBSD_version >= 700031
driver_filter_t *filter,
#endif
driver_intr_t *intr, void *arg, void **cookiep)
{
sc_p scp;
csa_res *resp;
struct sndcard_func *func;
#if __FreeBSD_version >= 700031
if (filter != NULL) {
printf("ata-csa.c: we cannot use a filter here\n");
return (EINVAL);
}
#endif
scp = device_get_softc(bus);
resp = &scp->res;
/*
* Look at the function code of the child to determine
* the appropriate hander for it.
*/
func = device_get_ivars(child);
if (func == NULL || irq != resp->irq)
return (EINVAL);
switch (func->func) {
case SCF_PCM:
scp->pcmintr = intr;
scp->pcmintr_arg = arg;
break;
case SCF_MIDI:
scp->midiintr = intr;
scp->midiintr_arg = arg;
break;
default:
return (EINVAL);
}
*cookiep = scp;
if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
return (0);
}
/* The interrupt handler */
static void
csa_intr(void *arg)
{
sc_p scp = arg;
csa_res *resp;
u_int32_t hisr;
resp = &scp->res;
/* Is this interrupt for us? */
hisr = csa_readio(resp, BA0_HISR);
if ((hisr & 0x7fffffff) == 0) {
/* Throw an eoi. */
csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
return;
}
/*
* Pass the value of HISR via struct csa_bridgeinfo.
* The children get access through their ivars.
*/
scp->binfo.hisr = hisr;
/* Invoke the handlers of the children. */
if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) {
scp->pcmintr(scp->pcmintr_arg);
hisr &= ~(HISR_VC0 | HISR_VC1);
}
if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) {
scp->midiintr(scp->midiintr_arg);
hisr &= ~HISR_MIDI;
}
/* Throw an eoi. */
csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
}
int
csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data)
{
int i;
u_int32_t acsda, acctl, acsts;
/*
* Make sure that there is not data sitting around from a previous
* uncompleted access. ACSDA = Status Data Register = 47Ch
*/
acsda = csa_readio(resp, BA0_ACSDA);
/*
* Setup the AC97 control registers on the CS461x to send the
* appropriate command to the AC97 to perform the read.
* ACCAD = Command Address Register = 46Ch
* ACCDA = Command Data Register = 470h
* ACCTL = Control Register = 460h
* set DCV - will clear when process completed
* set CRW - Read command
* set VFRM - valid frame enabled
* set ESYN - ASYNC generation enabled
* set RSTN - ARST# inactive, AC97 codec not reset
*/
/*
* Get the actual AC97 register from the offset
*/
csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
csa_writeio(resp, BA0_ACCDA, 0);
csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
/*
* Wait for the read to occur.
*/
acctl = 0;
for (i = 0 ; i < 10 ; i++) {
/*
* First, we want to wait for a short time.
*/
DELAY(25);
/*
* Now, check to see if the read has completed.
* ACCTL = 460h, DCV should be reset by now and 460h = 17h
*/
acctl = csa_readio(resp, BA0_ACCTL);
if ((acctl & ACCTL_DCV) == 0)
break;
}
/*
* Make sure the read completed.
*/
if ((acctl & ACCTL_DCV) != 0)
return (EAGAIN);
/*
* Wait for the valid status bit to go active.
*/
acsts = 0;
for (i = 0 ; i < 10 ; i++) {
/*
* Read the AC97 status register.
* ACSTS = Status Register = 464h
*/
acsts = csa_readio(resp, BA0_ACSTS);
/*
* See if we have valid status.
* VSTS - Valid Status
*/
if ((acsts & ACSTS_VSTS) != 0)
break;
/*
* Wait for a short while.
*/
DELAY(25);
}
/*
* Make sure we got valid status.
*/
if ((acsts & ACSTS_VSTS) == 0)
return (EAGAIN);
/*
* Read the data returned from the AC97 register.
* ACSDA = Status Data Register = 474h
*/
*data = csa_readio(resp, BA0_ACSDA);
return (0);
}
static int
csa_initialize(sc_p scp)
{
int i;
u_int32_t acsts, acisv;
csa_res *resp;
resp = &scp->res;
/*
* First, blast the clock control register to zero so that the PLL starts
* out in a known state, and blast the master serial port control register
* to zero so that the serial ports also start out in a known state.
*/
csa_writeio(resp, BA0_CLKCR1, 0);
csa_writeio(resp, BA0_SERMC1, 0);
/*
* If we are in AC97 mode, then we must set the part to a host controlled
* AC-link. Otherwise, we won't be able to bring up the link.
*/
#if 1
csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */
#else
csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */
#endif /* 1 */
/*
* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
* spec) and then drive it high. This is done for non AC97 modes since
* there might be logic external to the CS461x that uses the ARST# line
* for a reset.
*/
csa_writeio(resp, BA0_ACCTL, 1);
DELAY(50);
csa_writeio(resp, BA0_ACCTL, 0);
DELAY(50);
csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN);
/*
* The first thing we do here is to enable sync generation. As soon
* as we start receiving bit clock, we'll start producing the SYNC
* signal.
*/
csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
/*
* Now wait for a short while to allow the AC97 part to start
* generating bit clock (so we don't try to start the PLL without an
* input clock).
*/
DELAY(50000);
/*
* Set the serial port timing configuration, so that
* the clock control circuit gets its clock from the correct place.
*/
csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97);
DELAY(700000);
/*
* Write the selected clock control setup to the hardware. Do not turn on
* SWCE yet (if requested), so that the devices clocked by the output of
* PLL are not clocked until the PLL is stable.
*/
csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
csa_writeio(resp, BA0_PLLM, 0x3a);
csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8);
/*
* Power up the PLL.
*/
csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP);
/*
* Wait until the PLL has stabilized.
*/
DELAY(5000);
/*
* Turn on clocking of the core so that we can setup the serial ports.
*/
csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE);
/*
* Fill the serial port FIFOs with silence.
*/
csa_clearserialfifos(resp);
/*
* Set the serial port FIFO pointer to the first sample in the FIFO.
*/
#ifdef notdef
csa_writeio(resp, BA0_SERBSP, 0);
#endif /* notdef */
/*
* Write the serial port configuration to the part. The master
* enable bit is not set until all other values have been written.
*/
csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
/*
* Wait for the codec ready signal from the AC97 codec.
*/
acsts = 0;
for (i = 0 ; i < 1000 ; i++) {
/*
* First, lets wait a short while to let things settle out a bit,
* and to prevent retrying the read too quickly.
*/
DELAY(125);
/*
* Read the AC97 status register to see if we've seen a CODEC READY
* signal from the AC97 codec.
*/
acsts = csa_readio(resp, BA0_ACSTS);
if ((acsts & ACSTS_CRDY) != 0)
break;
}
/*
* Make sure we sampled CODEC READY.
*/
if ((acsts & ACSTS_CRDY) == 0)
return (ENXIO);
/*
* Assert the vaid frame signal so that we can start sending commands
* to the AC97 codec.
*/
csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
/*
* Wait until we've sampled input slots 3 and 4 as valid, meaning that
* the codec is pumping ADC data across the AC-link.
*/
acisv = 0;
for (i = 0 ; i < 1000 ; i++) {
/*
* First, lets wait a short while to let things settle out a bit,
* and to prevent retrying the read too quickly.
*/
#ifdef notdef
DELAY(10000000L); /* clw */
#else
DELAY(1000);
#endif /* notdef */
/*
* Read the input slot valid register and see if input slots 3 and
* 4 are valid yet.
*/
acisv = csa_readio(resp, BA0_ACISV);
if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
break;
}
/*
* Make sure we sampled valid input slots 3 and 4. If not, then return
* an error.
*/
if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4))
return (ENXIO);
/*
* Now, assert valid frame and the slot 3 and 4 valid bits. This will
* commense the transfer of digital audio data to the AC97 codec.
*/
csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
/*
* Power down the DAC and ADC. We will power them up (if) when we need
* them.
*/
#ifdef notdef
csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300);
#endif /* notdef */
/*
* Turn off the Processor by turning off the software clock enable flag in
* the clock control register.
*/
#ifdef notdef
clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE;
csa_writeio(resp, BA0_CLKCR1, clkcr1);
#endif /* notdef */
/*
* Enable interrupts on the part.
*/
#if 0
csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
#endif /* notdef */
return (0);
}
static int
csa_attach(device_t dev)
{
u_int32_t stcmd;
sc_p scp;
csa_res *resp;
struct sndcard_func *func;
int error = ENXIO;
scp = device_get_softc(dev);
/* Fill in the softc. */
bzero(scp, sizeof(*scp));
scp->dev = dev;
/* Wake up the device. */
stcmd = pci_read_config(dev, PCIR_COMMAND, 2);
if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) {
stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, stcmd, 2);
}
/* Allocate the resources. */
resp = &scp->res;
scp->card = csa_findsubcard(dev);
scp->binfo.card = scp->card;
kprintf("csa: card is %s\n", scp->card->name);
resp->io_rid = PCIR_BAR(0);
resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&resp->io_rid, RF_ACTIVE);
if (resp->io == NULL)
return (ENXIO);
resp->mem_rid = PCIR_BAR(1);
resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&resp->mem_rid, RF_ACTIVE);
if (resp->mem == NULL)
goto err_io;
resp->irq_rid = 0;
resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&resp->irq_rid, RF_ACTIVE | RF_SHAREABLE);
if (resp->irq == NULL)
goto err_mem;
/* Enable interrupt. */
if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih))
goto err_intr;
#if 0
if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
#endif
/* Initialize the chip. */
if (csa_initialize(scp))
goto err_teardown;
/* Reset the Processor. */
csa_resetdsp(resp);
/* Download the Processor Image to the processor. */
if (csa_downloadimage(resp))
goto err_teardown;
/* Attach the children. */
/* PCM Audio */
func = kmalloc(sizeof(struct sndcard_func), M_DEVBUF,
M_WAITOK | M_ZERO);
func->varinfo = &scp->binfo;
func->func = SCF_PCM;
scp->pcm = device_add_child(dev, "pcm", -1);
device_set_ivars(scp->pcm, func);
/* Midi Interface */
func = kmalloc(sizeof(struct sndcard_func), M_DEVBUF,
M_WAITOK | M_ZERO);
func->varinfo = &scp->binfo;
func->func = SCF_MIDI;
scp->midi = device_add_child(dev, "midi", -1);
device_set_ivars(scp->midi, func);
bus_generic_attach(dev);
return (0);
err_teardown:
bus_teardown_intr(dev, resp->irq, scp->ih);
err_intr:
bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
err_mem:
bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
err_io:
bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
return (error);
}
