int cvm_oct_sgmii_init(struct net_device *dev)
{
// struct octeon_ethernet *priv = netdev_priv(dev);
cvm_oct_common_init(dev);
dev->netdev_ops->ndo_stop(dev);
return 0;
}
int cvm_oct_sgmii_init(struct net_device *dev)
{
cvm_oct_common_init(dev);
/* FIXME: Need autoneg logic */
return 0;
}
int cvm_oct_sgmii_init(struct net_device *dev)
{
struct octeon_ethernet *priv = netdev_priv(dev);
cvm_oct_common_init(dev);
dev->netdev_ops->ndo_stop(dev);
if (!octeon_is_simulation() && priv->phydev == NULL)
priv->poll = cvm_oct_sgmii_poll;
return 0;
}
int cvm_oct_rgmii_init(struct net_device *dev)
{
struct octeon_ethernet *priv = netdev_priv(dev);
int r;
cvm_oct_common_init(dev);
dev->netdev_ops->ndo_stop(dev);
INIT_WORK(&priv->port_work, cvm_oct_rgmii_immediate_poll);
/*
* Due to GMX errata in CN3XXX series chips, it is necessary
* to take the link down immediately when the PHY changes
* state. In order to do this we call the poll function every
* time the RGMII inband status changes. This may cause
* problems if the PHY doesn't implement inband status
* properly.
*/
if (number_rgmii_ports == 0) {
r = request_irq(OCTEON_IRQ_RML, cvm_oct_rgmii_rml_interrupt,
IRQF_SHARED, "RGMII", &number_rgmii_ports);
if (r != 0)
return r;
}
number_rgmii_ports++;
/*
* Only true RGMII ports need to be polled. In GMII mode, port
* 0 is really a RGMII port.
*/
if (((priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII)
&& (priv->port == 0))
|| (priv->imode == CVMX_HELPER_INTERFACE_MODE_RGMII)) {
if (!octeon_is_simulation()) {
union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
int interface = INTERFACE(priv->port);
int index = INDEX(priv->port);
/*
* Enable interrupts on inband status changes
* for this port.
*/
gmx_rx_int_en.u64 =
cvmx_read_csr(CVMX_GMXX_RXX_INT_EN
(index, interface));
gmx_rx_int_en.s.phy_dupx = 1;
gmx_rx_int_en.s.phy_link = 1;
gmx_rx_int_en.s.phy_spd = 1;
cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, interface),
gmx_rx_int_en.u64);
priv->poll = cvm_oct_rgmii_poll;
}
}
return 0;
}
int cvm_oct_xaui_init(struct ifnet *ifp)
{
cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
cvm_oct_common_init(ifp);
priv->open = cvm_oct_common_open;
priv->stop = cvm_oct_common_stop;
priv->stop(ifp);
return 0;
}
int cvm_oct_sgmii_init(struct net_device *dev)
{
struct octeon_ethernet *priv = netdev_priv(dev);
cvm_oct_common_init(dev);
dev->netdev_ops->ndo_stop(dev);
priv->link_change = cvm_oct_sgmii_link_change;
return 0;
}
int cvm_oct_sgmii_init(struct ifnet *ifp)
{
cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
cvm_oct_common_init(ifp);
priv->open = cvm_oct_common_open;
priv->stop = cvm_oct_common_stop;
priv->stop(ifp);
/* FIXME: Need autoneg logic */
return 0;
}
int cvm_oct_sgmii_init(struct net_device *dev)
{
struct octeon_ethernet *priv = netdev_priv(dev);
cvm_oct_common_init(dev);
dev->netdev_ops->ndo_stop(dev);
if (!octeon_is_simulation())
priv->poll = cvm_oct_sgmii_poll;
/* FIXME: Need autoneg logic */
return 0;
}
int cvm_oct_spi_init(struct net_device *dev)
{
int r;
struct octeon_ethernet *priv = netdev_priv(dev);
if (number_spi_ports == 0) {
r = request_irq(OCTEON_IRQ_RML, cvm_oct_spi_rml_interrupt,
IRQF_SHARED, "SPI", &number_spi_ports);
}
number_spi_ports++;
if ((priv->port == 0) || (priv->port == 16)) {
cvm_oct_spi_enable_error_reporting(INTERFACE(priv->port));
priv->poll = cvm_oct_spi_poll;
}
cvm_oct_common_init(dev);
return 0;
}
int cvm_oct_rgmii_init(struct net_device *dev)
{
struct octeon_ethernet *priv = netdev_priv(dev);
int r;
cvm_oct_common_init(dev);
dev->netdev_ops->ndo_stop(dev);
if (number_rgmii_ports == 0) {
r = request_irq(OCTEON_IRQ_RML, cvm_oct_rgmii_rml_interrupt,
IRQF_SHARED, "RGMII", &number_rgmii_ports);
}
number_rgmii_ports++;
if (((priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII)
&& (priv->port == 0))
|| (priv->imode == CVMX_HELPER_INTERFACE_MODE_RGMII)) {
if (!octeon_is_simulation()) {
union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
int interface = INTERFACE(priv->port);
int index = INDEX(priv->port);
gmx_rx_int_en.u64 =
cvmx_read_csr(CVMX_GMXX_RXX_INT_EN
(index, interface));
gmx_rx_int_en.s.phy_dupx = 1;
gmx_rx_int_en.s.phy_link = 1;
gmx_rx_int_en.s.phy_spd = 1;
cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, interface),
gmx_rx_int_en.u64);
priv->poll = cvm_oct_rgmii_poll;
}
}
return 0;
}
int cvm_oct_spi_init(struct ifnet *ifp)
{
struct octebus_softc *sc;
cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
int error;
int rid;
if (number_spi_ports == 0) {
sc = device_get_softc(device_get_parent(priv->dev));
rid = 0;
sc->sc_spi_irq = bus_alloc_resource(sc->sc_dev, SYS_RES_IRQ,
&rid, OCTEON_IRQ_RML,
OCTEON_IRQ_RML, 1,
RF_ACTIVE);
if (sc->sc_spi_irq == NULL) {
device_printf(sc->sc_dev, "could not allocate SPI irq");
return ENXIO;
}
error = bus_setup_intr(sc->sc_dev, sc->sc_spi_irq,
INTR_TYPE_NET | INTR_MPSAFE,
cvm_oct_spi_rml_interrupt, NULL,
&number_spi_ports, NULL);
if (error != 0) {
device_printf(sc->sc_dev, "could not setup SPI irq");
return error;
}
}
number_spi_ports++;
if ((priv->port == 0) || (priv->port == 16)) {
cvm_oct_spi_enable_error_reporting(INTERFACE(priv->port));
priv->poll = cvm_oct_spi_poll;
}
if (cvm_oct_common_init(ifp) != 0)
return ENXIO;
return 0;
}
int cvm_oct_rgmii_init(struct ifnet *ifp)
{
struct octebus_softc *sc;
cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
int error;
int rid;
if (cvm_oct_common_init(ifp) != 0)
return ENXIO;
priv->open = cvm_oct_common_open;
priv->stop = cvm_oct_common_stop;
priv->stop(ifp);
/* Due to GMX errata in CN3XXX series chips, it is necessary to take the
link down immediately whne the PHY changes state. In order to do this
we call the poll function every time the RGMII inband status changes.
This may cause problems if the PHY doesn't implement inband status
properly */
if (number_rgmii_ports == 0) {
sc = device_get_softc(device_get_parent(priv->dev));
rid = 0;
sc->sc_rgmii_irq = bus_alloc_resource(sc->sc_dev, SYS_RES_IRQ,
&rid, OCTEON_IRQ_RML,
OCTEON_IRQ_RML, 1,
RF_ACTIVE);
if (sc->sc_rgmii_irq == NULL) {
device_printf(sc->sc_dev, "could not allocate RGMII irq");
return ENXIO;
}
error = bus_setup_intr(sc->sc_dev, sc->sc_rgmii_irq,
INTR_TYPE_NET | INTR_MPSAFE,
cvm_oct_rgmii_rml_interrupt, NULL,
&number_rgmii_ports, NULL);
if (error != 0) {
device_printf(sc->sc_dev, "could not setup RGMII irq");
return error;
}
}
number_rgmii_ports++;
/* Only true RGMII ports need to be polled. In GMII mode, port 0 is really
a RGMII port */
if (((priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII) && (priv->port == 0)) ||
(priv->imode == CVMX_HELPER_INTERFACE_MODE_RGMII)) {
if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) {
cvmx_gmxx_rxx_int_en_t gmx_rx_int_en;
int interface = INTERFACE(priv->port);
int index = INDEX(priv->port);
/* Enable interrupts on inband status changes for this port */
gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(index, interface));
gmx_rx_int_en.s.phy_dupx = 1;
gmx_rx_int_en.s.phy_link = 1;
gmx_rx_int_en.s.phy_spd = 1;
cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, interface), gmx_rx_int_en.u64);
priv->poll = cvm_oct_rgmii_poll;
}
}
return 0;
}
