static void cvm_oct_sgmii_poll(struct net_device *dev)
{
struct octeon_ethernet *priv = netdev_priv(dev);
cvmx_helper_link_info_t link_info;
link_info = cvmx_helper_link_get(priv->port);
if (link_info.u64 == priv->link_info)
return;
link_info = cvmx_helper_link_autoconf(priv->port);
priv->link_info = link_info.u64;
/* Tell Linux */
if (link_info.s.link_up) {
if (!netif_carrier_ok(dev))
netif_carrier_on(dev);
if (priv->queue != -1)
printk_ratelimited
("%s: %u Mbps %s duplex, port %2d, queue %2d\n",
dev->name, link_info.s.speed,
(link_info.s.full_duplex) ? "Full" : "Half",
priv->port, priv->queue);
else
printk_ratelimited
("%s: %u Mbps %s duplex, port %2d, POW\n",
dev->name, link_info.s.speed,
(link_info.s.full_duplex) ? "Full" : "Half",
priv->port);
} else {
if (netif_carrier_ok(dev))
netif_carrier_off(dev);
printk_ratelimited("%s: Link down\n", dev->name);
}
}
static void cvm_oct_sgmii_poll(struct net_device *dev)
{
struct octeon_ethernet *priv = netdev_priv(dev);
cvmx_helper_link_info_t link_info;
link_info = cvmx_helper_link_get(priv->ipd_port);
if (link_info.u64 == priv->link_info)
return;
link_info = cvmx_helper_link_autoconf(priv->ipd_port);
priv->link_info = link_info.u64;
/* Tell the core */
cvm_oct_set_carrier(priv, link_info);
}
static int cvm_oct_sgmii_hw_status(struct notifier_block *nb,
unsigned long val, void *v)
{
struct octeon_ethernet *priv = container_of(nb, struct octeon_ethernet,
hw_status_notifier);
if (val == OCTEON_HW_STATUS_SOURCE_ASSERTED) {
struct octeon_hw_status_data *d = v;
if (d->reg == CVMX_GMXX_RXX_INT_REG(priv->interface_port,
priv->interface) &&
(d->bit == INT_BIT_LOC_FAULT ||
d->bit == INT_BIT_REM_FAULT)) {
cvmx_helper_link_autoconf(priv->ipd_port);
return NOTIFY_STOP;
}
}
return NOTIFY_DONE;
}
void cvm_oct_link_poll(struct net_device *dev)
{
struct octeon_ethernet *priv = netdev_priv(dev);
cvmx_helper_link_info_t link_info;
link_info = cvmx_helper_link_get(priv->port);
if (link_info.u64 == priv->link_info)
return;
link_info = cvmx_helper_link_autoconf(priv->port);
priv->link_info = link_info.u64;
if (link_info.s.link_up) {
if (!netif_carrier_ok(dev))
netif_carrier_on(dev);
} else if (netif_carrier_ok(dev)) {
netif_carrier_off(dev);
}
cvm_oct_note_carrier(priv, link_info);
}
/**
* Poll for link status change.
*/
void cvm_oct_common_poll(struct ifnet *ifp)
{
cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
cvmx_helper_link_info_t link_info;
/*
* If this is a simulation, do nothing.
*/
if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
return;
/*
* If there is a device-specific poll method, use it.
*/
if (priv->poll != NULL) {
priv->poll(ifp);
return;
}
/*
* If an MII bus is attached, don't use the Simple Executive's link
* state routines.
*/
if (priv->miibus != NULL)
return;
/*
* Use the Simple Executive's link state routines.
*/
link_info = cvmx_helper_link_get(priv->port);
if (link_info.u64 == priv->link_info)
return;
link_info = cvmx_helper_link_autoconf(priv->port);
priv->link_info = link_info.u64;
priv->need_link_update = 1;
}
static void cvm_oct_rgmii_poll(struct net_device *dev)
{
struct octeon_ethernet *priv = netdev_priv(dev);
cvmx_helper_link_info_t link_info;
link_info = cvmx_helper_link_get(priv->port);
if (link_info.u64 == priv->link_info) {
/*
* If the 10Mbps preamble workaround is supported and we're
* at 10Mbps we may need to do some special checking.
*/
if (USE_10MBPS_PREAMBLE_WORKAROUND && (link_info.s.speed == 10)) {
/*
* Read the GMXX_RXX_INT_REG[PCTERR] bit and
* see if we are getting preamble errors.
*/
int interface = INTERFACE(priv->port);
int index = INDEX(priv->port);
union cvmx_gmxx_rxx_int_reg gmxx_rxx_int_reg;
gmxx_rxx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, interface));
if (gmxx_rxx_int_reg.s.pcterr) {
/*
* We are getting preamble errors at
* 10Mbps. Most likely the PHY is
* giving us packets with mis aligned
* preambles. In order to get these
* packets we need to disable preamble
* checking and do it in software.
*/
union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl;
union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs;
/* Disable preamble checking */
gmxx_rxx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));
gmxx_rxx_frm_ctl.s.pre_chk = 0;
cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface), gmxx_rxx_frm_ctl.u64);
/* Disable FCS stripping */
ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
ipd_sub_port_fcs.s.port_bit &= 0xffffffffull ^ (1ull << priv->port);
cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
/* Clear any error bits */
cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface), gmxx_rxx_int_reg.u64);
DEBUGPRINT("%s: Using 10Mbps with software preamble removal\n",
dev->name);
}
}
return;
}
/* If the 10Mbps preamble workaround is allowed we need to on
preamble checking, FCS stripping, and clear error bits on
every speed change. If errors occur during 10Mbps operation
the above code will change this stuff */
if (USE_10MBPS_PREAMBLE_WORKAROUND) {
union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl;
union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs;
union cvmx_gmxx_rxx_int_reg gmxx_rxx_int_reg;
int interface = INTERFACE(priv->port);
int index = INDEX(priv->port);
/* Enable preamble checking */
gmxx_rxx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));
gmxx_rxx_frm_ctl.s.pre_chk = 1;
cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface), gmxx_rxx_frm_ctl.u64);
/* Enable FCS stripping */
ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
ipd_sub_port_fcs.s.port_bit |= 1ull << priv->port;
cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
/* Clear any error bits */
gmxx_rxx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, interface));
cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface), gmxx_rxx_int_reg.u64);
}
if (priv->phydev == NULL) {
link_info = cvmx_helper_link_autoconf(priv->port);
priv->link_info = link_info.u64;
}
if (priv->phydev == NULL)
cvm_oct_set_carrier(priv, link_info);
}
static void cvm_oct_rgmii_poll(struct net_device *dev)
{
struct octeon_ethernet *priv = netdev_priv(dev);
unsigned long flags = 0;
cvmx_helper_link_info_t link_info;
int use_global_register_lock = (priv->phydev == NULL);
BUG_ON(in_interrupt());
if (use_global_register_lock) {
/*
* Take the global register lock since we are going to
* touch registers that affect more than one port.
*/
spin_lock_irqsave(&global_register_lock, flags);
} else {
mutex_lock(&priv->phydev->bus->mdio_lock);
}
link_info = cvmx_helper_link_get(priv->port);
if (link_info.u64 == priv->link_info) {
/*
* If the 10Mbps preamble workaround is supported and we're
* at 10Mbps we may need to do some special checking.
*/
if (USE_10MBPS_PREAMBLE_WORKAROUND && (link_info.s.speed == 10)) {
/*
* Read the GMXX_RXX_INT_REG[PCTERR] bit and
* see if we are getting preamble errors.
*/
int interface = INTERFACE(priv->port);
int index = INDEX(priv->port);
union cvmx_gmxx_rxx_int_reg gmxx_rxx_int_reg;
gmxx_rxx_int_reg.u64 =
cvmx_read_csr(CVMX_GMXX_RXX_INT_REG
(index, interface));
if (gmxx_rxx_int_reg.s.pcterr) {
/*
* We are getting preamble errors at
* 10Mbps. Most likely the PHY is
* giving us packets with mis aligned
* preambles. In order to get these
* packets we need to disable preamble
* checking and do it in software.
*/
union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl;
union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs;
/* Disable preamble checking */
gmxx_rxx_frm_ctl.u64 =
cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL
(index, interface));
gmxx_rxx_frm_ctl.s.pre_chk = 0;
cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL
(index, interface),
gmxx_rxx_frm_ctl.u64);
/* Disable FCS stripping */
ipd_sub_port_fcs.u64 =
cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
ipd_sub_port_fcs.s.port_bit &=
0xffffffffull ^ (1ull << priv->port);
cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS,
ipd_sub_port_fcs.u64);
/* Clear any error bits */
cvmx_write_csr(CVMX_GMXX_RXX_INT_REG
(index, interface),
gmxx_rxx_int_reg.u64);
printk_ratelimited("%s: Using 10Mbps with software "
"preamble removal\n",
dev->name);
}
}
if (use_global_register_lock)
spin_unlock_irqrestore(&global_register_lock, flags);
else
mutex_unlock(&priv->phydev->bus->mdio_lock);
return;
}
/* If the 10Mbps preamble workaround is allowed we need to on
preamble checking, FCS stripping, and clear error bits on
every speed change. If errors occur during 10Mbps operation
the above code will change this stuff */
if (USE_10MBPS_PREAMBLE_WORKAROUND) {
union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl;
union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs;
union cvmx_gmxx_rxx_int_reg gmxx_rxx_int_reg;
int interface = INTERFACE(priv->port);
int index = INDEX(priv->port);
/* Enable preamble checking */
gmxx_rxx_frm_ctl.u64 =
cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));
gmxx_rxx_frm_ctl.s.pre_chk = 1;
cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface),
gmxx_rxx_frm_ctl.u64);
/* Enable FCS stripping */
ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
ipd_sub_port_fcs.s.port_bit |= 1ull << priv->port;
cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
/* Clear any error bits */
gmxx_rxx_int_reg.u64 =
cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, interface));
cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface),
gmxx_rxx_int_reg.u64);
}
if (priv->phydev == NULL) {
link_info = cvmx_helper_link_autoconf(priv->port);
priv->link_info = link_info.u64;
}
if (use_global_register_lock)
spin_unlock_irqrestore(&global_register_lock, flags);
else {
mutex_unlock(&priv->phydev->bus->mdio_lock);
}
if (priv->phydev == NULL) {
/* Tell core. */
if (link_info.s.link_up) {
if (!netif_carrier_ok(dev))
netif_carrier_on(dev);
if (priv->queue != -1)
printk_ratelimited("%s: %u Mbps %s duplex, "
"port %2d, queue %2d\n",
dev->name, link_info.s.speed,
(link_info.s.full_duplex) ?
"Full" : "Half",
priv->port, priv->queue);
else
printk_ratelimited("%s: %u Mbps %s duplex, "
"port %2d, POW\n",
dev->name, link_info.s.speed,
(link_info.s.full_duplex) ?
"Full" : "Half",
priv->port);
} else {
if (netif_carrier_ok(dev))
netif_carrier_off(dev);
printk_ratelimited("%s: Link down\n", dev->name);
}
}
}
/**
* @INTERNAL
* Configure all of the ASX, GMX, and PKO regsiters required
* to get RGMII to function on the supplied interface.
*
* @param interface PKO Interface to configure (0 or 1)
*
* @return Zero on success
*/
int __cvmx_helper_rgmii_enable(int interface)
{
int num_ports = cvmx_helper_ports_on_interface(interface);
int port;
cvmx_gmxx_inf_mode_t mode;
cvmx_asxx_tx_prt_en_t asx_tx;
cvmx_asxx_rx_prt_en_t asx_rx;
mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
if (mode.s.en == 0)
return -1;
if ((OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) && mode.s.type == 1) /* Ignore SPI interfaces */
return -1;
/* Configure the ASX registers needed to use the RGMII ports */
asx_tx.u64 = 0;
asx_tx.s.prt_en = cvmx_build_mask(num_ports);
cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64);
asx_rx.u64 = 0;
asx_rx.s.prt_en = cvmx_build_mask(num_ports);
cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64);
/* Configure the GMX registers needed to use the RGMII ports */
for (port=0; port<num_ports; port++)
{
/* Setting of CVMX_GMXX_TXX_THRESH has been moved to
__cvmx_helper_setup_gmx() */
/* Configure more flexible RGMII preamble checking. Pass 1 doesn't
support this feature. */
cvmx_gmxx_rxx_frm_ctl_t frm_ctl;
frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface));
frm_ctl.s.pre_free = 1; /* New field, so must be compile time */
cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface), frm_ctl.u64);
/* Each pause frame transmitted will ask for about 10M bit times
before resume. If buffer space comes available before that time
has expired, an XON pause frame (0 time) will be transmitted to
restart the flow. */
cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_TIME(port, interface), 20000);
cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(port, interface), 19000);
/*
* Board types we have to know at compile-time.
*/
#if defined(OCTEON_BOARD_CAPK_0100ND)
cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 26);
cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), 26);
#else
/*
* Vendor-defined board types.
*/
#if defined(OCTEON_VENDOR_LANNER)
switch (cvmx_sysinfo_get()->board_type) {
case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
case CVMX_BOARD_TYPE_CUST_LANNER_MR321X:
if (port == 0) {
cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 4);
} else {
cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 7);
}
cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), 0);
break;
}
#else
/*
* For board types we can determine at runtime.
*/
if (OCTEON_IS_MODEL(OCTEON_CN50XX))
{
cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 16);
cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), 16);
}
else
{
cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 24);
cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), 24);
}
#endif
#endif
}
__cvmx_helper_setup_gmx(interface, num_ports);
/* enable the ports now */
for (port=0; port<num_ports; port++)
{
cvmx_gmxx_prtx_cfg_t gmx_cfg;
cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port(interface, port));
gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface));
gmx_cfg.s.en = 1;
cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface), gmx_cfg.u64);
}
return 0;
}
static void cvm_oct_rgmii_poll(struct ifnet *ifp)
{
cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc;
cvmx_helper_link_info_t link_info;
/* Take the global register lock since we are going to touch
registers that affect more than one port */
mtx_lock_spin(&global_register_lock);
link_info = cvmx_helper_link_get(priv->port);
if (link_info.u64 == priv->link_info) {
/* If the 10Mbps preamble workaround is supported and we're
at 10Mbps we may need to do some special checking */
if (USE_10MBPS_PREAMBLE_WORKAROUND && (link_info.s.speed == 10)) {
/* Read the GMXX_RXX_INT_REG[PCTERR] bit and
see if we are getting preamble errors */
int interface = INTERFACE(priv->port);
int index = INDEX(priv->port);
cvmx_gmxx_rxx_int_reg_t gmxx_rxx_int_reg;
gmxx_rxx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, interface));
if (gmxx_rxx_int_reg.s.pcterr) {
/* We are getting preamble errors at 10Mbps.
Most likely the PHY is giving us packets
with mis aligned preambles. In order to get
these packets we need to disable preamble
checking and do it in software */
cvmx_gmxx_rxx_frm_ctl_t gmxx_rxx_frm_ctl;
cvmx_ipd_sub_port_fcs_t ipd_sub_port_fcs;
/* Disable preamble checking */
gmxx_rxx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));
gmxx_rxx_frm_ctl.s.pre_chk = 0;
cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface), gmxx_rxx_frm_ctl.u64);
/* Disable FCS stripping */
ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
ipd_sub_port_fcs.s.port_bit &= 0xffffffffull ^ (1ull<<priv->port);
cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
/* Clear any error bits */
cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface), gmxx_rxx_int_reg.u64);
DEBUGPRINT("%s: Using 10Mbps with software preamble removal\n", if_name(ifp));
}
}
mtx_unlock_spin(&global_register_lock);
return;
}
/* If the 10Mbps preamble workaround is allowed we need to on
preamble checking, FCS stripping, and clear error bits on
every speed change. If errors occur during 10Mbps operation
the above code will change this stuff */
if (USE_10MBPS_PREAMBLE_WORKAROUND) {
cvmx_gmxx_rxx_frm_ctl_t gmxx_rxx_frm_ctl;
cvmx_ipd_sub_port_fcs_t ipd_sub_port_fcs;
cvmx_gmxx_rxx_int_reg_t gmxx_rxx_int_reg;
int interface = INTERFACE(priv->port);
int index = INDEX(priv->port);
/* Enable preamble checking */
gmxx_rxx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));
gmxx_rxx_frm_ctl.s.pre_chk = 1;
cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface), gmxx_rxx_frm_ctl.u64);
/* Enable FCS stripping */
ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
ipd_sub_port_fcs.s.port_bit |= 1ull<<priv->port;
cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
/* Clear any error bits */
gmxx_rxx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, interface));
cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface), gmxx_rxx_int_reg.u64);
}
if (priv->miibus == NULL) {
link_info = cvmx_helper_link_autoconf(priv->port);
priv->link_info = link_info.u64;
priv->need_link_update = 1;
}
mtx_unlock_spin(&global_register_lock);
}
/**
* Configure all of the ASX, GMX, and PKO regsiters required
* to get RGMII to function on the supplied interface.
*
* @interface: PKO Interface to configure (0 or 1)
*
* Returns Zero on success
*/
int __cvmx_helper_rgmii_enable(int interface)
{
int num_ports = cvmx_helper_ports_on_interface(interface);
int port;
struct cvmx_sysinfo *sys_info_ptr = cvmx_sysinfo_get();
union cvmx_gmxx_inf_mode mode;
union cvmx_asxx_tx_prt_en asx_tx;
union cvmx_asxx_rx_prt_en asx_rx;
mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
if (mode.s.en == 0)
return -1;
if ((OCTEON_IS_MODEL(OCTEON_CN38XX) ||
OCTEON_IS_MODEL(OCTEON_CN58XX)) && mode.s.type == 1)
/* Ignore SPI interfaces */
return -1;
/* Configure the ASX registers needed to use the RGMII ports */
asx_tx.u64 = 0;
asx_tx.s.prt_en = cvmx_build_mask(num_ports);
cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64);
asx_rx.u64 = 0;
asx_rx.s.prt_en = cvmx_build_mask(num_ports);
cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64);
/* Configure the GMX registers needed to use the RGMII ports */
for (port = 0; port < num_ports; port++) {
/* Setting of CVMX_GMXX_TXX_THRESH has been moved to
__cvmx_helper_setup_gmx() */
if (cvmx_octeon_is_pass1())
__cvmx_helper_errata_asx_pass1(interface, port,
sys_info_ptr->
cpu_clock_hz);
else {
/*
* Configure more flexible RGMII preamble
* checking. Pass 1 doesn't support this
* feature.
*/
union cvmx_gmxx_rxx_frm_ctl frm_ctl;
frm_ctl.u64 =
cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL
(port, interface));
/* New field, so must be compile time */
frm_ctl.s.pre_free = 1;
cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface),
frm_ctl.u64);
}
/*
* Each pause frame transmitted will ask for about 10M
* bit times before resume. If buffer space comes
* available before that time has expired, an XON
* pause frame (0 time) will be transmitted to restart
* the flow.
*/
cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_TIME(port, interface),
20000);
cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL
(port, interface), 19000);
if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface),
16);
cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface),
16);
} else {
cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface),
24);
cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface),
24);
}
}
__cvmx_helper_setup_gmx(interface, num_ports);
/* enable the ports now */
for (port = 0; port < num_ports; port++) {
union cvmx_gmxx_prtx_cfg gmx_cfg;
cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port
(interface, port));
gmx_cfg.u64 =
cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface));
gmx_cfg.s.en = 1;
cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface),
gmx_cfg.u64);
}
__cvmx_interrupt_asxx_enable(interface);
__cvmx_interrupt_gmxx_enable(interface);
return 0;
}
static void cvm_oct_rgmii_poll(struct net_device *dev)
{
struct octeon_ethernet *priv = netdev_priv(dev);
unsigned long flags;
cvmx_helper_link_info_t link_info;
spin_lock_irqsave(&global_register_lock, flags);
link_info = cvmx_helper_link_get(priv->port);
if (link_info.u64 == priv->link_info) {
if (USE_10MBPS_PREAMBLE_WORKAROUND && (link_info.s.speed == 10)) {
int interface = INTERFACE(priv->port);
int index = INDEX(priv->port);
union cvmx_gmxx_rxx_int_reg gmxx_rxx_int_reg;
gmxx_rxx_int_reg.u64 =
cvmx_read_csr(CVMX_GMXX_RXX_INT_REG
(index, interface));
if (gmxx_rxx_int_reg.s.pcterr) {
union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl;
union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs;
gmxx_rxx_frm_ctl.u64 =
cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL
(index, interface));
gmxx_rxx_frm_ctl.s.pre_chk = 0;
cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL
(index, interface),
gmxx_rxx_frm_ctl.u64);
ipd_sub_port_fcs.u64 =
cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
ipd_sub_port_fcs.s.port_bit &=
0xffffffffull ^ (1ull << priv->port);
cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS,
ipd_sub_port_fcs.u64);
cvmx_write_csr(CVMX_GMXX_RXX_INT_REG
(index, interface),
gmxx_rxx_int_reg.u64);
DEBUGPRINT("%s: Using 10Mbps with software "
"preamble removal\n",
dev->name);
}
}
spin_unlock_irqrestore(&global_register_lock, flags);
return;
}
if (USE_10MBPS_PREAMBLE_WORKAROUND) {
union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl;
union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs;
union cvmx_gmxx_rxx_int_reg gmxx_rxx_int_reg;
int interface = INTERFACE(priv->port);
int index = INDEX(priv->port);
gmxx_rxx_frm_ctl.u64 =
cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));
gmxx_rxx_frm_ctl.s.pre_chk = 1;
cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface),
gmxx_rxx_frm_ctl.u64);
ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
ipd_sub_port_fcs.s.port_bit |= 1ull << priv->port;
cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
gmxx_rxx_int_reg.u64 =
cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, interface));
cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface),
gmxx_rxx_int_reg.u64);
}
link_info = cvmx_helper_link_autoconf(priv->port);
priv->link_info = link_info.u64;
spin_unlock_irqrestore(&global_register_lock, flags);
if (link_info.s.link_up) {
if (!netif_carrier_ok(dev))
netif_carrier_on(dev);
if (priv->queue != -1)
DEBUGPRINT
("%s: %u Mbps %s duplex, port %2d, queue %2d\n",
dev->name, link_info.s.speed,
(link_info.s.full_duplex) ? "Full" : "Half",
priv->port, priv->queue);
else
DEBUGPRINT("%s: %u Mbps %s duplex, port %2d, POW\n",
dev->name, link_info.s.speed,
(link_info.s.full_duplex) ? "Full" : "Half",
priv->port);
} else {
if (netif_carrier_ok(dev))
netif_carrier_off(dev);
DEBUGPRINT("%s: Link down\n", dev->name);
}
}