static void m68hc11sio_info (struct hw *me) { SIM_DESC sd; uint16 base = 0; sim_cpu *cpu; struct m68hc11sio *controller; uint8 val; long clock_cycle; sd = hw_system (me); cpu = STATE_CPU (sd, 0); controller = hw_data (me); sim_io_printf (sd, "M68HC11 SIO:\n"); base = cpu_get_io_base (cpu); val = cpu->ios[M6811_BAUD]; print_io_byte (sd, "BAUD ", baud_desc, val, base + M6811_BAUD); sim_io_printf (sd, " (%ld baud)\n", (cpu->cpu_frequency / 4) / controller->baud_cycle); val = cpu->ios[M6811_SCCR1]; print_io_byte (sd, "SCCR1", sccr1_desc, val, base + M6811_SCCR1); sim_io_printf (sd, " (%d bits) (%dN1)\n", controller->data_length, controller->data_length - 2); val = cpu->ios[M6811_SCCR2]; print_io_byte (sd, "SCCR2", sccr2_desc, val, base + M6811_SCCR2); sim_io_printf (sd, "\n"); val = cpu->ios[M6811_SCSR]; print_io_byte (sd, "SCSR ", scsr_desc, val, base + M6811_SCSR); sim_io_printf (sd, "\n"); clock_cycle = controller->data_length * controller->baud_cycle; if (controller->tx_poll_event) { signed64 t; int n; t = hw_event_remain_time (me, controller->tx_poll_event); n = (clock_cycle - t) / controller->baud_cycle; n = controller->data_length - n; sim_io_printf (sd, " Transmit finished in %s (%d bit%s)\n", cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE), n, (n > 1 ? "s" : "")); } if (controller->rx_poll_event) { signed64 t; t = hw_event_remain_time (me, controller->rx_poll_event); sim_io_printf (sd, " Receive finished in %s\n", cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE)); } }
void interrupts_info (SIM_DESC sd, struct interrupts *interrupts) { signed64 t; sim_io_printf (sd, "Interrupts Info:\n"); sim_io_printf (sd, " Interrupts raised: %lu\n", interrupts->nb_interrupts_raised); if (interrupts->start_mask_cycle >= 0) { t = cpu_current_cycle (interrupts->cpu); t -= interrupts->start_mask_cycle; if (t > interrupts->max_mask_cycles) interrupts->max_mask_cycles = t; sim_io_printf (sd, " Current interrupts masked sequence: %s\n", cycle_to_string (interrupts->cpu, t)); } t = interrupts->min_mask_cycles == CYCLES_MAX ? interrupts->max_mask_cycles : interrupts->min_mask_cycles; sim_io_printf (sd, " Shortest interrupts masked sequence: %s\n", cycle_to_string (interrupts->cpu, t)); t = interrupts->max_mask_cycles; sim_io_printf (sd, " Longest interrupts masked sequence: %s\n", cycle_to_string (interrupts->cpu, t)); t = interrupts->last_mask_cycles; sim_io_printf (sd, " Last interrupts masked sequence: %s\n", cycle_to_string (interrupts->cpu, t)); if (interrupts->xirq_start_mask_cycle >= 0) { t = cpu_current_cycle (interrupts->cpu); t -= interrupts->xirq_start_mask_cycle; if (t > interrupts->xirq_max_mask_cycles) interrupts->xirq_max_mask_cycles = t; sim_io_printf (sd, " XIRQ Current interrupts masked sequence: %s\n", cycle_to_string (interrupts->cpu, t)); } t = interrupts->xirq_min_mask_cycles == CYCLES_MAX ? interrupts->xirq_max_mask_cycles : interrupts->xirq_min_mask_cycles; sim_io_printf (sd, " XIRQ Min interrupts masked sequence: %s\n", cycle_to_string (interrupts->cpu, t)); t = interrupts->xirq_max_mask_cycles; sim_io_printf (sd, " XIRQ Max interrupts masked sequence: %s\n", cycle_to_string (interrupts->cpu, t)); t = interrupts->xirq_last_mask_cycles; sim_io_printf (sd, " XIRQ Last interrupts masked sequence: %s\n", cycle_to_string (interrupts->cpu, t)); }
static void m68hc11spi_info (struct hw *me) { SIM_DESC sd; uint16 base = 0; sim_cpu *cpu; struct m68hc11spi *controller; uint8 val; sd = hw_system (me); cpu = STATE_CPU (sd, 0); controller = hw_data (me); sim_io_printf (sd, "M68HC11 SPI:\n"); base = cpu_get_io_base (cpu); val = cpu->ios[M6811_SPCR]; print_io_byte (sd, "SPCR", spcr_desc, val, base + M6811_SPCR); sim_io_printf (sd, "\n"); val = cpu->ios[M6811_SPSR]; print_io_byte (sd, "SPSR", spsr_desc, val, base + M6811_SPSR); sim_io_printf (sd, "\n"); if (controller->spi_event) { signed64 t; sim_io_printf (sd, " SPI has %d bits to send\n", controller->tx_bit + 1); t = hw_event_remain_time (me, controller->spi_event); sim_io_printf (sd, " SPI current bit-cycle finished in %s\n", cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE)); t += (controller->tx_bit + 1) * 2 * controller->clock; sim_io_printf (sd, " SPI operation finished in %s\n", cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE)); } }
static void m68hc11tim_print_timer (struct hw *me, const char *name, struct hw_event *event) { SIM_DESC sd; sd = hw_system (me); if (event == 0) { sim_io_printf (sd, " No %s interrupt will be raised.\n", name); } else { signed64 t; sim_cpu *cpu; cpu = STATE_CPU (sd, 0); t = hw_event_remain_time (me, event); sim_io_printf (sd, " Next %s interrupt in %s\n", name, cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE)); } }
void interrupts_info (SIM_DESC sd, struct interrupts *interrupts) { signed64 t, prev_interrupt; int i; sim_io_printf (sd, "Interrupts Info:\n"); sim_io_printf (sd, " Interrupts raised: %lu\n", interrupts->nb_interrupts_raised); if (interrupts->start_mask_cycle >= 0) { t = cpu_current_cycle (interrupts->cpu); t -= interrupts->start_mask_cycle; if (t > interrupts->max_mask_cycles) interrupts->max_mask_cycles = t; sim_io_printf (sd, " Current interrupts masked sequence: %s\n", cycle_to_string (interrupts->cpu, t, PRINT_TIME | PRINT_CYCLE)); } t = interrupts->min_mask_cycles == CYCLES_MAX ? interrupts->max_mask_cycles : interrupts->min_mask_cycles; sim_io_printf (sd, " Shortest interrupts masked sequence: %s\n", cycle_to_string (interrupts->cpu, t, PRINT_TIME | PRINT_CYCLE)); t = interrupts->max_mask_cycles; sim_io_printf (sd, " Longest interrupts masked sequence: %s\n", cycle_to_string (interrupts->cpu, t, PRINT_TIME | PRINT_CYCLE)); t = interrupts->last_mask_cycles; sim_io_printf (sd, " Last interrupts masked sequence: %s\n", cycle_to_string (interrupts->cpu, t, PRINT_TIME | PRINT_CYCLE)); if (interrupts->xirq_start_mask_cycle >= 0) { t = cpu_current_cycle (interrupts->cpu); t -= interrupts->xirq_start_mask_cycle; if (t > interrupts->xirq_max_mask_cycles) interrupts->xirq_max_mask_cycles = t; sim_io_printf (sd, " XIRQ Current interrupts masked sequence: %s\n", cycle_to_string (interrupts->cpu, t, PRINT_TIME | PRINT_CYCLE)); } t = interrupts->xirq_min_mask_cycles == CYCLES_MAX ? interrupts->xirq_max_mask_cycles : interrupts->xirq_min_mask_cycles; sim_io_printf (sd, " XIRQ Min interrupts masked sequence: %s\n", cycle_to_string (interrupts->cpu, t, PRINT_TIME | PRINT_CYCLE)); t = interrupts->xirq_max_mask_cycles; sim_io_printf (sd, " XIRQ Max interrupts masked sequence: %s\n", cycle_to_string (interrupts->cpu, t, PRINT_TIME | PRINT_CYCLE)); t = interrupts->xirq_last_mask_cycles; sim_io_printf (sd, " XIRQ Last interrupts masked sequence: %s\n", cycle_to_string (interrupts->cpu, t, PRINT_TIME | PRINT_CYCLE)); if (interrupts->pending_mask) { sim_io_printf (sd, " Pending interrupts : "); for (i = 0; i < M6811_INT_NUMBER; i++) { enum M6811_INT int_number = interrupts->interrupt_order[i]; if (interrupts->pending_mask & (1 << int_number)) { sim_io_printf (sd, "%s ", interrupt_names[int_number]); } } sim_io_printf (sd, "\n"); } prev_interrupt = 0; sim_io_printf (sd, "N Interrupt Cycle Taken Latency" " Delta between interrupts\n"); for (i = 0; i < MAX_INT_HISTORY; i++) { int which; struct interrupt_history *h; signed64 dt; which = interrupts->history_index - i - 1; if (which < 0) which += MAX_INT_HISTORY; h = &interrupts->interrupts_history[which]; if (h->taken_cycle == 0) break; dt = h->taken_cycle - h->raised_cycle; sim_io_printf (sd, "%2d %-9.9s %15.15s ", i, interrupt_names[h->type], cycle_to_string (interrupts->cpu, h->taken_cycle, 0)); sim_io_printf (sd, "%15.15s", cycle_to_string (interrupts->cpu, dt, 0)); if (prev_interrupt) { dt = prev_interrupt - h->taken_cycle; sim_io_printf (sd, " %s", cycle_to_string (interrupts->cpu, dt, PRINT_TIME)); } sim_io_printf (sd, "\n"); prev_interrupt = h->taken_cycle; } }