void
cyg_hal_plf_pci_init(void)
{
cyg_uint8 next_bus;
static int initialized = 0;
if (initialized) return;
initialized = 1;
// Set PCI bases
HAL_WRITE_UINT32(CYGARC_REG_PCI_IO_MEMOFFSET, CYGARC_BUS_ADDRESS(HAL_PCI_ALLOC_BASE_IO));
HAL_WRITE_UINT32(CYGARC_REG_PCI_MEM_MEMOFFSET, CYGARC_BUS_ADDRESS(HAL_PCI_ALLOC_BASE_MEMORY));
// Reset PCI - this does not have the desired effect; devices remain enabled.
HAL_WRITE_UINT32(CYGARC_REG_SD0001_RESET, CYGARC_REG_SD0001_RESET_PCIRST);
CYGACC_CALL_IF_DELAY_US(100);
// Bring PCI out of reset
HAL_WRITE_UINT32(CYGARC_REG_SD0001_RESET, 0);
CYGACC_CALL_IF_DELAY_US(10000);
// Set PCI access timeouts/retries to max
HAL_WRITE_UINT32(CYGARC_REG_SD0001_PCI_CTL, (CYGARC_REG_SD0001_PCI_CTL_MAX_DEADLOCK_CNT
|CYGARC_REG_SD0001_PCI_CTL_MAX_RETRY_CNT));
CYGACC_CALL_IF_DELAY_US(10000);
// Enable controller
// Setup for bus mastering
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
// Setup latency timer field
cyg_hal_plf_pci_cfg_write_byte(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 32);
// Set memory base
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_1, 0x0c000008);
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
void cyg_hal_plf_pci_init(void)
{
cyg_uint32 bar_ena, start10, start32, end, size;
cyg_uint8 next_bus;
// Program PCI window in CPU address space and CPU->PCI remap
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIMEM0_LD_OFFSET,
HAL_OCELOT_PCI_MEM0_BASE >> HAL_GALILEO_CPU_DECODE_SHIFT);
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIMEM0_HD_OFFSET,
(HAL_OCELOT_PCI_MEM0_BASE+HAL_OCELOT_PCI_MEM0_SIZE-1) >> HAL_GALILEO_CPU_DECODE_SHIFT);
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIMEM1_LD_OFFSET,
HAL_OCELOT_PCI_MEM1_BASE >> HAL_GALILEO_CPU_DECODE_SHIFT);
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIMEM1_HD_OFFSET,
(HAL_OCELOT_PCI_MEM1_BASE+HAL_OCELOT_PCI_MEM1_SIZE-1) >> HAL_GALILEO_CPU_DECODE_SHIFT);
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIIO_LD_OFFSET,
HAL_OCELOT_PCI_IO_BASE >> HAL_GALILEO_CPU_DECODE_SHIFT);
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIIO_HD_OFFSET,
(HAL_OCELOT_PCI_IO_BASE+HAL_OCELOT_PCI_IO_SIZE-1) >> HAL_GALILEO_CPU_DECODE_SHIFT);
// Setup for bus mastering
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_IO |
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
// Setup latency timer field
cyg_hal_plf_pci_cfg_write_byte(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 6);
// Disable all BARs
bar_ena = 0x1ff;
// Allow PCI bus to access local memory
// Check for active SCS10
start10 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_LD_OFFSET) << HAL_GALILEO_CPU_DECODE_SHIFT;
end = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_HD_OFFSET) & 0x7f) + 1) << HAL_GALILEO_CPU_DECODE_SHIFT;
if (end > start10) {
if ((size = __check_bar(start10, end - start10)) != 0) {
// Enable BAR
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS10_SIZE_OFFSET, size);
bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10;
}
}
// Check for active SCS32
start32 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_LD_OFFSET) << HAL_GALILEO_CPU_DECODE_SHIFT;
end = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_HD_OFFSET) & 0x7f) + 1) << HAL_GALILEO_CPU_DECODE_SHIFT;
if (end > start32) {
if ((size = __check_bar(start32, end - start32)) != 0) {
// Enable BAR
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS32_SIZE_OFFSET, size);
bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS32;
}
}
bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10;
HAL_GALILEO_PUTREG(HAL_GALILEO_BAR_ENA_OFFSET, bar_ena);
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0, 0xffffffff);
end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0);
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0, start10);
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_1, 0xffffffff);
end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_1);
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_1, start32);
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
