static cyg_uint32 isr0(cyg_vector_t vector, cyg_addrword_t data)
{
CYG_UNUSED_PARAM(cyg_addrword_t, data);
cyg_interrupt_acknowledge(vector);
return 0;
}
/*Handler d'IT*/
cyg_uint32 dev_linux_com0_isr(cyg_vector_t vector, cyg_addrword_t data)
{
/*Blocage d'une IT similaire tant que la DSR ne sait pas exécutée*/
cyg_interrupt_mask(vector);
u_int32 _usart_csr;
u_int32 _usart_imr;
if(_linux_uart_s0_loaded) {
do {
send_order_r('R', US_CSR, &_usart_csr);
send_order_r('R', US_IMR, &_usart_imr);
if((_usart_csr&IER_MASK_RCV)==IER_MASK_RCV) {
//dev_linux_com0_read(_linux_uart_s0_desc_rd, uart_0_rcv_buffer, 1);
dev_linux_com0_rcv();
}
if((_usart_csr&IER_MASK_SND)==IER_MASK_SND) {
dev_linux_com0_snd();
}
} while((_usart_csr & _usart_imr & (IER_MASK_RCV)) ||
(_usart_csr & _usart_imr & (IER_MASK_SND)) );
}
/*ACK de l'IT au CPU*/
cyg_interrupt_acknowledge(vector);
/*Informe kernel d'exécuter DSR*/
return(CYG_ISR_HANDLED | CYG_ISR_CALL_DSR);
}
void Int_Handler_FastI2C(void)
#endif
{
unsigned int intst;
intst=inpw(REG_FastSerialBusStatus);
if ((intst&0x00000002)==0x02)
{
//k07055-1 if (_i2c_IrqHandlerTable[0]!=0)
//k07055-1 _i2c_IrqHandlerTable[0]();
intst=inpw(REG_FastSerialBusStatus)|0x02;
outpw(REG_FastSerialBusStatus,intst);
++i2c_I2C_INT_CNT;
// printf ("i2c_I2C_INT_CNT = %d\n", i2c_I2C_INT_CNT);
if (_i2c_IrqHandlerTable[0]!=0) //k07055-1
_i2c_IrqHandlerTable[0](); //k07055-1
//#ifdef OPT_FastI2C_INT_TEST
// cntFastI2C=cntFastI2C+1;
//#endif //OPT_FastI2C_INT_TEST
}
#ifdef ECOS
cyg_interrupt_acknowledge (vector); //k01105-1
return CYG_ISR_HANDLED;
#endif //ECOS
}
cyg_uint32 dev_at91sam9261_isr(cyg_vector_t vector, cyg_addrword_t data)
{
volatile unsigned int spi_sr;
cyg_interrupt_mask(vector);
// le driver est il deja charge?
if (dev_at91sam9261_spi_loaded)
{
//lecture du registre d'etat pour connaitre l'origine de l'IT
spi_sr = *AT91C_SPI0_SR;
//est ce une it de fin d'emission?
if (spi_sr & AT91C_SPI_ENDTX)
{
// desactivation de l'emetteur et du récepteur
*AT91C_SPI0_PTCR = AT91C_PDC_RXTDIS| AT91C_PDC_TXTDIS;
//desactivation de l'it ENDTX
*AT91C_SPI0_IDR = AT91C_SPI_ENDTX;
}
}
//ACK de l'IT au CPU
cyg_interrupt_acknowledge(vector);
//appel du DSR
return(CYG_ISR_HANDLED | CYG_ISR_CALL_DSR);
}
cyg_uint32 Reset_INT_Handler(cyg_vector_t vector, cyg_addrword_t data)
{
/* clear GPIO interrupt state */
//diag_printf("state: %08x\n", inpw(REG_GPIO_IS));
Reset_Int_ISR_MP4EVB_Board();
cyg_interrupt_acknowledge(vector);
return CYG_ISR_HANDLED;
}
/*-------------------------------------------
| Name:_kinetis_uart_isr
| Description:
| Parameters:
| Return Type:
| Comments:
| See:
---------------------------------------------*/
cyg_uint32 _kinetis_uart_x_isr(cyg_vector_t vector, cyg_addrword_t data) {
cyg_interrupt_mask(vector);
cyg_interrupt_acknowledge(vector);
_kinetis_uart_stat.isr++;
return CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
}
cyg_uint32 dev_at91sam9261_uart_isr(cyg_vector_t vector, cyg_addrword_t data) {
cyg_interrupt_mask(vector);
dev_at91sam9261_uart_x_interrupt((board_inf_uart_t*)data);
cyg_interrupt_acknowledge(vector);
//Informe kernel d'exécuter DSR
return(CYG_ISR_HANDLED | CYG_ISR_CALL_DSR);
}
/*-------------------------------------------
| Name : dev_at91sam9260_uart1_isr
| Description:
| Parameters : None
| Return Type: None
| Comments : -
| See : -
---------------------------------------------*/
cyg_uint32 dev_at91sam9260_uart1_isr(cyg_vector_t vector, cyg_addrword_t data)
{
cyg_interrupt_mask(vector);
unsigned int usart_csr;
unsigned int recv_intr_cond = 0;
unsigned int trans_intr_cond = 0;
board_inf_uart_t *p_inf_uart;
AT91S_USART *p_adr;
p_inf_uart = (board_inf_uart_t *)ofile_lst[desc_uart1].p;
p_adr = (AT91S_USART*)p_inf_uart->base_adr;
// if device is loaded
if (p_inf_uart->loaded) {
do {
usart_csr = p_adr->US_CSR;
if (p_inf_uart->o_flag & O_RDONLY) {
// Overrun Error
if ((usart_csr & 0x00000020) == 0x00000020) {
// Reset status bits, reset rx/tx.
p_adr->US_CR = AT91C_US_RSTSTA;
}
// Receiver byte per byte
if ((usart_csr & 0x01) == 0x01) { // RXRDY
//receive fifo
dev_at91sam9260_uart_x_fifo_rcv(desc_uart1);
}
recv_intr_cond = usart_csr & (p_adr->US_IMR) & (0x00000001);
}
//
if (p_inf_uart->o_flag & O_WRONLY) {
// TXRDY
if (((usart_csr & 0x00000002) == 0x00000002) && (p_inf_uart->XMIT)) {
//Transmission (per byte)
dev_at91sam9260_uart_x_snd(desc_uart1);
}
trans_intr_cond = ( (p_inf_uart->XMIT) && (usart_csr & (p_adr->US_IMR) & (0x00000002)));
}
} while ( recv_intr_cond || trans_intr_cond );
}
// Timer Value initialization for Read
p_inf_uart->inter_char_timer = p_inf_uart->ttys_termios.c_cc[VTIME];
//ACK de l'IT au CPU
cyg_interrupt_acknowledge(vector);
//Informe kernel d'ex�cuter DSR
return(CYG_ISR_HANDLED | CYG_ISR_CALL_DSR);
}
// This DSR handles the board insertion
static void
cf_detect_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
unsigned long new_state = *SA11X0_GPIO_PIN_LEVEL;
struct cf_slot *slot = (struct cf_slot *)data;
if ((new_state & SA1110_GPIO_CF_DETECT) == SA1110_GPIO_CF_PRESENT) {
slot->state = CF_SLOT_STATE_Inserted;
} else {
slot->state = CF_SLOT_STATE_Removed; // Implies powered up, etc.
}
cyg_interrupt_acknowledge(SA1110_CF_DETECT);
cyg_interrupt_unmask(SA1110_CF_DETECT);
}
cyg_uint32 dev_linux_eth_isr(cyg_vector_t vector, cyg_addrword_t data) {
//Blocage d'une IT similaire tant que la DSR ne sait pas exécutée
cyg_interrupt_mask(vector);
//
if(data==OPS_READ) {
dev_linux_eth_rcv();
}
if(data==OPS_WRITE) {
dev_linux_eth_snd();
}
//ACK de l'IT au CPU
cyg_interrupt_acknowledge(vector);
//Informe kernel d'exécuter DSR
return(CYG_ISR_HANDLED | CYG_ISR_CALL_DSR);
}
cyg_uint32
keyb_isr_handler(cyg_vector_t vector, cyg_addrword_t data)
{
cyg_interrupt_acknowledge(vector);
// Read Keyboard status
cyg_uint8 kbstat, code = 0;
HAL_READ_UINT8( KBSTATPORT, kbstat );
// If Data available, read them -> implicitly acknowledges interrupt on hardware side!
if( (kbstat & 0x01) != 0 ){
HAL_READ_UINT8( KBDATAPORT, code );
g_keycode = code;
// Only resume thread, if there is a new keycode.
return CYG_ISR_CALL_DSR | CYG_ISR_HANDLED;
}
return CYG_ISR_HANDLED;
}
void capIntHandler(void)
#endif
{
UCHAR ucBuf;
#ifdef ECOS
cyg_interrupt_mask(vector);
#endif
_cap_uFrame=_cap_uFrame+1;
if(inpw(REG_CAPFuncEnable)&0x10)
{//Dual Buffer enable
if(inpw(REG_CAPFuncEnable)&0x40)
{//will use the buffer 0 for VPOST & JPEG
outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)&0xffffff9F);
ucBuf=0;
}
else
{//will use the buffer 1 for VPOST & JPEG
outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)|0x00000060);
ucBuf=1;
}
}
//Call back to the function written by user.
outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable));
#ifndef ECOS
if(CapIntHandlerTable[0]!=0)
{
UCHAR ucfr;
ucfr=(inpw(REG_CAPFuncEnable)&0x04) ? TRUE:FALSE;
CapIntHandlerTable[0](ucBuf,ucBuf,ucfr, FALSE);
}
#endif
#ifdef ECOS
cyg_interrupt_acknowledge(vector); //important
return CYG_ISR_CALL_DSR;
#endif
}
// Serial I/O - low level interrupt handler (ISR)
static cyg_uint32 ra305x_timer0_isr(cyg_vector_t vector, cyg_addrword_t data)
{
cyg_interrupt_mask(CYGNUM_HAL_INTERRUPT_TIMER0);
cyg_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_TIMER0);
return CYG_ISR_CALL_DSR; // Cause DSR to be run
}
cyg_uint32 dev_at91sam9261_uart_dbg_isr(cyg_vector_t vector, cyg_addrword_t data) {
cyg_interrupt_mask(vector);
unsigned int usart_csr;
unsigned int recv_intr_cond = 0;
unsigned int trans_intr_cond = 0;
board_inf_uart_t *p_inf_uart;
AT91_REG *p_adr;
desc_t desc_r;
desc_t desc_w;
p_inf_uart = (board_inf_uart_t *)ofile_lst[desc_uart_dbg].p;
p_adr = (AT91_REG *)p_inf_uart->base_adr;
desc_r = p_inf_uart->desc_r;
desc_w = p_inf_uart->desc_w;
// if device is loaded
if (p_inf_uart->loaded) {
do {
usart_csr = *(p_adr+US_CSR);
if( (desc_r>=0) && (ofile_lst[desc_r].oflag & O_RDONLY) ) {
// Overrun Error
if ((usart_csr & 0x00000020) == 0x00000020) {
// Reset status bits, reset rx/tx.
*(p_adr+US_CR) = AT91C_US_RSTSTA; // old value 0x00000100;
}
// Receiver byte per byte
if ((usart_csr & 0x01) == 0x01) // RXRDY
{
//receive fifo
dev_at91sam9261_uart_dbg_x_fifo_rcv(desc_uart_dbg);
}
recv_intr_cond = usart_csr & *(p_adr+US_IMR) & (0x00000001);
}
//
if( (desc_w>=0) && (ofile_lst[desc_w].oflag & O_WRONLY) ) {
// TXRDY
if (((usart_csr & 0x00000002) == 0x00000002) && (p_inf_uart->XMIT)) {
//Transmission (per byte)
//dev_at91sam9261_uart_x_snd(desc);
dev_at91sam9261_uart_dbg_x_snd(desc_uart_dbg);
}
//
trans_intr_cond = ( (p_inf_uart->XMIT) &&
(usart_csr & *(p_adr+US_IMR) & (0x00000002)));
}
} while ( recv_intr_cond || trans_intr_cond );
}
// Timer Value initialization for Read
p_inf_uart->inter_char_timer=ttys_termios.c_cc[VTIME];
//*AT91C_AIC_EOICR = 0; // Signal end of interrupt to AIC.
//ACK de l'IT au CPU
cyg_interrupt_acknowledge(vector);
//Informe kernel d'exécuter DSR
return(CYG_ISR_HANDLED | CYG_ISR_CALL_DSR);
}
